Features
•High P e rformance, Low Power 32-bit AVR® Micr ocon troller
– Compact Single-cycle RISC Instruction Set In cluding DSP Instru ction Set
– Built-in Floating-Point Processing Unit (FPU)
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.49 DMIPS / MHz
• Up to 91 DMIPS Runn in g at 66 MHz from Flash (1 Wait-State)
• Up to 49 DMIPS Runn in g at 33 MHz from Flash (0 Wait-State)
– Memory Protectio n Unit
•Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication
•Internal High-Speed Flash
– 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions
– Single Cycle Access up to 33 MHz
–FlashVault
™ Technology Allows Pre-programmed Secure Library Support for End
User Applications
– Prefetch Buffer Optimizing Instruction Ex ecution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
•Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB
Flash)
– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)
•External Memory Interface on AT32UC3C0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
•Interrupt Controller
– Autovectored Lo w Latency Interrupt Service with Programmable Priority
•System Functions
– Power and Clock Manager
– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators
– One 32 KHz and Two Multipurpose Oscillators
– Clock Failure detection
– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or
CAN Frequency
•Windowed Watchdog Timer (WDT)
•Asynchronous Timer (AST) with Real-Time Clock Capabil ity
– Counter or Calendar Mode Supported
•Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
•Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
•Universal Serial Bus (USB)
– Device 2.0 and Embedded Host Low Speed and Full Speed
– Flexible End-Point Config uration and Managemen t with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
•One 2-channel Controller Area Network (CAN)
– CAN2A and CAN2B protocol compliant, with high-level mailbox system 32117A–10/2010
32-bit AVR®
Microcontroller
AT32UC3C0512C
AT32UC3C0256C
AT32UC3C0128C
AT32UC3C064C
AT32UC3C1512C
AT32UC3C1256C
AT32UC3C1128C
AT32UC3C164C
AT32UC3C2512C
AT32UC3C2256C
AT32UC3C2128C
AT32UC3C264C
2
32117A–10/2010
AT32UC3C
– Two independent channels, 16 Message Objects per Channel
•One 4-Channel 20-bit Pulse Width Modulation Controller (PWM)
– Complementary outputs, with Dead Time Insertion
– Output Override and F a ul t Protection
•Two Quadrature Decoders
•One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC)
– Dual Sample and Hold Capability Allo wing 2 Synchronous Conversions
– Single-Ended and Differential Channels, Window Function
•Two 12-bit Digital-To-Analog Converters (DAC), with Dual Output Sample System
•Four Analog Comparators
•Six 16-bit Timer /C ounter (TC) Channels
– External Clock Inputs, PWM, Capture and Various Counting Capabilities
•One Peripheral Event Controller
– Trigger Actions in Peripherals Depending on Events Generated from Peripherals or from Input Pins
– Deterministic Trigger
– 34 Events and 22 Event Actions
•Five Universal Synchronous/Async hronous Receiver/Transmitters (USART)
– Independent Baudrate Generator, Support for SPI, LIN, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
•Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
•One Inter-IC Sound (I2S) Controller
– Compliant with I2S Bus Specification
– Time Division Multipl exed mode
•Three Master and Three Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible
•QTouch® Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
–QTouch
® and QMatrix® Acquisition
•On-Chip Non-intrusive Debug System
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
–aWire
™ single-pin programming trace and debug interface muxed with reset pin
– NanoTrace™ provides trace capabilities through JTAG or aWire interface
•3 package options
– 64-pin QFN/TQFP (45 GPI O pins)
– 100-pin TQFP (81 GPIO pins)
– 144-pin LQFP (123 GPIO pins)
•Two operating voltage ranges:
– Single 5V Power Supply
– Single 3.3V Power Supply
3
32117A–10/2010
AT32UC3C
1. Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC
processor running at frequencies up to 66 MHz. AVR32UC is a high-performance 32-bit RISC
microprocessor core , designed f or co st - sensit ive emb edded applicat ion s, with p ar ticular emph a-
sis on low power consumption, high code density and high performance.
The processor implements a M emory Protection Unit (MPU) and a fast a nd flexible interru pt con-
troller for supporting modern operating systems and real-time operating systems. Using the
Secure Access Unit (SAU) to gether with the MPU provides the required security and integrity.
Higher computation capabilities are achievable either using a rich set of DSP instructions or
using the floating-point instructions.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3C0 derivatives.
The Memory Direct Memo ry Access controller (MDMA) enables transfers of block of da ta from
memories to memories without processor involvement.
The Peripheral Direct Memory Access (PDCA) con troller ena bles data transfers betw een periph-
erals and mem ories without pr ocessor involvem ent. The PDCA dras tically reduces pr ocessing
overhead when tran sferring continuous and large data streams.
The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.
The FlashVault te chnology allows secure libra ries to be programme d into the device. The secure
libraries can be execute d wh ile th e CPU is in Secure Sta te , but no t r ead by non- se cu re software
in the device. The device can thus be shipped to end custumers, who are able to program their
own code into the device, accessing the secure libraries , without any risk of compromising th e
proprietary secure code.
The Power Manager improves design flexibility and security. Power monitoring is supp orted by
on-chip Power-On Reset (POR), Brown-Out Detectors (BOD18, BOD33, BOD50). The CPU
runs from the on-chip RC oscillators, the PLLs, or the Multipurpose Oscillators. The Asynchro-
nous Timer (AST) combined with the 32 KHz oscillator keeps track of the time. The AST can
operate in counter or calendar mode.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse gen eration, delay timing, and pulse width modulation.
The PWM module provides four channels with many configuratio n options including polarity,
edge alignment and waveform non overlap control. The PWM channels can operate indepen-
dently, with duty cycles set independently from each other, or in interlinked mode, with multiple
channels updated at the same time. It also includes safety feature with fault inputs and the ability
to lock the PWM configuration registers and the PWM pin assignment.
The AT32UC3C also features many communication interfaces for communication intensive
applications. In ad diti on t o stand ar d seri al int erfa ces like UART, SPI or TWI , ot he r int erface s like
flexible CAN, USB and Ethernet MAC are available. The USART supports different communica-
tion modes, like SPI mode and LIN mode.
The Inter-IC Sound Controller (I2 SC) provides a 5-bit wide, bidirectional, synchron ous, digital
audio link with off-chip audio devices. The controller is compliant with the I2S bus specification.
4
32117A–10/2010
AT32UC3C
The Full-Speed USB 2.0 Device interface supports several USB Classes at the same tim e
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the pr ocessor.
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.
The Peripheral Event Con troller (PEVC) allows to redirect events from one peripheral or from
input pins to another peripheral. It can then trigger, in a deterministic time, an action inside a
peripheral without the need of CPU. For instance a PWM waveform can directly trigger an ADC
capture, hence avoiding delays due to software interrupt processing.
The AT32UC3C featur es analo g function s like AD C, DAC, Ana log com parators . The ADC int er-
face is built around a 12-bit pipelined ADC core and is able to control two inde pendent 8-channel
or one 16-channel. The ADC block is able to measure two different voltages sampled at the
same time. The analog comparators can be paired to detect when the sensing voltage is within
or outside the defined reference window.
Atmel offers the QTouch lib rary for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR mi crocontrollers. The pate nted charge-transfe r signal acquisition o ffers
robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS®) technology for unambiguous detection of key even ts. The easy-to-use
QTouch Suite toolch ain allows you to explore, develop, and debug your own touch applications.
AT32UC3C integrates a class 2+ Nexus 2.0 On-Chip Debug (O CD) System, with non-intrusive
real-time trace , full-speed read/write memory a ccess in addition to basic runtime con trol. The
Nanotrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin
aWire interface allows all features available through the JTAG interface to be accessed through
the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals.
5
32117A–10/2010
AT32UC3C
2. Overview
2.1 Block diagram
Figure 2-1. Block diagram
supplied by VDDANA
supplied by VDDANA
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
GENERAL PURPOSE IOs
GENERAL PURPOSE IOs
PA
PB
PC
PD
PA
PB
PC
PD
USB
INTERFACE
ID
VBOF
VBUS
D-
D+
CANIF
32 KHz OSC
RCSYS
OSC0 / OSC1
PLL0 / PLL1
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TDI
RXLINE[0]
PB
PB
HSB HSB
TXLINE[0]
RXLINE[1]
TXCAN[1]
PERIPHERAL EVENT
CONTROLLER PAD_EVT
MM M
S
S
M
HIGH SPEED
BUS MATRIX
AVR32UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
MEMORY INTERFACE
64/32/16
KB SRAM
MEMORY PROTECTION UNIT
LOCAL BUS
INTERFACE
M
4 KB
HSB
RAM
S
S
EXTERNAL BUS INTERFACE
(SDRAM & STATIC MEMORY
CONTROLLER)
CAS
RAS
SDA10
SDCK
SDCKE
SDCS
SDWE
NCS[3..0]
NRD
NWAIT
NWE0
DATA[15..0]
ADDR[23..0]
NWE1
Memory
DMA
HSB-PB
BRIDGE C
PB
HSB
S
MS
M
CONFIGURATION REGISTERS BUS
PBB
SERIAL
PERIPHERAL
INTERFACE 1
DMA
MISO, MOSI
NPCS[3..0]
SCK
USART0
USART2
USART3
DMA
RXD
TXD
CLK
RTS, CTS
TWCK
TWD
TWO-WIRE
INTERFACE 0/1
DMA
PULSE WIDTH
MODULATION
CONTROLLER
DMA
DIGITAL TO
ANALOG
CONVERTER 0/1
DMA
DAC0A/B
ANALOG
COMPARATOR
0A/0B/1A/1B
AC0AP/N AC0BP/N
AC1AP/N AC1BP/N
DAC1A/B
I2S INTERFACE
DMA
TIMER/COUNTER 1
A[2..0]
B[2..0]
CLK[2..0]
QUADRATURE
DECODER
0/1
QEPA
QEPB
QEPI
XIN32
XOUT32
XIN[1:0]
XOUT[1:0]
TIMER/COUNTER 0
CLK[2..0]
A[2..0]
B[2..0]
ANALOG TO
DIGITAL
CONVERTER 0/1
DMA
ADCIN[15..0]
ADCVREFP/N
USART1
DMA
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
PBC
PBA
SERIAL
PERIPHERAL
INTERFACE 0
DMA
SCK
MISO, MOSI
NPCS[3..0]
M
R
W
PWML[3..0]
PWMH[3..0]
ADCREF0/1
aWire
RESET_N
ASYNCHRONOUS
TIMER
WATCHDOG
TIMER
FREQUENCY METER
POWER MANAGER
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
SYSTEM CONTROL
INTERFACE
GCLK[1..0]
BODs (1.8V,
3.3V, 5V)
RC8M
AC0AOUT/AC0BOUT
AC1AOUT/AC1BOUT
External Interrupt
Controller
EXTINT[8:1]
NMI
TWO-WIRE
INTERFACE 2
DMA
TWD
TWCK
ETHERNET
MAC
DMA
S
COL,
CRS,
RXD[3..0],
RX_CLK,
RX_DV,
RX_ER,
TX_CLK
MDC,
TXD[3..0],
TX_EN,
TX_ER,
SPEED
MDIO
M
512/
256/
128/64
KB
Flash
Flash
Controller
BCLK
IWS
ISDO
MCLK
LOCAL BUS
DACREF
ISDI
TMS
TCK
TDO
RC120M
EXT_FAULTS[1:0]
TWALM
USART4
DMA
RXD
TXD
CLK
RTS, CTS
6
32117A–10/2010
AT32UC3C
2.2 Configuration Summary
Table 2-1. Configuration Summary
Feature
AT32UC3C0512C/
AT32UC3C0256C/
AT32UC3C0128C/
AT32UC3C064C
AT32UC3C1512C/
AT32UC3C1256C/
AT32UC3C1128C/
AT32UC3C164C
AT32UC3C2512C/
AT32UC3C2256C/
AT32UC3C2128C/
AT32UC3C264C
Flash 512/256/128/64 KB 512/256/128/64 KB 512/256/128/64 KB
SRAM 64/64/32/16KB 64/64/32/16KB 64/64/32/16KB
HSB RAM 4 KB
EBI 1 0 0
GPIO 123 81 45
Exter nal Interrupts 8 8 8
TWI 3 3 2
USART 5 5 4
Peripheral DMA Channels 16 16 16
Peripheral Event System 1 1 1
SPI 2 2 1
CAN channels 2 2 2
USB 1 1 1
Ether net MAC 10/100 1 1 1
I2S 1 1 1
Asynchronous Timers 1 1 1
Timer/Counter Channels 6 6 3
PWM channels 4x2
QDEC 2 2 1
Frequency Meter 1
Watchdog Timer 1
Power Manager 1
Oscillators
PLL 80-240 MHz (PLL0/PLL1)
Crystal Oscillator 0.4-20 MHz (OSC0 )
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 115 kHz (RCSYS)
RC Oscillator 8 MHz (RC8M)
RC Oscillator 120 MHz (RC120M)
0.4-20 MHz (OSC1) -
12-bit ADC
number of channels 1
16 1
16 1
11
12-bit DAC
number of channels 1
41
41
2
7
32117A–10/2010
AT32UC3C
Analog Comparators 4 4 2
JTAG 1
aWire 1
Max Frequency 66 MHz
Package LQFP144 TQFP100 TQFP64/QFN64
Table 2-1. Configuration Summary
Feature
AT32UC3C0512C/
AT32UC3C0256C/
AT32UC3C0128C/
AT32UC3C064C
AT32UC3C1512C/
AT32UC3C1256C/
AT32UC3C1128C/
AT32UC3C164C
AT32UC3C2512C/
AT32UC3C2256C/
AT32UC3C2128C/
AT32UC3C264C
8
32117A–10/2010
AT32UC3C
3. Package and Pinout
3.1 Package
The device pins are mult iplexed with peripheral functions as described in Table 3-1 on page 10.
Figure 3-1. QFN64/TQFP64 Pinout
Note: on QFN packages, the exposed pad is unconnected.
PA001
PA012
PA023
PA034
VDDIO5
GNDIO6
PA047
PA058
PA069
PA0710
PA0811
PA0912
PA1613
ADCVREFP14
ADCVREFN15
PA1916
GNDANA17
VDDANA18
PA2019
PA2120
PA2221
PA2322
VBUS23
DM24
DP25
GNDPLL26
VDDIN_527
VDDIN_3328
VDDCORE29
GNDCORE30
PB3031
PB3132
PD0148
PD0047
PC2246
PC2145
PC2044
PC1943
PC1842
PC1741
PC1640
PC1539
PC0538
PC0437
GNDIO36
VDDIO35
PC0334
PC0233
PD02 49
PD03 50
VDDIO 51
GNDIO 52
PD11 53
PD12 54
PD13 55
PD14 56
PD21 57
PD27 58
PD28 59
PD29 60
PD30 61
PB00 62
PB01 63
RESET_N 64
9
32117A–10/2010
AT32UC3C
Figure 3-2. TQFP100 Pinout
PA001
PA012
PA023
PA034
VDDIO5
GNDIO6
PB047
PB058
PB069
PA0410
PA0511
PA0612
PA0713
PA0814
PA0915
PA1016
PA1117
PA1218
PA1319
PA1420
PA1521
PA1622
ADCVREFP23
ADCVREFN24
PA1925
GNDANA26
VDDANA27
PA2028
PA2129
PA2230
PA2331
PA2432
PA2533
VBUS34
DM35
DP36
GNDPLL37
VDDIN_538
VDDIN_3339
VDDCORE40
GNDCORE41
PB1942
PB2043
PB2144
PB2245
PB2346
PB3047
PB3148
PC0049
PC0150
PD0175
PD0074
PC3173
PC2472
PC2371
PC2270
PC2169
PC2068
PC1967
PC1866
PC1765
PC1664
PC1563
PC1462
PC1361
PC1260
PC1159
PC0758
PC0657
PC0556
PC0455
GNDIO54
VDDIO53
PC0352
PC0251
PD02 76
PD03 77
PD07 78
PD08 79
PD09 80
PD10 81
VDDIO 82
GNDIO 83
PD11 84
PD12 85
PD13 86
PD14 87
PD21 88
PD22 89
PD23 90
PD24 91
PD27 92
PD28 93
PD29 94
PD30 95
PB00 96
PB01 97
RESET_N 98
PB02 99
PB03 100
10
32117A–10/2010
AT32UC3C
Figure 3-3. LQFP144 Pinout
3.2 Peripheral Multiplexing on I/O lines
3.2.1 Multiplexed signals
Each GPIO line can be assigned to one of the periph eral functio ns.The following tab le describes
the peripheral signals multiplexed to the GPIO lines.
PA001
PA012
PA023
PA034
VDDIO5
GNDIO6
PB047
PB058
PB069
PB0710
PB0811
PB0912
PB1013
PB1114
PB1215
PB1316
PB1417
PB1518
PB1619
PB1720
PA0421
PA0522
PA0623
PA0724
PA0825
PA0926
PA1027
PA1128
PA1229
PA1330
PA1431
PA1532
PA1633
ADCVREFP34
ADCVREFN35
PA1936
GNDANA37
VDDANA38
PA2039
PA2140
PA2241
PA2342
PA2443
PA2544
PA2645
PA2746
PA2847
PA2948
VBUS49
DM50
DP51
GNDPLL52
VDDIN_553
VDDIN_3354
VDDCORE55
GNDCORE56
PB1857
PB1958
PB2059
PB2160
PB2261
PB2362
PB2463
PB2564
PB2665
PB2766
PB2867
PB2968
PB3069
PB3170
PC0071
PC0172
PD01108
PD00107
PC31106
PC30105
GNDIO104
VDDIO103
PC29102
PC28101
PC27100
PC2699
PC2598
PC2497
PC2396
PC2295
PC2194
PC2093
PC1992
PC1891
PC1790
PC1689
PC1588
PC1487
PC1386
PC1285
PC1184
PC1083
PC0982
PC0881
PC0780
PC0679
PC0578
PC0477
GNDIO76
VDDIO75
PC0374
PC0273
PD02 109
PD03 110
PD04 111
PD05 112
PD06 113
PD07 114
PD08 115
PD09 116
PD10 117
VDDIO 118
GNDIO 119
PD11 120
PD12 121
PD13 122
PD14 123
PD15 124
PD16 125
PD17 126
PD18 127
PD19 128
PD20 129
PD21 130
PD22 131
PD23 132
PD24 133
PD25 134
PD26 135
PD27 136
PD28 137
PD29 138
PD30 139
PB00 140
PB01 141
RESET_N 142
PB02 143
PB03 144
Table 3-1. GPIO Controller Function Multiplexing
TQFP/
QFN64 TQFP
100 LQFP
144 Pad
Type(1) PIN GPIO
GPIO function
ABCDEF
1 1 1 x1/x2 PA00 0 CANIF -
TXLINE[1]
11
32117A–10/2010
AT32UC3C
2 2 2 x1/x2 PA01 1 CANIF -
RXLINE[1]
PEVC -
PAD_EVT[
0]
3 3 3 x1/x2 PA02 2 SCIF -
GCLK[0]
PEVC -
PAD_EVT[
1]
4 4 4 x1/x2 PA03 3 SCIF -
GCLK[1] EIC -
EXTINT[1]
7 10 21 x1/x2 PA04 4 ADCIN0 USBC - ID AC IFA0 -
ACAOUT
8 11 22 x1/x2 PA05 5 ADCIN1 USBC -
VBOF AC IFA0 -
ACBOUT
9 12 23 x1/x2 PA06 6 ADCIN2 AC1AP1
PEVC -
PAD_EVT[
2]
10 13 24 x1/x2 PA07 7 ADCIN3 AC1AN1
PEVC -
PAD_EVT[
3]
11 14 25 x1/x2 PA08 8 ADCIN4 AC1BP1 EIC -
EXTINT[2]
12 15 26 x1/x2 PA09 9 ADCIN5 AC1BN1
16 27 x1/x2 PA10 10 ADCIN6 EIC -
EXTINT[4]
PEVC -
PAD_EVT[
13]
17 28 x1/x2 PA11 11 ADCIN7 ADCREF1
PEVC -
PAD_EVT[
14]
18 29 x1/x2 PA12 12 AC1AP0 SPI0 -
NPCS[0] DAC1A
19 30 x1/x2 PA13 13 AC1AN0 SPI0 -
NPCS[1] ADCIN15
20 31 x1/x2 PA14 14 AC1BP0 SPI1 -
NPCS[0]
21 32 x1/x2 PA15 15 AC1BN0 SPI1 -
NPCS[1] DAC1B
13 22 33 x1/x2 PA16 16 ADCREF0 DACREF
14 23 34 ADC
REFP
15 24 35 ADC
REFN
16 25 36 x1/x2 PA19 19 ADCIN8 EIC -
EXTINT[1]
19 28 39 x1/x2 PA20 20 ADCIN9 AC0AP0 DAC0A
20 29 40 x1/x2 PA21 21 ADCIN10 AC0BN0 DAC0B
21 30 41 x1/x2 PA22 22 ADCIN11 AC0AN0
PEVC -
PAD_EVT[
4] MACB -
SPEED
Table 3-1. GPIO Controller Function Multiplexing
12
32117A–10/2010
AT32UC3C
22 31 42 x1/x2 PA23 23 ADCIN12 AC0BP0
PEVC -
PAD_EVT[
5] MACB -
WOL
32 43 x1/x2 PA24 24 ADCIN13 SPI1 -
NPCS[2]
33 44 x1/x2 PA25 25 ADCIN14 SPI1 -
NPCS[3] EIC -
EXTINT[0]
45 x1/x2 PA26 26 AC0AP1 EIC -
EXTINT[1]
46 x1/x2 PA27 27 AC0AN1 EIC -
EXTINT[2]
47 x1/x2 PA28 28 AC0BP1 EIC -
EXTINT[3]
48 x1/x2 PA29 29 AC0BN1 EIC -
EXTINT[0]
62 96 140 x1 PB00 32 USART0 -
CLK CANIF -
RXLINE[1] EIC -
EXTINT[8]
PEVC -
PAD_EVT[
10]
63 97 141 x1 PB01 33 CANIF -
TXLINE[1]
PEVC -
PAD_EVT[
11]
99 143 x1 PB02 34 USBC - ID
PEVC -
PAD_EVT[
6] TC1 - A1
100 144 x1 PB03 35 USBC -
VBOF
PEVC -
PAD_EVT[
7]
7 7 x1/x2 PB04 36 SPI1 -
MOSI CANIF -
RXLINE[0] QDEC1 -
QEPI MACB -
TXD[2]
8 8 x1/x2 PB05 37 SPI1 -
MISO CANIF -
TXLINE[0]
PEVC -
PAD_EVT[
12] USART3 -
CLK MACB -
TXD[3]
9 9 x2/x4 PB06 38 SPI1 - SCK QDEC1 -
QEPA USART1 -
CLK MACB -
TX_ER
10 x1/x2 PB07 39 SPI1 -
NPCS[0] EIC -
EXTINT[2] QDEC1 -
QEPB MACB -
RX_DV
11 x1/x2 PB08 40 SPI1 -
NPCS[1]
PEVC -
PAD_EVT[1
]PWM -
PWML[0] EIC -
SCAN[0] MACB -
RXD[0]
12 x1/x2 PB09 41 SPI1 -
NPCS[2] PWM -
PWMH[0] EIC -
SCAN[1] MACB -
RXD[1]
13 x1/x2 PB10 42 USART1 -
DTR SPI0 - MOSI PWM -
PWML[1] EIC -
SCAN[2]
14 x1/x2 PB11 43 USART1 -
DSR SPI0 - MISO PWM -
PWMH[1] EIC -
SCAN[3]
15 x1/x2 PB12 44 USART1 -
DCD SPI0 - SCK PWM -
PWML[2] EIC -
SCAN[4]
16 x1/x2 PB13 45 USART1 -
RI SPI0 -
NPCS[0] PWM -
PWMH[2] EIC -
SCAN[5] MACB -
RX_ER
Table 3-1. GPIO Controller Function Multiplexing
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17 x1/x2 PB14 46 USART1 -
RTS SPI0 -
NPCS[1] PWM -
PWML[3] EIC -
SCAN[6] MACB -
MDC
18 x1/x2 PB15 47 USART1 -
CTS USART1 -
CLK PWM -
PWMH[3] EIC -
SCAN[7] MACB -
MDIO
19 x1/x2 PB16 48 USART1 -
RXD SPI0 -
NPCS[2]
PWM -
EXT_FAUL
TS[0] CANIF -
RXLINE[0]
20 x1/x2 PB17 49 USART1 -
TXD SPI0 -
NPCS[3]
PWM -
EXT_FAUL
TS[1] CANIF -
TXLINE[0]
57 x1/x2 PB18 50 TC0 -
CLK2 EIC -
EXTINT[4]
42 58 x1/x2 PB19 51 TC0 - A0 SPI1 - MOSI IISC - ISDO MACB -
CRS
43 59 x1/x2 PB20 52 TC0 - B0 SPI1 - MISO IISC - ISDI ACIFA1 -
ACAOUT MACB -
COL
44 60 x2/x4 PB21 53 TC0 -
CLK1 SPI1 - SCK IISC -
IMCK ACIFA1 -
ACBOUT MACB -
RXD[2]
45 61 x1/x2 PB22 54 TC0 - A1 SPI1 -
NPCS[3] IISC - ISCK SCIF -
GCLK[0] MACB -
RXD[3]
46 62 x1/x2 PB23 55 TC0 - B1 SPI1 -
NPCS[2] IISC - IWS SCIF -
GCLK[1] MACB -
RX_CLK
63 x1/x2 PB24 56 TC0 -
CLK0 SPI1 -
NPCS[1]
64 x1/x2 PB25 57 TC0 - A2 SPI1 -
NPCS[0]
PEVC -
PAD_EVT[
8]
65 x2/x4 PB26 58 TC0 - B2 SPI1 - SCK
PEVC -
PAD_EVT[
9] MACB -
TX_EN
66 x1/x2 PB27 59 QDEC0 -
QEPA SPI1 - MISO
PEVC -
PAD_EVT[
10] TC1 -
CLK0 MACB -
TXD[0]
67 x1/x2 PB28 60 QDEC0 -
QEPB SPI1 - MOSI
PEVC -
PAD_EVT[
11] TC1 - B0 MACB -
TXD[1]
68 x1/x2 PB29 61 QDEC0 -
QEPI SPI0 -
NPCS[0]
PEVC -
PAD_EVT[
12] TC1 - A0
31 47 69 x1 PB30 62
32 48 70 x1 PB31 63
49 71 x1/x2 PC00 64 USBC - ID SPI0 -
NPCS[1] USART2 -
CTS TC1 - B2 CANIF -
TXLINE[1]
50 72 x1/x2 PC01 65 USBC -
VBOF SPI0 -
NPCS[2] USART2 -
RTS TC1 - A2 CANIF -
RXLINE[1]
33 51 73 x1 PC02 66 TWIMS0 -
TWD SPI0 -
NPCS[3] USART2 -
RXD TC1 -
CLK1 MACB -
MDC
34 52 74 x1 PC03 67 TWIMS0 -
TWCK EIC -
EXTINT[1] USART2 -
TXD TC1 - B1 MACB -
MDIO
Table 3-1. GPIO Controller Function Multiplexing
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37 55 77 x1 PC04 68 TWIMS1 -
TWD EIC -
EXTINT[3] USART2 -
TXD TC0 - B1
38 56 78 x1 PC05 69 TWIMS1 -
TWCK EIC -
EXTINT[4] USART2 -
RXD TC0 - A2
57 79 x1 PC06 70
PEVC -
PAD_EVT[
15] USART2 -
CLK USART2 -
CTS TC0 -
CLK2 TWIMS2 -
TWD TWIMS0 -
TWALM
58 80 x1 PC07 71
PEVC -
PAD_EVT[
2] EBI -
NCS[3] USART2 -
RTS TC0 - B2 TWIMS2 -
TWCK TWIMS1 -
TWALM
81 x1/x2 PC08 72
PEVC -
PAD_EVT[
13] SPI1 -
NPCS[1] EBI -
NCS[0] USART4 -
TXD
82 x1/x2 PC09 73
PEVC -
PAD_EVT[
14] SPI1 -
NPCS[2] EBI -
ADDR[23] USART4 -
RXD
83 x1/x2 PC10 74
PEVC -
PAD_EVT[
15] SPI1 -
NPCS[3] EBI -
ADDR[22]
59 84 x1/x2 PC11 75 PWM -
PWMH[3] CANIF -
RXLINE[1] EBI -
ADDR[21] TC0 -
CLK0
60 85 x1/x2 PC12 76 PWM -
PWML[3] CANIF -
TXLINE[1] EBI -
ADDR[20] USART2 -
CLK
61 86 x1/x2 PC13 77 PWM -
PWMH[2] EIC -
EXTINT[7] EBI - SDCS USART0 -
RTS
62 87 x1/x2 PC14 78 PWM -
PWML[2] USART0 -
CLK EBI -
SDCKE USART0 -
CTS
39 63 88 x1/x2 PC15 79 PWM -
PWMH[1] SPI0 -
NPCS[0] EBI -
SDWE USART0 -
RXD CANIF -
RXLINE[1]
40 64 89 x1/x2 PC16 80 PWM -
PWML[1] SPI0 -
NPCS[1] EBI - CAS USART0 -
TXD CANIF -
TXLINE[1]
41 65 90 x1/x2 PC17 81 PWM -
PWMH[0] SPI0 -
NPCS[2] EBI - RAS IISC - ISDO USART3 -
TXD
42 66 91 x1/x2 PC18 82 PWM -
PWML[0] EIC -
EXTINT[5] EBI -
SDA10 IISC - ISDI USART3 -
RXD
43 67 92 x1/x2 PC19 83 PWM -
PWML[2] SCIF -
GCLK[0] EBI -
DATA[0] IISC -
IMCK USART3 -
CTS
44 68 93 x1/x2 PC20 84 PWM -
PWMH[2] SCIF -
GCLK[1] EBI -
DATA[1] IISC - ISCK USART3 -
RTS
45 69 94 x1/x2 PC21 85
PWM -
EXT_FAUL
TS[0] CANIF -
RXLINE[0] EBI -
DATA[2] IISC - IWS
46 70 95 x1/x2 PC22 86
PWM -
EXT_FAUL
TS[1] CANIF -
TXLINE[0] EBI -
DATA[3] USART3 -
CLK
71 96 x1/x2 PC23 87 QDEC1 -
QEPB CANIF -
RXLINE[1] EBI -
DATA[4]
PEVC -
PAD_EVT[
3]
72 97 x1/x2 PC24 88 QDEC1 -
QEPA CANIF -
TXLINE[1] EBI -
DATA[5]
PEVC -
PAD_EVT[
4]
Table 3-1. GPIO Controller Function Multiplexing
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98 x1/x2 PC25 89 TC1 - CLK2 EBI -
DATA[6] SCIF -
GCLK[0] USART4 -
TXD
99 x1/x2 PC26 90 QDEC1 -
QEPI TC1 - B2 EBI -
DATA[7] SCIF -
GCLK[1] USART4 -
RXD
100 x1/x2 PC27 91 TC1 - A2 EBI -
DATA[8] EIC -
EXTINT[0] USART4 -
CTS
101 x1/x2 PC28 92 SPI1 -
NPCS[3] TC1 - CLK1 EBI -
DATA[9] USART4 -
RTS
102 x1/x2 PC29 93 SPI0 -
NPCS[1] TC1 - B1 EBI -
DATA[10]
105 x1/x2 PC30 94 SPI0 -
NPCS[2] TC1 - A1 EBI -
DATA[11]
73 106 x1/x2 PC31 95 SPI0 -
NPCS[3] TC1 - B0 EBI -
DATA[12]
PEVC -
PAD_EVT[
5] USART4 -
CLK
47 74 107 x1/x2 PD00 96 SPI0 -
MOSI TC1 - CLK0 EBI -
DATA[13] QDEC0 -
QEPI USART0 -
TXD
48 75 108 x1/x2 PD01 97 SPI0 -
MISO TC1 - A0 EBI -
DATA[14] TC0 -
CLK1 USART0 -
RXD
49 76 109 x2/x4 PD02 98 SPI0 - SCK TC0 - CLK2 EBI -
DATA[15] QDEC0 -
QEPA
50 77 110 x1/x2 PD03 99 SPI0 -
NPCS[0] TC0 - B2 EBI -
ADDR[0] QDEC0 -
QEPB
111 x1/x2 PD04 100 SPI0 -
MOSI EBI -
ADDR[1]
112 x1/x2 PD05 101 SPI0 -
MISO EBI -
ADDR[2]
113 x2/x4 PD06 102 SPI0 - SCK EBI -
ADDR[3]
78 114 x1/x2 PD07 103 USART1 -
DTR EIC -
EXTINT[5] EBI -
ADDR[4] QDEC0 -
QEPI USART4 -
TXD
79 115 x1/x2 PD08 104 USART1 -
DSR EIC -
EXTINT[6] EBI -
ADDR[5] TC1 -
CLK2 USART4 -
RXD
80 116 x1/x2 PD09 105 USART1 -
DCD CANIF -
RXLINE[0] EBI -
ADDR[6] QDEC0 -
QEPA USART4 -
CTS
81 117 x1/x2 PD10 106 USART1 -
RI CANIF -
TXLINE[0] EBI -
ADDR[7] QDEC0 -
QEPB USART4 -
RTS
53 84 120 x1/x2 PD11 107 USART1 -
TXD USBC - ID EBI -
ADDR[8]
PEVC -
PAD_EVT[
6] MACB -
TXD[0]
54 85 121 x1/x2 PD12 108 USART1 -
RXD USBC -
VBOF EBI -
ADDR[9]
PEVC -
PAD_EVT[
7] MACB -
TXD[1]
55 86 122 x2/x4 PD13 109 USART1 -
CTS USART1 -
CLK EBI -
SDCK
PEVC -
PAD_EVT[
8] MACB -
RXD[0]
56 87 123 x1/x2 PD14 110 USART1 -
RTS EIC -
EXTINT[7] EBI -
ADDR[10]
PEVC -
PAD_EVT[
9] MACB -
RXD[1]
Table 3-1. GPIO Controller Function Multiplexing
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Note: 1. Ref er to ”Electrical Characteristics” on page 50 for a description of the electrical propertie s of
the pad types used.
See Section 3.3 for a description of the various pe ripheral signals.
Signals are prioritized according to the function priority listed in Table 3-2 on page 17 if multiple
functions are enabled simultaneously.
3.2.2 Peripheral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions ar e enabled.
124 x1/x2 PD15 111 TC0 - A0 USART3 -
TXD EBI -
ADDR[11]
125 x1/x2 PD16 112 TC0 - B0 USART3 -
RXD EBI -
ADDR[12]
126 x1/x2 PD17 113 TC0 - A1 USART3 -
CTS EBI -
ADDR[13] USART3 -
CLK
127 x1/x2 PD18 114 TC0 - B1 USART3 -
RTS EBI -
ADDR[14]
128 x1/x2 PD19 115 TC0 - A2 EBI -
ADDR[15]
129 x1/x2 PD20 116 TC0 - B2 EBI -
ADDR[16]
57 88 130 x1/x2 PD21 117 USART3 -
TXD EIC -
EXTINT[0] EBI -
ADDR[17] QDEC1 -
QEPI
89 131 x1/x2 PD22 118 USART3 -
RXD TC0 - A2 EBI -
ADDR[18] SCIF -
GCLK[0]
90 132 x1/x2 PD23 119 USART3 -
CTS USART3 -
CLK EBI -
ADDR[19] QDEC1 -
QEPA
91 133 x1/x2 PD24 120 USART3 -
RTS EIC -
EXTINT[8] EBI -
NWE1 QDEC1 -
QEPB
134 x1/x2 PD25 121 TC0 -
CLK0 USBC - ID EBI -
NWE0 USART4 -
CLK
135 x1/x2 PD26 122 TC0 -
CLK1 USBC -
VBOF EBI - NRD
58 92 136 x1/x2 PD27 123 USART0 -
TXD CANIF -
RXLINE[0] EBI -
NCS[1] TC0 - A0 MACB -
RX_ER
59 93 137 x1/x2 PD28 124 USART0 -
RXD CANIF -
TXLINE[0] EBI -
NCS[2] TC0 - B0 MACB -
RX_DV
60 94 138 x1/x2 PD29 125 USART0 -
CTS EIC -
EXTINT[6] USART0 -
CLK TC0 -
CLK0 MACB -
TX_CLK
61 95 139 x1/x2 PD30 126 USART0 -
RTS EIC -
EXTINT[3] EBI -
NWAIT TC0 - A1 MACB -
TX_EN
Table 3-1. GPIO Controller Function Multiplexing
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Table 3-2. Peripheral Functions
3.2.3 Oscillato r Pino ut
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more
information about this.
3.2.4 JTAG port connections
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
3.2.5 Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the GPIO configuration. Two different OCD trace pin mappings are possible,
Function Description
A GPIO peripheral selecti on A
B GPIO peripheral selecti on B
C GPIO peripheral selecti on C
D GPIO peripheral selecti on D
E GPIO peripheral selecti on E
F GPIO peripheral selecti on F
Table 3-3. Oscillator pinout
QFN64/
TQFP64 pin T QFP100 pin LQFP144 pin Pad Oscillator pin
31 47 69 PB30 xin0
99 143 PB02 xin1
62 96 140 PB00 xin32
32 48 70 PB31 xout0
100 144 PB03 xout1
63 97 141 PB01 xout32
Table 3-4. JTAG pinout
QFN64/
TQFP64 pin TQFP100 pin LQFP144 pin Pin name JTAG pin
222PA01TDI
333PA02TDO
444PA03TMS
111PA00TCK
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depending on the con f igurat ion of th e O CD AXS reg iste r. Fo r de tails, see the AVR32UC Te chni-
cal Reference Manual.
3.2.6 Other Functions
The functions listed in Table 3-6 are n ot mapped to t he normal GPIO funct ions. The aWire DATA
pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active
after the aWire is enable d and the 2_PIN_MODE command has been sent.
3.3 Signals Description
The following table give details on the signal name classified by peripherals.
Table 3-5. Nexus OCD AUX port connections
Pin AXS=0 AXS=1 AXS=2
EVTI_N PA08 PB19 PA10
MDO[5] PC05 PC31 PB06
MDO[4] PC04 PC12 PB15
MDO[3] PA23 PC11 PB14
MDO[2] PA22 PB23 PA27
MDO[1] PA19 PB22 PA26
MDO[0] PA09 PB20 PA19
EVTO_N PD29 PD29 PD29
MCKO PD13 PB21 PB26
MSEO[1] PD30 PD08 PB25
MSEO[0] PD14 PD07 PB18
Table 3-6. Other Functions
QFN64/
TQFP64 pin T QFP100 pin LQFP144 pin Pad Oscillator pin
64 98 142 R ESET_N aWire DATA
333PA02aWire DATAOUT
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIO I/O Power Supply Power
Input
4.5V to 5.5V
or
3.0V to 3.6 V
VDDANA Analog Power Supply Power
Input
4.5V to 5.5V
or
3.0V to 3.6 V
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VDDIN_5 1.8V Voltag e Regulator Input Power
Input
Power Supply:
4.5V to 5.5V
or
3.0V to 3.6 V
VDDIN_33 USB I/O power supply Power
Output/
Input
Capacitor Connection for the 3.3V
voltage regulator
or power supply:
3.0V to 3.6 V
VDDCORE 1.8V Voltag e Regulator Output Power
output Capacitor Connection for the 1.8V
voltage regulator
GNDIO I/O Ground Ground
GNDANA Analog Ground Ground
GNDCORE Ground of the core Ground
GNDPLL Ground of the PLLs Ground
Analog Comparator Interface - A CIFA0/1
A C0AN1/AC0AN0 Negative inputs fo r comparator AC0A Analog
AC0AP1/AC0AP0 Positive inputs for comparator AC0A Analog
A C0BN1/AC0BN0 Negative inputs for comparator AC0B Analog
AC0BP1/AC0BP0 Positive inputs for comparator AC0B Analog
A C1AN1/AC1AN0 Negative inputs for comparator AC1A Analog
AC1AP1/AC1AP0 Positive inputs for comparator AC1A Analog
A C1BN1/AC1BN0 Negative inputs for comparator AC1B Analog
AC1BP1/AC1BP0 Positive inputs for comparator AC1B Analog
ACAOUT/ACBOUT analog comparator outputs output
ADC Interface - ADCIFA
ADCIN[15:0 ] ADC input pins Analog
ADCREF0 Analog positive reference 0 voltage input Analog
ADCREF1 Analog positive reference 1 voltage input Analog
ADCVREFP Analog positive reference connected to external
capacitor Analog
ADCVREFN Analog negative reference connected to
external capacitor Analog
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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Auxiliary Port - AUX
MCKO Tr ace Dat a Output Clock Output
MDO[5:0] Trace Data Output Output
MSEO[1:0] Trace Frame Control Output
EVTI_N Event In Output Low
EVTO_N Event Out Output Low
aWire - AW
DATA aWire data I/O
DATAOUT aWire data output for 2-pin mode I/O
Controller Area Network Interface - CANIF
RXLINE[1:0] CAN channel rxline I/O
TXLINE[1:0] CAN channel txline I/O
DAC Interface - DACIFB0/1
DAC0A, DAC0B DAC0 output pins of S/H A Analog
DAC1A, DAC1B DAC output pins of S/H B Analog
DACREF Analog reference voltage input Analog
External Bus Interface - EBI
ADDR[23:0] Address Bus Output
CAS Column Signal Output Low
DATA[15:0] Data Bus I/O
NCS[3:0] Chip Select Output Low
NRD Read Sign al Output Low
NWAIT External Wait Signal Input Low
NWE0 Write Enable 0 Output Low
NWE1 Write Enable 1 Output Low
RAS Row Signal Output Low
SDA10 SDRAM Address 10 Line Output
SDCK SDRAM Clock Output
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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SDCKE SDRAM Clock Enable Output
SDCS SDRAM Chip Select Output Low
SDWE SDRAM Write Enable Output Low
External Interrupt Controller - EIC
EXTINT[8:1] Exter nal Interrupt Pins Input
NMI_N = EXTINT[0 ] Non-Maskable In te rrupt Pin Input Low
General Purpose Input/Output - GPIOA, GPIOB, GPIOC, GPIOD
PA[29:19] - PA[16:0] Parallel I/O Controller GPIOA I/O
PB[31:0] Parallel I/O Controller GPIOB I/O
PC[31:0] Parallel I/O Controller GPIOC I/O
PD[30:0] Parallel I/O Controller GPIOD I/O
Inter-IC Sound (I2S) Controller - IISC
IMCK I2S Master Clock Output
ISCK I2S Serial Clock I/O
ISDI I2S Serial Data In Input
ISDO I2S Serial Data Out Output
IWS I2S Word Select I/O
JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
Ethernet MAC - MACB
COL Collision Detect Input
CRS Carrier Sense and Data Vali d Input
MDC Management Data Clock Output
MDIO Managemen t Data Input/Output I/O
RXD[3:0] Receive Data Input
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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RX_CLK Receive Clock Input
RX_DV Receive Data Valid Input
RX_ER Receive Coding Error Input
SPEED Speed Output
TXD[3:0] Transmit Data Output
TX_CLK Transmit Clock or Reference Clock Input
TX_EN Transmit Enable Output
TX_ER Transmit Coding Error Output
WOL Wake-On-LAN Output
P e ripheral Event Controller - PEVC
PAD_EVT[15:0] Event Input Pins In put
Power Manager - PM
RESET_N Reset Pin Input Low
Pulse Width Modulator - PWM
PWMH[3:0]
PWML[3:0] PWM Output Pins Output
EXT_FAULT[1:0] PWM Fault Inpu t Pins Input
Quadrature Decoder- QDEC0/QDEC1
QEPA QEPA quadrature input Input
QEPB QEPB quadrature input Input
QEPI Index input Input
System Controller Interface- SCIF
XIN0, XIN1, XIN32 Crystal 0, 1, 32K Inputs Analog
XOUT0, XOUT1,
XOUT32 Crystal 0, 1, 32K Outp ut Analog
GCLK0 - GCLK1 Generic Clock Pins Output
Serial Peripheral Interface - SPI0, SPI1
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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NPCS[3:0] SPI Peripheral Chip Select I/O Low
SCK Clock Output
Timer/Counter - TC0, TC1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWIMS0 , TWIMS1, TWIMS2
TWALM SMBus SMBALERT I/O Low Only on TWIMS0, TWIMS1
TWCK Serial Clock I/O
TWD Serial Data I/O
Universal Synchr onous Asynch ronous Receiver Transmitter - USART0, USART1, USART2, USART3, USART4
CLK Clock I/O
CTS Clear To Send Input Low
DCD Data Carrier Detect Input Low Only USART1
DSR Data Set Ready Input Low Only USART1
DTR Data Terminal Ready Output Low Only USART1
RI Ring Indicator Input Low Only USART1
RTS Request To Send Output Low
RXD Receive Data Input
TXD Transmit Data Output
Universal Serial Bus Device - USB
DM USB Device Port Data - Analog
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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3.4 I/O Line Considerations
3.4.1 JTAG pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-u p resistors when JTAG is enabled. The TCK p in always have pull-up e nabled
during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG
pins can be used as GPIO pins and muxed with peripherals when the JTAG is disabled. Please
refer to Section 3.2.4 for the JTAG port connections.
3.4.2 RESET_N pin The RESET_N pin integrates a pull-up resistor to VDDIO. As the product integrates a power-on
reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to
be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
3.4.3 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike-f iltering. When u sed as GPIO-pins or used fo r other perip herals, the
pins have the same characteristics as GPIO pins.
3.4.4 GPIO pins All I/O lines integrate programmable pull-up and pull-down resistors. Most I/O lines integrate
drive strength control, see Table 3-1. Programming of this pull-up and pull-down resistor or this
drive strength is performed independently for each I/O line through th e GPIO Controllers.
After reset, I/O lines default as inputs with pull-up/pull-down resistors disabled. After reset, out-
put drive strength is configured to the lowest value to reduce global EMI of the device.
When the I/O line is configured as analog function (ADC I/O, AC inputs, DAC I/O), the pull-up
and pull-down resistors are automatically disabled.
DP USB Device Port Data + Analog
VBUS USB VBUS Monitor and OTG Negociation Analog
Input
ID ID Pin of the USB Bus Input
VBOF USB VBUS On/off: bus power control port output
Table 3-7. Signal Description List
Signal Name Function Type Active
Level Comments
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4. Processor and Architecture
Rev: 2.1.2.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
4.1 Features •32-bit load/store AVR32A RISC architecture
– 15 general-purpose 32-bit registers
– 32-bit Stac k Pointer, Program Counter and Link Register reside in register file
– Fully or thogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure operating systems
– Innov ative instruction set together with v ariab le instruction length ensuring industry leading
code density
– DSP extension wi th saturating ari thmetic, an d a wid e variety of multiply instructions
•3-stage pipeline allowing one instruction per clock cycle for most instructions
– Byte, halfword, word, and double word memory access
– Multiple interrupt priority levels
•MPU allows for operating systems with memory protection
•FPU enables hardware accelerated floating point calculations
•Secure State for supporting FlashVaultTM technology
4.2 AVR32 Architecture
AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-
sensitive embedded applications, with particular emphasis on low power consumption and high
code density. In addition, the instruction set architecture has been tuned to allow a variety of
microarchitectures, enablin g the AVR32 to be implemented as low-, mid-, or high-performan ce
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirem ents, a compact cod e size also contr ibutes to the core’s low power charact eris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an ext ended format with a larger imm ediate. In this way, the comp iler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases perfor mance, allowing an a ddition and a data move in the sa me instr uction in a
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single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
The register file is organized as sixteen 32-bit registers and inclu des the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
4.3 The AVR32UC CPU
The AVR32UC CPU targets low- and medium-performance applications, and provides an
advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Un it (MPU). A
hardware Floating Point Unit (FPU) is also provided through the coprocessor instruction space.
Java acceleration hardware is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.
Also, power consumption is re duced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and I /O control ler ports. This local bus has to be enabled by writing a
one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data
between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated
memory range allocate d to it, and data transfers are performed using regular load and store
instructions. Details on which devices that are mapped into the local bus space is given in the
CPU Local Bus section in the Memor ies chap te r .
Figure 4-1 on page 27 displays the contents of AVR32UC.
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Figure 4-1. Overview of the AVR32UC CPU
4.3.1 Pipeline Overview
AVR32UC has three pipeline stages, Instru ction Fetch (I F), Instr uction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) sect ion.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no dat a dependencies can arise in the pipeline .
Figure 4-2 on page 28 shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
MPU
High Speed Bus
High Speed Bus
OCD
system
OCD interface
Interrupt controller interface
High
Speed
Bus slave
High Speed Bus
High Speed Bus master
Power/
Reset
control
Reset interface
CPU Local
Bus
master
CPU Local Bus
Data memory controller
CPU RAM
High Speed
Bus master
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Figure 4-2. The AVR32UC Pipeline
4.3.2 AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers a nd return status re gisters. Instead, all th is information is sto red on the system
stack. This saves chip area at the expense of slower interrupt handling.
4.3.2.1 Interrupt Handling
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 re gisters and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to stor e the status register and ret urn address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register an d continue execution at the popped return address.
4.3.2.2 Java SupportAVR32UC does not provide Java hardware acceleration.
4.3.2.3 Floating Point Support
A fused multiply-accumulate Floating Point Unit (FPU), performaing a multiply and accumulate
as a single operation with no intermediate rounding, therby increasing precision is provided. The
floating point hardware conforms to the requirements of the C standard, which is based on the
IEEE 754 floating point standard.
4.3.2.4 Memor y Protection
The MPU allows the user to check all memory a ccesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
IF ID ALU
MUL
Regfile
write
Prefetch unit Decode unit
ALU unit
Multiply unit
Load-store
unit
LS
Regfile
Read
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4.3.2.5 Unaligned Reference Handling
AVR32UC does not support unali gne d accesses, e xcept fo r do ublewor d accesses. AVR32 UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
4.3.2.6 Unimplemented Instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
• All SIMD instructions
• All coprocessor instructions if no coprocessor s are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
4.3.2.7 CPU and Architecture Revision
Three major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 3.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. co de compiled
for revision 1 or 2 is binary-compatible with r evision 3 CPUs.
Table 4-1. Instructions with Unaligned Reference Support
Instruction Supported Alignment
ld.d Word
st.d Word
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4.4 Programming Model
4.4.1 Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3. The AVR32UC Register File
4.4.2 Status Register Configur ation
The Status Register (SR) is split into two halfwords, one upper and one lower, see Fi gure 4-4
and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition cod e flags and th e R, T,
and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4. The Status Register High Halfword
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
SP_APP SP_SYS
R12
R11
R9
R10
R8
Exception NMIINT1 INT2 INT3
LRLR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Secure
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SEC
LR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
Bit 31
000
Bit 16
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 3 Mask
Interrupt Level 2 Mask
10 0 0 0 1 1 0 0 0 00 0
FE I0M GMM1- D M0 EM I2MDM -M2
LC
1
SS
Initial value
Bit name
I1M
Mode Bit 0
Mode Bit 1
-
Mode Bit 2
Reserved
Debug State
-I3M
Reserved
Exception Mask
Global Interrupt Mask
Debug State Mask
Secure State
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Figure 4-5. The Status Register Low Halfword
4.4.3 Processor States
4.4.3.1 Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a hig her priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs execute d in this mode are restricted from executin g certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accesse d. Protect ed memo ry are as are also no t a vailab le. All other o perat ing
modes are privileged and ar e collectively called System Mod es. They have full acce ss to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read ou t and al ter system in formation for use during ap plication develop ment. This
implies that all system and application regist ers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Bit 15 Bit 0
Reserved
Carry
Zero
Sign
0 0 0 00000000000
- - --T- Bit name
Initial value
0 0
L Q V N Z C-
Overflow
Saturation
- - -
Lock
Reserved
Scratch
Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
Priority Mode Security Description
1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode
2 Exception Privileged Execute exceptions
3 Interrupt 3 Privileged General purpose interrupt mode
4 Interrupt 2 Privileged General purpose interrupt mode
5 Interrupt 1 Privileged General purpose interrupt mode
6 Interrupt 0 Privileged General purpose interrupt mode
N/A Supervisor Privileged Runs supervisor calls
N/A Application Unprivileged Normal program execution mode
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Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
4.4.3.3 Secure StateThe AVR32 can be set in a secure stat e, that allows a part of the code to execute in a state with
higher security levels. The rest of the code can not access resources reserved for this secure
code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Techni-
cal Reference Manual for details.
4.4.4 System Registers
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 4-3. System Registers
Reg # Address Name Function
0 0 SR Status Register
1 4 EVBA Exception Vector Base Address
2 8 ACBA Application Call Base Address
3 12 CPUCR CPU Control Register
4 16 ECR Exception Cause Register
5 20 RSR_SUP Unused in AVR32UC
6 24 RSR_INT0 Unused in AVR32UC
7 28 RSR_INT1 Unused in AVR32UC
8 32 RSR_INT2 Unused in AVR32UC
9 36 RSR_INT3 Unused in AVR32UC
10 40 RSR_EX Unused in AVR32UC
11 44 RSR_NMI Unused in AVR32UC
12 48 RSR_DBG Return Status Register for Debug mode
13 52 RAR_SUP Unused in AVR32UC
14 56 RAR_INT0 Unused in AVR32UC
15 60 RAR_INT1 Unused in AVR32UC
16 64 RAR_INT2 Unused in AVR32UC
17 68 RAR_INT3 Unused in AVR32UC
18 72 RAR_EX Unused in AVR32UC
19 76 RAR_NMI Unused in AVR32UC
20 80 RAR_DBG Return Address Register for Debug mode
21 84 JECR Unused in AVR32UC
22 88 JOSP Unused in AVR32UC
23 92 JAVA_LV0 Unused in AVR32UC
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24 96 JAVA_LV1 Unused in AVR32UC
25 100 JAVA_LV2 Unused in AVR32UC
26 104 JAVA_LV3 Unused in AVR32UC
27 108 JAVA_LV4 Unused in AVR32UC
28 112 JAVA_LV5 Unused in AVR32UC
29 116 JAVA_LV6 Unused in AVR32UC
30 120 JAVA_LV7 Unused in AVR32UC
31 124 JTBA Unused in AVR32UC
32 128 JBCR Unused in AVR32UC
33-63 132-252 Reserved Reserved for future use
64 256 CONFIG0 Configuration register 0
65 260 CONFIG1 Configuration register 1
66 264 COUNT Cycle Counter register
67 268 COMPARE Compare register
68 272 T LBEH I Unused in AVR32UC
69 276 T LBEL O Unused i n AVR32UC
70 280 PTBR Unused in AVR32UC
71 284 T LBEAR Un u se d i n AVR32UC
72 288 MMUCR Unused in AVR32UC
73 292 TLBARLO Unused in AVR32UC
74 296 TLBARHI Unused in AVR32UC
75 300 PCCNT Unused in AVR32UC
76 304 PCNT0 Unused in AVR32UC
77 308 PCNT1 Unused in AVR32UC
78 312 PCCR Unused in AVR32UC
79 316 BEAR Bus Error Address Register
80 320 MPUAR0 MPU Address Register region 0
81 324 MPUAR1 MPU Address Register region 1
82 328 MPUAR2 MPU Address Register region 2
83 332 MPUAR3 MPU Address Register region 3
84 336 MPUAR4 MPU Address Register region 4
85 340 MPUAR5 MPU Address Register region 5
86 344 MPUAR6 MPU Address Register region 6
87 348 MPUAR7 MPU Address Register region 7
88 352 MPUPSR0 MPU Privilege Select Register region 0
89 356 MPUPSR1 MPU Privilege Select Register region 1
Table 4-3. System Registers (Continued)
Reg # Address Name Function
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4.5 Exceptions and Interrupts
In the AVR32 architecture, events are used as a common term for exceptions and interrupts.
AVR32UC incorporates a p owerf ul event han dling sche me. The d iff eren t eve nt sou rces, like Ille-
gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined
behavior when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execut ion is passed
to an event handler at an address specified in Table 4-4 on page 38. Most of the handlers ar e
placed sequentially in the code space starting at the address specified by EVBA, with four bytes
between each handler. This gives ample space for a jump instruction to be placed there, jump-
ing to the event r outine it self. A few critical handlers have larger spacing between them, allowing
the entire event r outine t o be placed d irect ly at t he addr ess sp ecified by t he EVBA- relat ive o ffs et
generated by ha rdware. All interrupt sou rces have autovectored int errupt service routine (I SR)
addresses. This allows the interrupt controller to directly specify the ISR address as an address
90 360 MPUPSR2 MPU Privilege Select Register region 2
91 364 MPUPSR3 MPU Privilege Select Register region 3
92 368 MPUPSR4 MPU Privilege Select Register region 4
93 372 MPUPSR5 MPU Privilege Select Register region 5
94 376 MPUPSR6 MPU Privilege Select Register region 6
95 380 MPUPSR7 MPU Privilege Select Register region 7
96 384 MPUCRA Unused in this version of AVR32UC
97 388 MPUCRB Unused in this version of AVR32UC
98 392 MPUBRA Unused in this version of AVR32UC
99 396 MPUBRB Unused in this version of AVR32UC
100 400 MPUAPRA MPU Access Permission Register A
101 404 MPUAPRB MPU Access Permission Register B
102 408 MPUCR MPU Control Register
103 412 SS_STATUS Secure State Status Register
104 416 SS_ADRF Secure State Address Flash Register
105 420 SS_ADRR Secure State Address RAM Register
106 424 SS_ADR0 Secure State Address 0 Register
107 428 SS_ADR1 Secure State Address 1 Register
108 432 SS_SP_SYS Secure State Stack Pointer System Register
109 436 SS_SP_APP Secure State Stack Pointer Application Register
110 440 SS_RAR Secure State Return Address Register
111 444 SS_RSR Secure State Return Status Register
112-191 448-764 Reserved Reserved for future use
192-255 768-1020 IMPL IMPLEMENTATION DEFINED
Table 4-3. System Registers (Continued)
Reg # Address Name Function
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relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384
bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),
not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up
appropriately. The same mechanisms are used to service all different types of events, including
interrupt requests, yielding a uniform event handling scheme.
An interrupt cont roller does t he priority ha ndling of the int errupts and p rovides the autovect or off-
set to the CPU.
4.5.1 System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should po int to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
4.5.2 Exceptions and Interrupt Requests
When an event other than scall or deb ug request is received by the core, the following act ions
are performed atomically:
1. The pending e vent will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Re gister are used to mask different events. Not all ev ents can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits co rresponding t o all sour ces with eq ual or lo w er priority. This inh ibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the ev ent is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are a lso automatically stored to stack. Storing the Status
Register ensur es that the core is returned to the pr evious execution mode when the
current ev ent handlin g is co mplete d. When exceptions occur, both the EM and GM bits
are set, a nd the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address un iqu ely iden tifie s th e exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and th e corr ect regi s-
ter file bank is selected. The address of the event handler, as shown in Table 4-4 on
page 38, is loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Addr ess Register ar e popped f rom t he system st ack and r est ored to t he Statu s Re g-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains informa tion allowin g th e core t o resum e ope ra tion in t he p re vious e xecut ion mode. T his
concludes the event handling.
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4.5.3 Supervisor Calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall ins truction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. Th e scall mechanism is designed so th at a minimal
execution cycle ov erhead is experienced when pe rforming supervisor routine ca lls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set refer ence. In orde r to allow the scall ro utine to return to th e
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
4.5.4 Debug Requests
The AVR32 architecture d efines a dedicate d Debug mode. Wh en a debug requ est is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the
Debug Exception handler. By de fault, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to the pr evious context.
4.5.5 Entry Points for Events
Several different event handler entry points exist. In AVR32UC, the reset address is
0x80000000. This places the reset address in the boot flash memor y area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds u p execution by removin g the need for a ju mp instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to sig nal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All interrupt requests have entry points located at an offset relative to EVBA. This autovector off-
set is specified by an interrupt controller. The programmer must make sure that none of the
autovector offsets interfere with the placement of other code. The autovector offset has 14
address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash mem ory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on t he same instruction, the y are handled in a prior itized way. The priorit y
ordering is presented in Table 4-4 on page 38. If events occur on several instructions at different
locations in the pipeline, the events on the oldest instruction are always handled before any
events on any younger instruction, even if the younger instruction has events of higher priority
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than the oldest instruction. An instruction B is younger than an instruction A if it was sent down
the pipeline later than A.
The addresses and priority of simultaneous events ar e shown in Table 4-4 on page 38. Some of
the exceptions are unuse d in AVR3 2UC since it has no MM U, co pr ocessor in te rface, or floa tin g-
point unit.
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Table 4-4. Priority and Handler Addresses for Events
Priority Handler Ad dr es s Name Event source Stored Return Address
1 0x80000000 Reset External input Undefined
2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction
3 EVBA+0x00 Unrecoverable e xception Internal PC of offending instruction
4 EVBA+0x04 TLB multiple hit MPU PC of offending instruction
5 EVBA+0x08 Bus error data fetch Data bus First non-completed instruction
6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction
7 EVBA+0x10 NMI External input First non-completed instruction
8 Autovectored Interrup t 3 request External input First non-completed instruction
9 Autovectored Interrup t 2 request External input First non-completed instruction
10 Autovectored Interrupt 1 requ est External inpu t Fi rst non-completed instruction
11 Autovectored Interrupt 0 requ est External inpu t Fi rst non-completed instruction
12 EVBA+0x14 Instruction Address CP U PC of offending instruction
13 EVBA+0x50 ITLB Miss MPU PC of offending instruction
14 EVBA+0x18 ITLB Protection MPU PC of offending instruction
15 EVBA+0x1C Breakpoint OCD system First non-completed instruction
16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction
17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction
18 EVBA+0x28 Privilege violation Instruction PC of offending instruction
19 EVBA+0x2C Floating-point UNUSED
20 EVBA+0x30 Coprocessor absent Instruction PC of offending instruction
21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2
22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction
23 EVBA+0x38 Data Address (Write) CPU PC of offending instruction
24 EVBA+0x60 DTLB Miss (Read) MPU PC of offending instruction
25 EVBA+0x70 DTLB Miss (Write) MPU PC of offending instruction
26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction
27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction
28 EVBA+0x44 DTLB Modified UNUSED
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5. Memories
5.1 Embedded Memories
•Internal High-Speed Flash (See Table 5-1 on page 40)
– 512 Kbytes
– 256 Kbytes
– 128 Kbytes
– 64 Kbytes
• 0 Wait State Access at up to 33 MHz in Worst Case Conditions
• 1 Wait State Access at up to 66 MHz in Worst Case Conditions
• Pipelined Flash Ar chitecture, allowing b urst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
• 100 000 Write Cycles, 15-year Data Retention Capability
• 4ms Page Programming Time and 8ms Full-Chip Erase Time
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 64 Fuses, 32 Of Which Are Preserved During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
•Internal High-Speed SRAM, Single-cycle access at full speed (See Table 5-1 on page 40)
– 64 Kbytes
– 32 Kbytes
– 16 Kbytes
•Supplementary Internal High-Speed System SRAM (HSB RAM), Single-cycle access at full speed
– Memory space available on System Bus for peripherals data.
– 4 Kbytes
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5.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1. AT32UC3C Physical Memory Map
Device Start Address AT32UC3 Derivatives
C0512C C1512C
C2512C C0256C C1256C
C2256C C0128C C1128C
C2128C C064C C164C
C264C
Embedded
SRAM 0x0000_0000 64 KB 64 KB 64 KB 64 KB 32 KB 32 KB 16 KB 16 KB
Embedded
Flash 0x8000_0000 512 KB 512 KB 256 KB 256 KB 128 KB 128 KB 64 KB 64 KB
SAU 0x9000_0000 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB
HSB
SRAM 0xA000_0000 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB
EBI SRAM
CS0 0xC000_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
CS2 0xC800_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
CS3 0xCC00_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
CS1
/SDRAM
CS0
0xD000_0000 128 MB - 128 MB - 128 MB - 128 MB -
HSB-PB
Bridge C 0 xFFFD_0 000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
HSB-PB
Bridge B 0xFFFE_0000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
HSB-PB
Bridge A 0xFFFF_0000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
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5.3 Peripheral Address Map
Table 5-2. Flash Memory Param e te rs
Part Number Flash Size
(FLASH_PW)
Number of
pages
(FLASH_P)
Page size
(FLASH_W)
AT32UC3C0512C
AT32UC3C1512C
AT32UC3C2512C 512 Kbytes 1024 128 words
AT32UC3C0256C
AT32UC3C1256C
AT32UC3C2256C 256 Kbytes 512 128 words
AT32UC3C0128C
AT32UC3C1128C
AT32UC3C2128C 128 Kbytes 256 128 words
AT32UC3C064C
AT32UC3C164C
AT32UC3C264C 64 Kbytes 128 128 words
Table 5-3. Peripheral Address Mapping
Address Peripheral Name
0xFFFD0000 PDCA Peripheral DMA Controller - PDCA
0xFFFD1000 MDMA Memory DMA - MDMA
0xFFFD1400 USART1 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART1
0xFFFD1800 SPI0 Serial Peripheral Interface - SPI0
0xFFFD1C00 CANIF Control Area Network interface - CANIF
0xFFFD2000 TC0 Timer/Counter - TC0
0xFFFD2400 ADCIFA ADC controller interface with Touch Screen functionality
- ADCIFA
0xFFFD2800 USART4 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART4
0xFFFD2C00 TWIM2 Two-wire Master Interface - TWIM2
0xFFFD3000 TWIS2 Two-wire Slave Interf ace - TWI S2
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0xFFFE0000 HFLASHC Flash Controller - HFLASHC
0xFFFE1000 USBC USB 2.0 OTG Interface - USBC
0xFFFE2000 HMATRIX HSB Matrix - HMATRIX
0xFFFE2400 SAU Secure Access Unit - SAU
0xFFFE2800 SMC Static Memory Controller - SMC
0xFFFE2C00 SDRAMC SDRAM Controller - SDRAMC
0xFFFE3000 MACB Ethernet MAC - MAC B
0xFFFF0000 INTC Interrupt controller - INTC
0xFFFF0400 PM Power Manager - PM
0xFFFF0800 SCIF System Control Interface - SCIF
0xFFFF0C00 AST Asynchronous Timer - AST
0xFFFF1000 WDT Watchdog Timer - WDT
0xFFFF1400 EIC External Interrupt Controller - EIC
0xFFFF1800 FREQM Frequency Meter - FREQM
0xFFFF2000 GPIO General Purpose Input/Output Controller - GPIO
0xFFFF2800 USART0 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART0
0xFFFF2C00 USART2 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART2
0xFFFF3000 USART3 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART3
0xFFFF3400 SPI1 Serial Peripheral Interface - SPI1
Table 5-3. Peripheral Address Mapping
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5.4 CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bu s, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
0xFFFF3800 TWIM0 Two-wire Master Interface - TWIM0
0xFFFF3C00 TWIM1 Two-wire Master Interface - TWIM1
0xFFFF4000 TWIS0 Tw o- wire Slave Interface - TWIS0
0xFFFF4400 TWIS1 Tw o- wire Slave Interface - TWIS1
0xFFFF4800 IISC Inter-IC Sound (I2S) Controller - IISC
0xFFFF4C00 PWM Pulse Width Modulation Controlle r - PWM
0xFFFF5000 QDEC0 Quadrature Decoder - QDEC0
0xFFFF5400 QDEC1 Quadrature Decoder - QDEC1
0xFFFF5800 TC1 Timer/Counter - TC1
0xFFFF5C00 PEVC Peripheral Event Controller - PEVC
0xFFFF6000 ACIFA0 Analog Comparators Interface - ACIFA0
0xFFFF6400 ACIFA1 Analog Comparators Interface - ACIFA1
0xFFFF6800 DACIFB0 DAC interface - DACIFB0
0xFFFF6C00 DACIFB1 DAC interface - DACIFB1
0xFFFF7000 AW aWire - AW
Table 5-3. Peripheral Address Mapping
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The following GPIO registers are mapped on the loca l bus:
Table 5-4. Local bus mapped GPIO registers
Port Register Mode Local Bus
Address Access
0 Output Driver Enable Register (ODER) WRITE 0x4000_0040 Write-only
SET 0x4000_0044 Write-only
CLEAR 0x4000_0048 Write-only
TOGGLE 0x4000_004C Write-only
Output Value Register (OVR) WRITE 0x4000_0050 Write-o nly
SET 0x4000_0054 Write-only
CLEAR 0x4000_0058 Write-only
TOGGLE 0x4000_005C Write-only
Pin Value Registe r (PVR) - 0x4000_0060 Read-only
1 Output Driver Enable Register (ODER) WRITE 0x4000_0240 Write-only
SET 0x4000_0244 Write-only
CLEAR 0x4000_0248 Write-only
TOGGLE 0x4000_024C Write-only
Output Value Register (OVR) WRITE 0x4000_0250 Write-o nly
SET 0x4000_0254 Write-only
CLEAR 0x4000_0258 Write-only
TOGGLE 0x4000_025C Write-only
Pin Value Registe r (PVR) - 0x4000_0460 Read-only
3 Output Driver Enable Register (ODER) WRITE 0x4000_0440 Write-only
SET 0x4000_0444 Write-only
CLEAR 0x4000_0448 Write-only
TOGGLE 0x4000_044C Write-only
Output Value Register (OVR) WRITE 0x4000_0450 Write-o nly
SET 0x4000_0454 Write-only
CLEAR 0x4000_0458 Write-only
TOGGLE 0x4000_045C Write-only
Pin Value Registe r (PVR) - 0x4000_0460 Read-only
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4 Output Driver Enable Register (ODER) WRITE 0x4000_0640 Write-only
SET 0x4000_0644 Write-only
CLEAR 0x4000_0648 Write-only
TOGGLE 0x4000_064C Write-only
Output Value Register (OVR) WRITE 0x4000_0650 Write-o nly
SET 0x4000_0654 Write-only
CLEAR 0x4000_0658 Write-only
TOGGLE 0x4000_065C Write-only
Pin Value Registe r (PVR) - 0x4000_0660 Read-only
Table 5-4. Local bus mapped GPIO registers
Port Register Mode Local Bus
Address Access
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6. Supply and Startup Considerations
6.1 Supply Considerations
6.1.1 Power Supplies
The AT32UC3C has several types of power supply pins:
•VDDIO: Powers I/O lines and the flash. 2 Voltage ranges available: 5V or 3.3V nominal.
•VDDANA: Powers the Analog part of the device (Analog I/Os, ADC, ACs, DACs). 2 voltage ranges
available: 5V or 3.3V nominal.
•VDDIN_5: Input voltage for the 1.8V and 3.3V regulators. 2 Voltage ranges available: 5V or 3.3V
nominal.
•VDDIN_33:
– USB I/O power supply
– if the device is 3.3V powered: Input voltage, voltage is 3.3V nominal.
– if the device is 5V powered: stabilization for the 3.3V voltage regulator, requires external
capacitors
•VDDCORE: Stabilization for the 1.8V voltage regulator, requires external capacitors.
•GNDCORE: Ground pins for the voltage regulators and the core.
•GNDANA: Ground pin for Analog par t of the design
•GNDPLL: Ground pin for the PLLs
•GNDIO: Ground pins for the I/O
See ”Electrical Characteristics” on page 50 for power consumption on the various supply pins.
For decoupling recommendations for the different power supplies, please refer to the schematic
checklist.
6.1.2 Voltage Regulators
The AT32UC3C embeds two voltage regulators:
• One 1.8V internal regulator that converts from VDDIN_5 to 1.8V. The regulator supplies the
output voltage on VDDCORE.
• One 3.3V internal regulator that converts from VDDIN_5 to 3.3V. The regulator supplies the
USB pads. If the USB is not used, the 3.3V regulator can be disabled through the
VREG33CTL field of the VREGCTRL SCIF register.
6.1.3 Regulators Connection
The AT32UC3C supports two p ower supply configurations.
• 5V single supply mode
• 3.3V single supply mode
6.1.3.1 5V Single Supply Mode
In 5V single supply mode, the 1.8V internal regulator is connected to the 5V source (VDDIN_ 5
pin) and its output feeds VDDCORE.
The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB
pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field
of the VREGCTRL SCIF register.
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Figure 6-1 on page 47 shows the power schematics to be used for 5V single supply mode. All
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO =
VDDANA).
Figure 6-1. 5V Single Power Supply mode
6.1.3.2 3.3V Single Supply Mode
In 3.3V single supply mode, the VDDIN_5 and VDDIN_33 pins should be connected together
exter nally. The 1.8V inter nal regulator is connected to the 3.3V source (VDDIN_5 pin) and its
output feeds VDDCORE.
The 3.3V regulator should be disabled once the circuit is running through the VREG33CTL field
of the VREGCTRL SCIF register.
Figure 6-2 on page 48 shows the power schematics to be used for 3.3V single supply mode. All
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIN_33 =
VDDIO = VDDANA).
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Figure 6-2. 3 Single Power Supply Mode
6.1.4 Power-up Sequence
6.1.4.1 Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 7-2 on page 51 .
Recommended order for power supplies is also described in this table.
6.1.4.2 Minimum Rise Rate
The integrated Power-Reset circuitry monitoring the powering supply requires a minimum rise
rate for the VDDIN_5 power supply.
See Table 7-2 on page 51 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, the following configuration can be used:
• A logic “0” value is applied during power-up on pin RESET_N until:
– VDDIN_5 rises above 4.5V in 5V single supply mode.
– VDDIN_33 rises above 3V in 3.3V single supply mode.
3.0-3.6V
VDDIN_33
VDDIO
CPU
Peripherals
Memories
SCIF, BOD,
RCSYS
3.3V
Reg
+
-
Analog: ADC, AC, DAC, ...
VDDIN_5 VDDANA GNDANA
VDDCORE
CCORE2 CCORE1
GNDCORE
GNDPLL
PLL
GNDIO
BOD50
BOD33
1.8V
Reg
BOD18
POR
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6.2 Startup Considerations
This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is
controlled by the Power Manager. For specific details, refer to the Power Manager chapter.
6.2.1 Starting of clocks
At power-up, the BOD33 and the BOD18 are enabled. The device will be held in a reset state by
the power-up circuitry, until the VDDIN_33 (resp. VDDCORE) has reached t he reset threshold of
the BOD33 (resp BOD18). Refer to the Electrical Characteristics for the BOD thresholds. Once
the power has stabilized, the device will use the System RC Oscillator (RC SYS, 115KHz typical
frequency) as clock sour ce. Th e BO D18 a nd BOD33 are ke pt enab led or are disab led accor ding
to the fuse settings (See the Fuse Setting section in the Flash Controller chapter).
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all par ts of th e system rece ive a clock with the same frequency as the inter-
nal RC Oscillator.
6.2.2 Fetching of initial instructions
After reset has been released, the AVR32UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The internal Flash uses VDDIO voltage during read and write operations. It is recommended to
use the BOD33 to monitor this voltage and make sure the VDDIO is above the minimum level
(3.0V).
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
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7. Electrical Characteristics
7.1 Absolute Maximum Ratings*
7.2 Supply Characteristics
The following chara cteristics are applica ble to the ope rating temperat ure range: T A = -40°C to 85°C, un less otherwise spec-
ified and are valid for a junction temperature up to TJ = 100°C. Please refer to Section 6. ”Supply and Startup
Considerations” on page 46.
Operating temperature..................................... -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage temperature...................................... -60°C to +150°C
Voltage on any pin except DM/DP/VBUS
with respect to ground...................-0.3V to VCC+VDDIO+0.3V
Voltag e on DM/DP with respect to ground.........-0.3V to +3.6V
Voltage on VBUS with respect to ground...........-0.3V to +5.5V
Maximum operating voltage (VDDIN_5)........................... 5.5V
Maximum operating voltage (VDDIO, VDDANA).............. 5.5V
Maximum operating voltage (VDDIN_33)......................... 3.6V
DC current per I/O pin................................................. TBD mA
DC current VCC and GND pins...................................TBD mA
Table 7-1. Supply Characteristics
Symbol Parameter Condition
Voltage
Min Max Unit
VVDDIN_5 DC supply internal regulators 5V range 4.5 5.5 V
3V range 3.0 3.6 V
VVDDIN_33 DC supply USB I/O only in 3V range 3.0 3.6 V
VVDDANA DC supply analog part 5V range 4.5 5.5 V
3V range 3.0 3.6 V
VVDDIO DC supply peripheral I/O 5V range 4.5 5.5 V
3V range 3.0 3.6 V
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7.3 Maximum Clock Frequencies
These parameters are given in the following conditions:
•V
VDDCORE = 1.85V
• Temperature = -40°C to 85°C
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.4 Power Consumption
The values in Table 7-4 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions core supply (Figure 7-1)
–V
DDIN_5 = VDDIN_33 = 3.3V
–V
VDDCORE = 1.85V, supplied by the internal regulator
–V
DDIO = 3.3V
–V
DDANA: 3.3V
– Internal 3.3V regulator is off.
•T
A = 25°C
Table 7-2. Supply Rise Rates and Order
Symbol Parameter
Rise Rate
Min Max Comment
VVDDIN_5 DC supply internal 3.3V regulator 0.01 V/ms 1.25 V/us
VVDDIN_33 DC supply internal 1.8V regulator 0.01 V/ms 1.25 V/us
VVDDIO DC supply peripheral I/O 0.01 V/ms 1.25 V/us Rise after or at the same time as
VDDIN_5, VDDIN_33
VVDDANA DC supply analog part 0.01 V/ms 1.25 V/u s Rise after or at the same time as
VDDIN_5, VDDIN_33
Table 7-3. Clock Frequencies
Symbol Parameter Conditions Min Max(1) Units
fCPU CPU clock frequency 66 MHz
fPBA PBA clock frequency 66 MHz
fPBB PBB clock frequency 66 MHz
fPBC PBC clock frequency 66 MHz
fGCLK0 GCLK0 clock frequency Generic clock for USBC 50 MHz
fGCLK1 GCLK1 clock frequency Generic clock for CANIF 66 MHz
fGCLK2 GCLK2 clock frequency Generic clock for AST 80 MHz
fGCLK4 GCLK4 clock frequency Generic clock for PWM 133 MHz
fGCLK11 GCLK11 clock frequency Generic clock for IISC 50 MHz
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• I/Os are configured as inputs, with internal pull-up enabled.
• Oscillators
– OSC0/1 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) stopped
– PLL0 running
– PLL1 stopped
• Clocks
– External clock on XIN0 as main clock source (10MHz)
– CPU, HSB, and PBB clocks undivided
– PBA, PBC clock divided by 4
– The following peripheral clocks running
• PM, SCIF, AST, FLASHC, PBA bridge
– All other peripheral clocks stopped
Table 7-4. Power Consumption for Different Operating Modes
Mode Conditions Measured on Consumption Typ Unit
Active -CPU running a recursive Fibonacci algorithm
Amp
TBD
µA/MHz
-CPU running a divisio n alg o rithm TBD
Idle TBD
Frozen TBD
Standby TBD
Stop 73
µA
DeepStop 43
Static -OSC32K and AST running 31
-AST and OSC32K stopped 31
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Figure 7-1. Measurement Schematic
7.4.1 Peripheral Power Consumption
The values in Table 7-5 are measured values of power consumption under the following
conditions.
• Operating conditions core supply (Figure 7-1)
–V
DDIN_5 = VDDIN_33 = 3.3V
–V
VDDCORE = 1.85V , supplied by the internal regulator
–V
DDIO = 3.3V
–V
DDANA: 3.3V
– Internal 3.3V regulator is off.
•T
A = 25°C
• I/Os are configured as inputs, with internal pull-up enabled.
• Oscillators
– OSC0/1 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) stopped
– PLL0 running
Amp
VDDANA
VDDIO
VDDIN_5
VDDCORE
GNDCORE
GNDPLL
VDDIN_33
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– PLL1 stopped
• Clocks
– External clock on XIN0 as main clock source.
– CPU, HSB, and PB clocks undivided
Consumption active is the added current consumption when the module clock is turned on and
when the module is doing a typical set of operations.
Table 7-5. Typical Current Consumption by Peripheral
Peripheral Typ Consumption Active Unit
ACIFA(1) TBD
µA/MHz
ADCIFA(1) TBD
AST TBD
CANIF TBD
DACIFB(1) TBD
EBI TBD
EIC TBD
FLASHC TBD
FREQM TBD
GPIO TBD
HMATRIX TBD
IISC TBD
INTC TBD
MACB TBD
MDMA TBD
PDCA TBD
PEVC TBD
PWM TBD
QDEC TBD
SAU TBD
SDRAMC TBD
SMC TBD
SPI TBD
TC TBD
TWIM TBD
TWIS TBD
USART TBD
USBC TBD
WDT TBD
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Notes: 1. Includes the current consumption on VDDANA.
7.5 I/O Pin Characteristics
Note: 1. All PA, PB, PC, PD pins have drive x1/x2 capabilities except PB00, PB01, PB02, PB03, PB30, PB31, PC02, PC03, PC04,
PC05, PC06, PC07 which have drive x1 capability and PB06, PB21, PB26, PD02, PD06, PD13 which have drive x2/x4
capabilities. The drive strength is programmable through ODCR0, ODCR0S, ODCR0C, ODCR0T registers of GPIO.
Table 7-6. Normal I/O Pin Characteristics
Symbol Parameter Condition Min Typ Max Units
RPULLUP Pull-up resistance 15 kOhm
RPULLDOWN Pull-down resistance 10 kOhm
VIL Input low-leve l voltage 0.8 V
VIH Input high-level voltage 2.0 V
VOL Output low-level voltage
IOL = -3.5mA for pad drive x1(1)
0.4
V
IOL = -7mA for pad drive x2(1)
IOL = -14mA for pad drive x4(1)
VOH Output high-level voltage
IOL = 3.5mA for pad drive x1(1)
VDDIO - 0.7 V
IOL = 7mA for pad drive x2(1)
IOL = 14mA for pad drive x4(1)
fMAX Output frequency
VVDDIO = 3.0V, load = 10pF TBD MHz
VVDD = 3.0V, load = 30pF TBD MHz
VVDDIO =4.5V, load = 10pF TBD MHz
VVDD = 4.5V, load = 30pF TBD MHz
tRISE Rise time
VVDD = 3.0V, load = 10pF TBD ns
VVDD = 3.0V, load = 30pF TBD ns
VVDDIO =4.5V, load = 10pF TBD ns
VVDD = 4.5V, load = 30pF TBD ns
tFALL Fall time
VVDD = 3.0V, load = 10pF TBD ns
VVDD = 3.0V, load = 30pF TBD ns
VVDDIO =4.5V, load = 10pF TBD ns
VVDD = 4.5V, load = 30pF TBD ns
ILEAK Input leakage current Pull-up resistors disabled TBD µA
CIN Input capacitance TBD pF
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7.6 Oscillator Characteristics
7.6.1 Oscillator (OSC0 and OSC1) Characteristics
7.6.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital cloc k is applied
on XIN0 or XIN1.
7.6.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected
between XIN and XOUT as shown in Figure 7-2. The user must choose a crystal oscillator
where the crystal lo ad capacitan ce CL is within the range given in the table. The exact value of CL
can be found in the crystal datasheet. The capacitance of the e xternal capacitors (CLEXT) can
then be computed as follows:
where CPCB is the capacitance of the PCB and Ci is the internal equivalent load capacitance.
Figure 7-2. Oscillator Connection
Table 7-7. Digital Clock Characteristics
Symbol Parameter Conditions Min Typ Max Units
fCPXIN XIN clock frequency 50 MHz
tCPXIN XIN clock duty cycle 40 60 %
tSTARTUP Startup time 0 cycles
CIN XIN input capacitance TBD pF
CLEXT 2C
LCi
–()CPCB
–=
XIN
XOUT
CLEXT
CLEXT
Ci
CL
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Notes: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics
7.6.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital cloc k is applied
on XIN32.
7.6.2.2 Crystal Oscillator Characteristics
Figure 7-2 and the equation above also applies to the 32KHz oscillator connection. The user
must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can then be found in the crystal datasheet..
Table 7-8. Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Crystal oscillator frequency 0.4(1) 20(1) MHz
CLCrystal load capacitance 12 pF
CiInternal equivalent load capacitance 2 pF
tSTARTUP Startup time TBD cycles
IOSC Current consumption TBD µA
Table 7-9. Digital 32KHz Clock Characterist ics
Symbol Parameter Conditions Min Typ Max Units
fCPXIN XIN32 clock frequency 32 768 Hz
tCPXIN XIN32 cloc k duty cycle TBD TBD %
tSTARTUP Startup time TBD cycles
CIN XIN32 input capacitance TBD pF
Table 7-10. 32 KHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Crystal oscillato r frequency 32 768 Hz
tSTARTUP Startup time RS = TBDk Ohm, CL = TBDpF TBD cycles
CLCrystal load capacitance TBD TBD pF
CiInternal equivalent load
capacitance TBD pF
IOSC32 Current consumption TBD µA
RSEquivalent series resistance 32 768Hz TBD TBD kOhm
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7.6.3 120MHz RC Oscillator (RC120M) Ch aracteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.6.4 System RC Oscillator (RCSYS) Characteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.6.5 8MHz/1MHz RC Oscillator (RC8M) Characteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
2. Please refer to the SCIF chapter for details.
7.6.6 Phase Lock Loop (PLL0 and PLL1) Characteristics
Table 7-11. Internal 120MHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency TBD 120(1) TBD MHz
IRC120M Current consumption 1.85(1) mA
tSTARTUP Startup time VVDDCORE = 1.8V 3(1) µs
Table 7-12. System RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency TBD 115(1) TBD kHz
Table 7-13. 8MHz/1MHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency SCIF.RCCR8.FREQMODE = 0(2) TBD 8(1) TBD MHz
SCIF.RCCR8.FREQMODE = 1(2) TBD 1(1) TBD MHz
Table 7-14. PLL Character istics
Symbol Parameter Conditions Min Typ Max Unit
fVCO Output frequency 80 240 MHz
fIN Input frequency 4 16 MHz
IPLL Current consumption 500 µA
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7.7 Flash Characteristics
Table 7-15 gives the device maximum operating frequency dep ending on the number of flash
wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used
when accessing the fla sh memory.
Table 7-15. Maximum Operating Frequency
Flash Wait States Read Mode Maximum Operating Frequency
0 1 cycle 33MHz
1 2 cycles 66MHz
Table 7-16. Flash Char act er istic s
Symbol Parameter Conditions Min Typ Max Unit
tFPP Page programming time
fCLK_HSB = 66MHz
4
ms
tFPE Page erase time 4
tFFP Fuse programming time TBD
tFEA Full chip erase time (EA) 8
tFCE JTAG chip erase time (CHIP_ERASE) fCLK_HSB = 115kHz TBD
Table 7-17. Flash Endurance and Data Retention
Symbol Parameter Conditions Min Typ Max Unit
NFARRAY Arr ay endurance (write/page) 100k cycles
NFFUSE General Purpose fuses endurance (write/bit) 10k cycles
tRET Data retention 15 years
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7.8 Analog Characteristics
7.8.1 1.8V Voltage Regulator Char acteristics
7.8.2 3.3V Voltage Regulator Char acteristics
Table 7-18. 1.8V Voltage Regulator Electrical Characteristics
Symbol Parameter Condition Min Typ Max Units
VVDDIN_5 Input v oltage range 5V range 5 V
3V range 3.3 V
VVDDCORE Output voltage, calibrated value 1.85 V
IOUT DC output curren t Normal mode TBD mA
Low power mode TBD mA
IVREG Static current of regulator Normal mode TBD µA
Low power mode TBD µA
Table 7-19. Decoupling Requirements
Symbol Parameter Condition Typ Techno. Units
CIN1 Input regulator capacitor 1 470 NPO nF
CIN2 Input regulator capacitor 2 2.2 X7R nF
COUT1 Output regulator capacitor 1 470 NPO µF
COUT2 Output regulator capacitor 2 2.2 X7R nF
Table 7-20. 3.3V Voltage Regulator Electrical Characteristics
Symbol Parameter Condition Min Typ Max Units
VVDDIN_5 Input v oltage range 5V
VVDDIN_33 Output voltage, calibrated value 3.3 V
IOUT DC output curren t Normal mode TBD mA
Low power mode TBD mA
IVREG Static current of regulator Normal mode TBD µA
Low power mode TBD µA
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7.8.3 1.8V Brown Out Detector (BOD18) Characteristics
The values in Table 7-21 describe the values of the BODLEVEL in the flash General Purpose
Fuse register.
Notes: 1. These values are guaranteed by design and will be updated after characterization of current
silicon.
7.8.4 3.3V Brown Out Detector (BOD33) Characteristics
The values in Table 7-23 describe the values of the BOD33.LEVEL field in the SCIF module.
Table 7-21. BODLEVEL Values
BODLEVEL Value Parameter Min Typ(1) Max Units
01.40V
20 1.50 V
26 threshold at power-up sequence 1.57 V
28 1.60 V
32 1.65 V
36 1.70 V
40 1.75 V
44 1.80 V
52 1.90 V
58 1.95 V
64 2.00 V
Table 7-23. BOD33.LEVEL Values
BOD33.LEVEL Value Parameter Min Typ(1) Max Units
32.10V
62.20V
11 2.30 V
17 2.40 V
22 2.50 V
27 2.60 V
31 threshold at power-up sequence 2.63 V
33 2.70 V
39 2.80 V
44 2.90 V
49 3.00 V
53 3.10 V
60 3.20 V
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Notes: 1. These values are guaranteed by design and will be updated after characterization of current
silicon.
7.8.5 5V Brown Out Detector (BOD50) Characteristics
The values in Table 7-25 describe the values of the BOD50.LEVEL field in the SCIF module.
Notes: 1. These values are guaranteed by design and will be updated after characterization of current
silicon.
Table 7-25. BOD50.LEVEL Values
BOD50.LEVEL Value Parameter Min Typ(1) Max Units
73.25V
16 3.50 V
25 3.75 V
35 4.00 V
44 4.25 V
53 4.50 V
61 4.75 V
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7.8.6 Analog to Digital Conv erter (ADC) Chara cteris tics
Notes: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Notes: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Table 7-27. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Units
ADC clock frequency
12-bit resolution mode - VDDANA = 5V 1.5(1) MHz
10-bit resolution mode - VDDANA = 5V 2(1) MHz
8-bit resolution mode - VDDANA = 5V TBD MHz
12-bit resolution mode - VDDANA = 3.3V 1.2(1) MHz
10-bit resolution mode - VDDANA = 3.3V 1.6(1) MHz
8-bit resolution mode - VDDANA = 3.3V TBD MHz
Startup time Return from idle mode TBD µs
Conversion time
12-bit resolution mode
ADC clock = 1.5 MHz - VDDANA = 5V 8 ADC clock
10-bit resolution mode
ADC clock = 2MHz - VDDANA = 5V 7 ADC cloc k
8-bit resolution mode
ADC clock = TBD - VDDANA = 5V 6 ADC clock
12-bit resolution mode
ADC clock = 1.2 MHz - VDDANA = 3V 8 ADC clock
10-bit resolution mode
ADC clock = 1.6MHz - VDDANA = 3V 7 ADC clock
8-bit resolution mode
ADC clock = TBD - VDDANA = 3V 6 ADC clock
Throughput rate 12-bit resolution
ADC clock = 1.5 MHz - VDDANA = 5V 1.5 MSPS
10-bit resolution
ADC clock = 2 MHz - VDDANA = 5V 2 MSPS
12-bit resolution
ADC clock = 1.2 MHz - VDDANA = 3V 1.2 MSPS
10-bit resolution
ADC clock = 1.6 MHz - VDDANA = 3V 1.6 MSPS
Table 7-28. Reference Voltage
Parameter Conditions Min Typ Max Units
ADCREF0/ADCREF1 input voltage
range 5V Range 1(1) 3.5(1) V
3V Range 1(1) VVDDANA-0.7(1) V
ADCREF0/ADCREF1 average
current TBD TBD µA
Internal 1V reference 1.0(1) V
Internal 0.6*VDDANA reference 0.6*VVDDANA(1) V
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Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.8.6.1 ADC S/H Characteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Table 7-29. Decoupling re qu ire m en ts
Symbol Parameter Conditions Min Typ Max Units Units
CADCREFPN ADCREFP-ADCREFN
capacitance 100 nF
Table 7-30. ADC Inputs
Parameter Conditions Min Typ Max Units
ADC input voltage range 0(1) VVDDANA(1)
Input leakage current 1µA
External source impedance ADC used without S/H 1 kΩ
ADC used with S/H 3 kΩ
Table 7-31. Transfer Characteristics 12-bit Resolution Mode
Parameter Conditions Min Typ Max Units
Resolution Differential mode 12(1) Bit
Single-ended mode 11(1) Bit
Integral Non-Linearity (INL) TBD LSB
Differential Non-Linearity (DNL) TBD LSB
Offset error TBD LSB
Gain error TBD LSB
Table 7-32. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Units
Gain 1 to
64(1)
Resolution Gain = 1 with calibration 11(1) bits
Gain not equal to 1 9(1) bits
clock frequency 1.5(1) MHz
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7.8.7 Digital to Analog Converter (DAC) Characteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
2. DACREF corresponds to the inter nal or external DAC reference voltage depending on the DACREF settings
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Table 7-33. Channel Conversion Time and DAC Clock
Parameter Conditions Min Typ Max Units
Startup time TBD µs
Throughput rate
12-bit resolution
One S/H 1(1) MSPS
12-bit resolution
Two S/H 0.750(1) MSPS
Table 7-34. External Voltage Reference Input
Parameter Conditions Min Typ Max Units
DACREF input voltage range 1(1) TBD V
DACREF input capacitance 1(1) TBD pF
DACREF input resitance 1(1) TBD kΩ
DACREF average current TBD µA
Current consumption on VDDANA TBD mA
Table 7-35. DAC Outputs
Parameter Min Typ Max Units
Output range 0(1) VDACREF(1)(2)
Output settling time TBD µs
Output capacitance TBD pF
Output resitance TBD kΩ
Table 7-36. Transfer Characteristics
Parameter Conditions Min Typ Max Units
Resolution Differential mode 12(1) Bit
Integral Non-Linearity (INL) TBD LSB
Differential Non - linearity (DNL) TBD LSB
Offset error TBD LSB
Gain error TBD LSB
Calibrated Gain/Offset error TBD LSB
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7.8.8 Analog Comparator Characteristics
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
Table 7-37. Analog Comparator Characteristics
Parameter Conditions Min Typ Max Units
Positive input vo ltage range 0 VVDDANA V
Negative input voltage range 0 VVDDANA V
Offset +/-5(1) TBD mV
Hysteresis No TBD mV
Low 20(1) TBD mV
High 50(1) TBD mV
Propagation delay High Speed mode TBD ns
Low Speed mode TBD ns
Current consumption on VDDANA High Speed mode 170(1) µA
Low Speed mode 23(1) µA
Start-up time 10(1) µs
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7.9 Timing Characteristics
7.9.1 Startup, Reset, and Wake-up Timing
The startup, reset, and wake-up timings are calculated using the following for mula:
Where and are found in T able 7-38. is the period of the CPU clock. If
another clock source than RCSYS is selected as C PU clock the startup time of the oscillator,
, must added to the wake-up time in the stop, d eepstop, and static sleep modes.
Please refer to the source for the CPU clock in the ”Oscillator Characteristics” on page 56 for
more details about oscillator startup times.
Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon.
7.9.2 RESET_N characteristics
tt
CONST NCPU tCPU
×+=
tCONST
NCPU
tCPU
tOSCSTART
Table 7-38. Maximum Reset and Wake-up Timing (1)
Parameter Measuring Max (in µs) Max
Startup time from power-up, using
regulator
VDDIN_5 rising (TBD V/ms)
Time from VDDIN_5=0 to the first instruction
entering the decode stage of CPU. VDDCORE is
supplied by the internal regulator.
TBD 0
Startup time from reset release Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU. 1240(1) 0
Wake-up
Idle
From wake-up event to the first instruction of an
interrupt routine entering the decode stage of the
CPU.
0TBD
Frozen 0TBD
Standby 0TBD
Stop TBD TBD
Deepstop TBD TBD
Static TBD TBD
tCONST
NCPU
Table 7-39. RESET_N Clock Waveform Parameters
Symbol Parameter Condition Min. Typ. Max. Units
tRESET RESET_N minimum pulse length 2 * TRCSYS clock cycles
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8. Mechanical Characteristics
8.1 Thermal Considerations
8.1.1 Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package.
8.1.2 Junction Temperature
The average chip-junction temperatur e, TJ, in °C can be obtained from the following:
1.
2.
where:
•θJA = pack age thermal resistance, J unctio n-to-ambient (°C/ W), prov ided in Table 8-1 on page
68.
•θJC = package thermal resistance, Junction-to-ca se thermal resistance (°C/W), provided in
Table 8-1 on page 68.
•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
•P
D = device power consumption (W) estimated from data provided in the section ”Power
Consumption” on page 51.
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation shou ld be used to compute the resulting average chip-junction temperature TJ in °C.
Table 8-1. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA Junction-to-ambient thermal resistance No air flow TQFP64 TBD ⋅C/W
θJC Junction-to-case thermal resistance TQFP64 TBD
θJA Junction-to-ambient thermal resistance No air flow TQFP100 39.3 ⋅C/W
θJC Junction-to-case thermal resistance TQFP100 8.5
θJA Junction-to-ambient thermal resistance No air flow LQFP144 38.1 ⋅C/W
θJC Junction-to-case thermal resistance LQFP144 8.4
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC ))++=
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8.2 Package Drawings
Figure 8-1. QFN-64 packa g e dr awing
Note: The exposed pad is not connected to anything.
Table 8-2. Device and Package Maximum Weight
TBD mg
Table 8-3. Package Characteristics
Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3
Table 8-4. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 8-2. TQFP-64 package dr awing
Table 8-5. Device and Package Maximum Weight
TBD mg
Table 8-6. Package Characteristics
Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3
Table 8-7. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 8-3. TQFP-100 package drawing
Table 8-8. Device and Package Maximum Weight
500 mg
Table 8-9. Package Characteristics
Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3
Table 8-10. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 8-4. LQFP-144 pa ckage drawing
Table 8-11. Device and Package Maximum Weight
1300 mg
Table 8-12. Package Characteristics
Moisture Sensitivity Level Jdec J-STD0-20D - MSL 3
Table 8-13. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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8.3 Soldering Profile
Table 8-14 gives the recommended soldering profile from J-STD-20.
Note: It is recommended to apply a soldering temperature higher than 250°C.
A maximum of three reflow passes is allowed per component.
Table 8-14. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/sec
Preheat Temperature 175°C ±25°C Min. 150 °C, Max. 200 °C
Temperature Maintained Above 217°C 60-150 sec
Time within 5⋅C of Actual Peak Temperature 30 sec
Peak Temperature Range 260 °C
Ramp-down Rate 6 °C/sec
Time 25⋅C to Peak Temperature Max. 8 minutes
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9. Ordering Information
Table 9-1. Ordering Inform ation
Device Ordering Code Carrier Type Packa ge Temperature Operating Range
AT32UC3C0512C
AT32UC3C0512C-ALUES ES
LQFP 144
Industri al (-40°C to 85°C)
AT32UC3C0512C-ALUT Tray
AT32UC3C0512C-ALUR Tape & Reel
AT32UC3C0256C AT32UC3C0256C-ALUT Tray
AT32UC3C0256C-ALUR Tape & Reel
AT32UC3C0128C AT32UC3C0128C-ALUT Tray
AT32UC3C0128C-ALUR Tape & Reel
AT32UC3C064C AT32UC3C064C-ALUT Tray
AT32UC3C064C-ALUR Tape & Reel
AT32UC3C1512C
AT32UC3C1512C-AUES ES
TQFP 100
AT32UC3C1512C-AUT Tray
AT32UC3C1512C-AUR Tape & Reel
AT32UC3C1256C AT32UC3C1256C-AUT Tray
AT32UC3C1256C-AUR Tape & Reel
AT32UC3C1128C AT32UC3C1128C-AUT Tray
AT32UC3C1128C-AUR Tape & Reel
AT32UC3C164C AT32UC3C164C-AUT Tray
AT32UC3C164C-AUR Tape & Reel
AT32UC3C2512C
32UC3C2512C-A2UES ES TQ FP 6432UC3C2512C-A2UT Tray
32UC3C2512C-A2UR Tape & Reel
32UC3C2512C-Z2UES ES QFN 6432UC3C2512C-Z2UT Tray
32UC3C2512C-Z2UR Tape & Reel
AT32UC3C2256C
32UC3C2256C-A2UT Tray TQFP 64
32UC3C2256C-A2UR Tape & Reel
32UC3C2256C-Z2UT Tray QFN 64
32UC3C2256C-Z2UR Tape & Reel
AT32UC3C2128C
32UC3C2128C-A2UT Tray TQFP 64
32UC3C2128C-A2UR Tape & Reel
32UC3C2128C-Z2UT Tray QFN 64
32UC3C2128C-Z2UR Tape & Reel
AT32UC3C264C
32UC3C2128C-A2UT Tray TQFP 64
32UC3C2128C-A2UR Tape & Reel
32UC3C2128C-Z2UT Tray QFN 64
32UC3C2128C-Z2UR Tape & Reel
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10. Errata
10.1 rev D
10.1.1 AST
1. AST wake signal is released one ast clock cycle after the busy register is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY b it in the Status Register ( SR.BUSY) is cleare d. If e ntering slee p mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
10.1.2 GPIO
1. Clearing Interrupt flags can mask other interrupts
When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening
in the same clock cycle will not be registered.
Fix / Workaround
Read the PVR register of the port before and after clearing the interrupt to see if any pin
change has happened while clearing the interrupt. If any change occurred in the PVR
between the read s, they must be treated as an interrupt.
10.1.3 Power Manager
1. Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off th e CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after tu rning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
2. Requesting clocks in idle sleep modes will mask all other PB clocks than the
requested
In idle or frozen sleep mode, all the PB clocks will be frozen if the TWIS or the AST need to
wake the cpu up.
Fix/Workaround
Disable the TWIS or the AST before entering idle or frozen sleep mode.
10.1.4 SPI
1. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and
NCPHA==0
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When multiple chip selects are in use, if one of the baudrates is equal to 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault de tection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
4. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
10.1.5 TWI
1. TWIM SMBAL polarity is wrong
The SMBAL signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal goin g into the TWIM. When using both TWIM
and TWIS on the same pins, the SMBAL cannot be used.
10.1.6 USBC
1. UPINRQx.INRQ field is limited to 8-bits
In Host mode, when using the UPINRQx.INRQ feature together with the multi-packet mode
to launch a finite number of packet among multi-packet, the multi-packet size (located in the
descriptor table) is limited to the UPINRQx.INRQ value multiply by the pipe size.
Fix/Workaround
UPINRQx.INRQ value shall be less than the number of configured multi-packet.
10.1.7 WDT
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog rese t.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
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11. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring re visio n in th is section are referring to the document revision.
11.1 Rev. A – 10/10
1 Initial revision
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1 Description ............................................................................................... 3
2 Overview ................................................................................................... 5
2.1 Block diagram .... .... ... ... ................ .... ... ... ... ... ................. ... ... ... ... .... ................ ... ..5
2.2 Configuration Summary .....................................................................................6
3 Package and Pinout ................................................................................. 8
3.1 Package ....... ...... ....... ...... ....... ...... .... ...... ...... ....... ...... ....... ...... ... ....... ...... ....... .....8
3.2 Peripheral Multiplexing on I/O lines .................................................................10
3.3 Signals Description ................ ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ...18
3.4 I/O Line Considera tio ns ...................... ................ ... ... .... ... ................ ... ... .... ......24
4 Processor and Architecture .................................................................. 25
4.1 Features ..........................................................................................................25
4.2 AVR32 Architecture .........................................................................................25
4.3 The AVR32UC CPU ........................................................................................26
4.4 Programming Model ........................................................................................30
4.5 Exceptions and Interrupts ................................................................................34
5 Memories ................................................................................................ 39
5.1 Embedded Memories ......................................................................................39
5.2 Physical Memory Ma p ........ ... ................ ... ... .... ... ................ ... ... .... ... ................40
5.3 Peripheral Address Map ..................................................................................41
5.4 CPU Local Bus Mapping .................................................................................43
6 Supply and Startup Considerations ..................................................... 46
6.1 Supply Consideratio ns ........... ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ...46
6.2 Startup Considerations ....................................................................................49
7 Electrical Characteristics ...................................................................... 50
7.1 Absolute Maximu m Ra ting s* ........................................ ... ... ... ... .... ................ ...50
7.2 Supply Characteri stic s .............. ... ................ .... ... ... ... .... ... ... ................ ... .... ... ...50
7.3 Maximum Clock Frequencies ..........................................................................51
7.4 Power Consumption ........................................................................................51
7.5 I/O Pin Characteristic s . ................ .... ... ... ... ... .... ................ ... ... ... .... ... ................55
7.6 Oscillator Characteristics .................................................................................56
7.7 Flash Characteri st ic s ...... .... ... ................ ... ... .... ... ................ ... ... .... ... ................59
7.8 Analog Characteristics .....................................................................................60
7.9 Timing Characteristics .....................................................................................67
8 Mechanical Characteristics ................................................................... 68
80
32117A–10/2010
AT32UC3C
8.1 Thermal Considerations ..................................................................................68
8.2 Package Drawings .............. ... ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ...69
8.3 Soldering Profile ..............................................................................................73
9 Ordering Information ............................................................................. 74
10 Errata ....................................................................................................... 75
10.1 rev D ...................... ... ... ................ .... ... ... ... ................ .... ... ... ... ... ................. ... ...75
11 Datasheet Revision History .................................................................. 78
11.1 Rev. A – 10/10 .................................................................................................78
32117A–10/2010
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