Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES
• TTLcompatibleinputsandoutputs;tristateI/O
• RefreshInterval:
—1,024cycles/16ms
• RefreshMode:
—
RAS-Only,CAS-before-RAS(CBR),andHidden
• JEDECstandardpinout
• Singlepowersupply:
—5V±10%(IS41C16105C)
—3.3V±10%(IS41LV16105C)
• ByteWriteandByteReadoperationviatwoCAS
• IndustrialTemperatureRange-40oCto85oC
• Lead-freeavailable
DESCRIPTION
TheISSIIS41C16105CandIS41LV16105Care1,048,576x
16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1,024 random accesses
withinasinglerowwithaccesscycletimeasshortas20nsper
16-bitword.The ByteWritecontrol, ofupper andlower byte,
makestheIS41C16105Cidealforusein16-,32-bitwidedata
bussystems.
These features make the IS41C16105C and IS41LV16105C
ideally suited for high-bandwidth graphics, digital signal
processing,high-performancecomputingsystems,andperipheral
applications.
The IS41C16105C and IS41LV16105C are packaged in a
42-pin400-milSOJand400-mil44-(50-)pinTSOP(TypeII).
1Mx16
16Mb DRAM WITH FAST PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
Max.RASAccessTime(tr a c ) 50 60 ns
Max.CASAccessTime(tc a c ) 13 15 ns
Max.ColumnAddressAccessTime(ta a ) 25 30 ns
Min.FastPageModeCycleTime(tp c ) 20 25 ns
Min.Read/WriteCycleTime(tr c ) 84 104 ns
ADVANCED INFORMATION
APRIL 2010
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II) 42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 AddressInputs
I/O0-15 DataInputs/Outputs
WE WriteEnable
OE OutputEnable
RAS RowAddressStrobe
UCAS UpperColumnAddressStrobe
LCAS LowerColumnAddressStrobe
Vd d Power
GND Ground
NC NoConnection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774 3
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
TRUTH TABLE
Function RAS LCAS UCAS WE OE Address tR/tC I/O
Standby H H H X X X High-Z
Read:Word L L L H L ROW/COL Do u t
Read:LowerByte L L H H L ROW/COL LowerByte,Do u t
UpperByte,High-Z
Read:UpperByte L H L H L ROW/COL LowerByte,High-Z
UpperByte,Do u t
Write:Word(EarlyWrite) L L L L X ROW/COL Di n
Write:LowerByte(EarlyWrite) L L H L X ROW/COL LowerByte,Di n
UpperByte,High-Z
Write:UpperByte(EarlyWrite) L H L L X ROW/COL LowerByte,High-Z
UpperByte,Di n
Read-Write(1,2) L L L H→L L→H ROW/COL Do u t ,Di n
HiddenRefresh Read(2) L→H→L L L H L ROW/COL Do u t
Write(1,3) L→H→L L L L X ROW/COL Do u t
RAS-OnlyRefresh L H H X X ROW/NA High-Z
CBRRefresh(4) H→L L L X X X High-Z
Notes:
1. TheseWRITEcyclesmayalsobeBYTEWRITEcycles(eitherLCASorUCASactive).
2. TheseREADcyclesmayalsobeBYTEREADcycles(eitherLCASorUCASactive).
3. EARLYWRITEonly.
4. AtleastoneofthetwoCASsignalsmustbeactive(LCASorUCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774 5
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
Functional Description
TheIS41C16105CandIS41LV16105CisaCMOSDRAM
optimizedforhigh-speedbandwidth,lowpowerapplica-
tions.DuringREADorWRITEcycles,eachbitisuniquely
addressedthroughthe16addressbits.Theseareentered
tenbits(A0-A9)atatime.Therowaddressislatched
bytheRowAddressStrobe(RAS).Thecolumnaddress
islatchedbytheColumnAddressStrobe(CAS).RASis
usedtolatchtherstninebitsandCASisusedthelatter
ninebits.
The IS41C16105C and IS41LV16105C has two CAS
controls,LCASandUCAS.TheLCASandUCASinputs
internallygeneratesaCASsignalfunctioninginanidenti-
calmannertothesingleCASinputontheother1Mx16
DRAMs.ThekeydifferenceisthateachCAScontrolsits
correspondingI/O tristatelogic(inconjunctionwith OE
andWEandRAS).LCAScontrolsI/O0throughI/O7and
UCAScontrolsI/O8throughI/O15.
TheIS41C16105CandIS41LV16105CCASfunctionis
determinedbytherstCAS ( LCASorUCAS)transitioning
LOWandthelasttransitioningbackHIGH.ThetwoCAS
controlsgivetheIS41C16105CandIS41LV16105Cboth
BYTEREADandBYTEWRITEcyclecapabilities.
Memory Cycle
AmemorycycleisinitiatedbybringRASLOWanditis
terminated by returning both RAS and CAS HIGH. To
ensuresproperdeviceoperationanddataintegrityany
memorycycle,onceinitiated,mustnotbeendedoraborted
beforetheminimumtr a s timehasexpired.Anewcycle
mustnotbeinitiateduntil theminimumprechargetime
tr p ,tc p haselapsed.
Read Cycle
AreadcycleisinitiatedbythefallingedgeofCASorOE,
whicheveroccurslast,whileholdingWEHIGH.Thecolumn
addressmustbeheldforaminimumtimespeciedbyta r .
DataOutbecomesvalidonlywhentr a c ,ta a ,tc a c andto e a
areallsatised.Asaresult,theaccesstimeisdependent
onthetimingrelationshipsbetweentheseparameters.
Write Cycle
AwritecycleisinitiatedbythefallingedgeofCASand
WE,whicheveroccurslast.Theinputdatamustbevalid
atorbeforethe falling edge ofCASorWE, whichever
occurslast.
Refresh Cycle
Toretaindata,1,024refreshcyclesarerequiredineach
16msperiod.Therearetwowaystorefreshthemem-
ory.
1.Byclockingeachofthe1,024rowaddresses(A0through
A9) with RAS at least once every 16 ms.Any read,
write, read-modify-write or RAS-only cycle refreshes
theaddressedrow.
2.UsingaCAS-before-RASrefreshcycle.CAS-before-
RASrefreshisactivatedbythefallingedgeofRAS,while
holdingCASLOW.InCAS-before-RASrefreshcycle,
aninternal9-bitcounterprovidestherowaddresses
andtheexternaladdressinputsareignored.
CAS-before-RAS is a refresh-only mode and no data
accessordeviceselectionis allowed.Thus, theoutput
remainsintheHigh-Zstateduringthecycle.
Power-On
After application of the Vd d supply, an initial pause of
200µsisrequiredfollowedbyaminimumofeightinitial-
ization cycles (any combination of cycles containing a
RASsignal).
Duringpower-on,itisrecommendedthatRAStrackwith
Vd d orbeheldatavalidVi h toavoidcurrentsurges.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vt VoltageonAnyPinRelativetoGND 5V –1.0to+7.0 V
3.3V –0.5to+4.6
Vd d SupplyVoltage 5V –1.0to+7.0 V
3.3V –0.5to+4.6
Io u t OutputCurrent 50 mA
Pd PowerDissipation 1 W
Ta CommercialTemperature 0to+70 °C
IndustrialTemperature –40to+85 °C
Ts t g StorageTemperature –55to+125 °C
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothe
device.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabove
thoseindicatedintheoperationalsectionsofthisspecicationisnotimplied.Exposuretoabsolutemaximum
ratingconditionsforextendedperiodsmayaffectreliability.
RECOMMENDED OPERATING CONDITIONS (VoltagesarereferencedtoGND.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vd d SupplyVoltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
Vi h InputHighVoltage 5V 2.0 — Vd d +1.0 V
3.3V 2.0 — Vd d +0.3
Vi l InputLowVoltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
Ta CommercialTemperature 0 — 70 °C
IndustrialTemperature –40 — 85 °C
ii l InputLeakageCurrent Anyinput0V≤ Vi n ≤ Vd d –5 5 µA
Otherinputsnotundertest=0V
ii o OutputLeakageCurrent Outputisdisabled(Hi-Z) –5 5 µA
0V ≤ Vo u t ≤ Vd d
Vo h OutputHighVoltageLevel io h =–5.0mA 5V 2.4 — V
io h =–2.0mA 3.3V
Vo l OutputLowVoltageLevel io l =4.2mA 5V — 0.4 V
io l =2.0mA 3.3V
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
Ci n 1 InputCapacitance:A0-A9 5 pF
Ci n 2 InputCapacitance:RAS, UCAS, LCAS, WE, OE 7 pF
Ci o DataInput/OutputCapacitance:I/O0-I/O15 7 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2.Testconditions:Ta=25°C,f=1MHz,
Integrated Silicon Solution, Inc. — 1-800-379-47747
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
ELECTRICAL CHARACTERISTICS(1)
(RecommendedOperatingConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition VD D /Speed Min. Max. Unit
id d 1 StandbyCurrent:TTL RAS, LCAS, UCAS ≥ Vi h
Com. 5V — 3 m A
3.3V — 3
Ind. 5V — 4
3.3V — 4
id d 2 StandbyCurrent:CMOS
RAS, LCAS, UCAS ≥
Vd d
–0.2V
5V — 2 m A
3.3V — 2
id d 3 OperatingCurrent: RAS, LCAS, UCAS, -50 — 160 m A
RandomRead/Write(2,3,4) AddressCycling,tr c =tr c (min.) -60 — 145
AveragePowerSupplyCurrent
id d 4 OperatingCurrent: RAS=Vi l , LCAS, UCAS, -50 — 90 m A
FastPageMode(2,3,4) Cyclingtp c =tp c (min.) -60 — 80
AveragePowerSupplyCurrent
id d 5 RefreshCurrent: RASCycling,LCAS, UCAS ≥ Vi h -50 — 160 m A
RAS-Only(2,3)tr c =tr c (min.) -60 — 145
AveragePowerSupplyCurrent
id d 6 RefreshCurrent: RAS, LCAS, UCASCycling -50 — 160 m A
CBR(2,3,5)tr c =tr c (min.) -60 — 145
AveragePowerSupplyCurrent
Notes:
1. Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRASrefreshcycles(RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAScycleswake-upshouldberepeatedanytimethetr e f refreshrequirementisexceeded.
2. Dependentoncyclerates.
3. Speciedvaluesareobtainedwithminimumcycletimeandtheoutputopen.
4. Column-addressischangedonceeachFastpagecycle.
5. Enableson-chiprefreshandaddresscounters.
8 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tr c RandomREADorWRITECycleTime 84 — 104 — ns
tr a c AccessTimefromRAS(6,7) — 50 — 60 ns
tc a c AccessTimefromCAS(6,8,15) — 13 — 15 ns
ta a AccessTimefromColumn-Address(6) — 25 — 30 ns
tr a s RASPulseWidth 50 10K 60 10K ns
tr p RASPrechargeTime 30 — 40 — ns
tc a s CASPulseWidth(26) 8 10K 10 10K ns
tc p CASPrechargeTime(9,25) 9 — 9 — ns
tc s h CASHoldTime(21) 38 — 40 — ns
tr c d RAStoCASDelayTime(10,20) 12 37 14 45 ns
ta s r Row-AddressSetupTime 0 — 0 — ns
tr a h Row-AddressHoldTime 8 — 10 — ns
ta s c Column-AddressSetupTime(20) 0 — 0 — ns
tc a h Column-AddressHoldTime(20) 8 — 10 — ns
ta r Column-AddressHoldTime 30 — 40 — ns
(referencedtoRAS)
tr a d RAStoColumn-AddressDelayTime(11) 10 25 12 30 ns
tr a l Column-AddresstoRASLeadTime 25 — 30 — ns
tr p c RAStoCASPrechargeTime 5 — 5 — ns
tr s h RASHoldTime(27) 8 — 10 — ns
tr h c p RASHoldTimefromCASPrecharge 37 — 37 — ns
tc l z CAStoOutputinLow-Z(15,29) 0 — 0 — ns
tc r p CAStoRASPrechargeTime(21) 5 — 5 — ns
to d OutputDisableTime(19,28,29) 3 15 3 15 ns
to e OutputEnableTime(15,16) — 13 — 15 ns
to e d OutputEnableDataDelay(Write) 20 — 20 — ns
to e h c OEHIGHHoldTimefromCASHIGH 5 — 5 — ns
to e p OEHIGHPulseWidth 10 — 10 — ns
to e s OELOWtoCASHIGHSetupTime 5 — 5 — ns
tr c s ReadCommandSetupTime(17,20) 0 — 0 — ns
tr r h ReadCommandHoldTime 0 — 0 — ns
(referencedtoRAS)(12)
tr c h ReadCommandHoldTime 0 — 0 — ns
(referencedtoCAS)(12,17,21)
tw c h WriteCommandHoldTime(17,27) 8 — 10 — ns
Integrated Silicon Solution, Inc. — 1-800-379-4774 9
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tw c r WriteCommandHoldTime 40 — 50 — ns
(referencedtoRAS)(17)
tw p WriteCommandPulseWidth(17) 8 — 10 — ns
tw p z WEPulseWidthstoDisableOutputs 10 — 10 — ns
tr w l WriteCommandtoRASLeadTime(17) 13 — 15 — ns
tc w l WriteCommandtoCASLeadTime(17,21) 8 — 10 — ns
tw c s WriteCommandSetupTime(14,17,20) 0 — 0 — ns
td h r Data-inHoldTime(referencedtoRAS) 39 — 39 — ns
ta c h Column-AddressSetupTimetoCAS 15 — 15 — ns
PrechargeduringWRITECycle
to e h OEHoldTimefromWEduring 8 — 10 — ns
READ-MODIFY-WRITEcycle(18)
td s Data-InSetupTime(15,22) 0 — 0 — ns
td h Data-InHoldTime(15,22) 8 — 10 — ns
tr w c READ-MODIFY-WRITECycleTime 108 — 133 — ns
tr w d RAStoWEDelayTimeduring 64 — 77 — ns
READ-MODIFY-WRITECycle(14)
tc w d CAStoWEDelayTime(14,20) 26 — 32 — ns
ta w d Column-AddresstoWEDelayTime(14) 39 — 47 — ns
tp c FastPageModeREADorWRITE 20 — 25 — ns
CycleTime(24)
tr a s p RASPulseWidth 50 100K 60 100K ns
tc p a AccessTimefromCASPrecharge(15) — 30 — 35 ns
tp r w c READ-WRITECycleTime(24) 56 — 68 — ns
tc o h DataOutputHoldafterCASLOW 5 — 5 — ns
to f f OutputBufferTurn-OffDelayfrom 1.6 12 1.6 15 ns
CASorRAS(13,15,19,29)
tw h z OutputDisableDelayfromWE 3 10 3 10 ns
tc l c h LastCASgoingLOWtoFirstCAS 10 — 10 — ns
returningHIGH(23)
tc s r CASSetupTime(CBRREFRESH)(30,20) 5 — 5 — ns
tc h r CASHoldTime(CBRREFRESH)(30,21) 8 — 10 — ns
to r d OESetupTimepriortoRASduring 0 — 0 — ns
HIDDENREFRESHCycle
tr e f AutoRefreshPeriod(1,024Cycles) — 16 — 16 ms
tt TransitionTime(RiseorFall)(2,3) 1 50 1 50 ns
10 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
Notes:
1.Aninitialpauseof200µsisrequiredafterpower-upfollowedbyeightRASrefreshcycle(RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAScycleswake-upshouldberepeatedanytimethetr e f refreshrequirementisexceeded.
2. Vi h (MIN)andVi l (MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVi h
andVi l (orbetweenVi l andVi h )andassumetobe1nsforallinputs.
3.Inadditiontomeetingthetransitionratespecication,allinputsignalsmusttransitbetweenVi h andVi l (orbetweenVi l andVi h )
inamonotonicmanner.
4.IfCASandRAS=Vi h ,dataoutputisHigh-Z.
5.IfCAS=Vi l ,dataoutputmaycontaindatafromthelastvalidREADcycle.
6.MeasuredwithaloadequivalenttooneTTLgateand50pF.
7.Assumesthattr c d tr c d (MAX).Iftr c d isgreaterthanthemaximumrecommendedvalueshowninthistable,tr a c willincreaseby
theamountthattr c d exceedsthevalueshown.
8.Assumesthattr c d žtr c d (MAX).
9.IfCASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclear
thedataoutputbuffer,CASandRASmustbepulsedfortc p .
10.Operationwiththetr c d (MAX)limitensuresthattr a c (MAX)canbemet.tr c d (MAX)isspeciedasareferencepointonly;iftr c d
isgreaterthanthespeciedtr c d (MAX)limit,accesstimeiscontrolledexclusivelybytc a c .
11.Operationwithinthetr a d (MAX)limitensuresthattr c d (MAX)canbemet.tr a d (MAX)isspeciedasareferencepointonly;iftr a d
isgreaterthanthespeciedtr a d (MAX)limit,accesstimeiscontrolledexclusivelybyta a .
12.Eithertr c h ortr r h mustbesatisedforaREADcycle.
13.to f f (MAX)denesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVo h orVo l .
14.tw c s ,tr w d ,ta w d andtc w d arerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftw c s ž
tw c s (MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftr w d ž
tr w d (MIN),ta w d žta w d (MIN)andtc w d žtc w d (MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread
fromtheselectedcell.Ifneitheroftheaboveconditionsismet,thestateofI/O(ataccesstimeanduntilCASandRASorOEgo
backtoVi h )isindeterminate.OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)
cycle.
15.Outputparameter(I/O)isreferencedtocorrespondingCASinput,I/O0-I/O7byLCASandI/O8-I/O15byUCAS.
16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a
LATEWRITEorREAD-MODIFY-WRITEisnotpossible.
17.WritecommandisdenedasWEgoinglow.
18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothto d andto e h met(OEHIGHduringWRITEcycle)inorderto
ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCASremains
LOWandOEistakenbacktoLOWafterto e h ismet.
19.TheI/OsareinopenduringREADcyclesonceto d orto f f occur.
20.TherstχCASedgetotransitionLOW.
21.ThelastχCASedgetotransitionHIGH.
22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-
MODIFY-WRITEcycles.
23.LastfallingχCASedgetorstrisingχCASedge.
24.LastrisingχCASedgetonextcycle’slastrisingχCASedge.
25.LastrisingχCASedgetorstfallingχCASedge.
26.EachχCASmustmeetminimumpulsewidth.
27.LastχCAStogoLOW.
28.I/Oscontrolled,regardlessUCASandLCAS.
29.The3nsminimumisaparameterguaranteedbydesign.
30.Enableson-chiprefreshandaddresscounters.
AC TEST CONDITIONS
Outputload:TwoTTLLoadsand50pF(Vd d =5.0V±10%)
OneTTLLoadand50pF(Vd d =3.3V±10%)
Inputtimingreferencelevels: Vi h =2.4V,Vi l =0.8V(Vd d =5.0V±10%);
Vi h =2.0V,Vi l =0.8V(Vd d =3.3V±10%)
Outputtimingreferencelevels: Vo h =2.4V,Vo l =0.4V(Vd d =5V±10%,3.3V±10%)
Integrated Silicon Solution, Inc. — 1-800-379-4774 11
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
FAST-PAGE-MODE READ CYCLE
Note:
1. to f f isreferencedfromrisingedgeofRASorCAS,whicheveroccurslast.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
Open Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF
(1)
t
RAC
t
CLC
t
OES
t
OE
t
OD
Don’tCare
12 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
OUT
t
AR
t
RWD
t
AWD
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Column Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OEA
t
CLZ
t
CAC
t
OEA
t
CAC
t
OEA
OUT
OUT ININ IN
t
OEZ
t
OEZ
t
OED
t
OED
t
DS
t
OEZ
t
OED
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CPWD
t
CPWD
t
CAH
t
CRP
t
DS
Don’tCare
Integrated Silicon Solution, Inc. — 1-800-379-4774 13
Rev. 00A
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IS41C16105C
IS41LV16105C
FAST-PAGE-MODE EARLY WRITE CYCLE (OE=DON'TCARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don’tCare
14 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
FAST-PAGE-MODE READ WRITE CYCLE (LATEWRITEandREAD-MODIFY-WRITECycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid DOUT Valid DIN
Don’tCare
Integrated Silicon Solution, Inc. — 1-800-379-4774 15
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
FAST PAGE MODE EARLY WRITE CYCLE
t
AR
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Column Column
t
AR
t
CWL
t
WCR
t
DHR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
RHCP
t
PC
t
RCD
t
CRP
t
ASR
t
WCS
t
DS
t
RAD
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
WCH
t
DH
t
DS
t
DS
t
DH
t
DH
t
CP
t
CP
t
RP
t
CAH
t
RAH
t
CAH
t
CRP
t
CWL
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
CWL
t
WCH
t
WP
Valid DIN Valid DIN
Valid DIN
Don’tCare
16 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
AC WAVEFORMS
READ CYCLE (WithWE-ControlledDisable)
RAS-ONLY REFRESH CYCLE (OE, WE=DON'TCARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
UCAS/LCAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don’tCare
Don’tCare
Integrated Silicon Solution, Inc. — 1-800-379-4774 17
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
HIDDEN REFRESH CYCLE(1) (WE=HIGH;OE=LOW)
CBR REFRESH CYCLE (Addresses;WE, OE=DON'TCARE)
Notes:
1. AHiddenRefreshmayalsobeperformedafteraWriteCycle.Inthiscase,WE=LOWandOE=HIGH.
2. to f f isreferencedfromrisingedgeofRASorCAS,whicheveroccurslast.
tRAS tRAStRP tRP
I/O
UCAS/LCAS
RAS
Open
tCP
tRPC
tCSR
tCHR tRPC
tCSR
tCHR
t
RAS
t
RAS
t
RP
UCAS/LCAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’tCare
18 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
ORDERING INFORMATION : 5V
Industrial Range: -40oC to 85oC
Speed (ns) Order Part No. Package
50 IS41C16105C-50KI 400-milSOJ
IS41C16105C-50KLI 400-milSOJ,Lead-free
IS41C16105C-50TI 400-milTSOP(TypeII)
IS41C16105C-50TLI 400-milTSOP(TypeII),Lead-free
ORDERING INFORMATION : 3.3V
Industrial Range: -40oC to 85oC
Speed (ns) Order Part No. Package
50 IS41LV16105C-50KI 400-milSOJ
IS41LV16105C-50KLI 400-milSOJ,Lead-free
IS41LV16105C-50TI 400-milTSOP(TypeII)
IS41LV16105C-50TLI 400-milTSOP(TypeII),Lead-free
Note:
The -50 speed option supports 50ns and 60ns timing specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774 19
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C
20 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
IS41C16105C
IS41LV16105C