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MB90340E Series
F2MC-16LX 16-bit Microcontroller
Datasheet
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-04498 Rev. *A Revised May 4, 2016
The MB90340E series with up to 2 FULL-CAN interfaces is especially designed for automotive and other industrial applications. Its
main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message
buffer scheme and so offering more functions than a normal full CAN approach.
The power to the MCU core (3 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior performance in
terms of power consumption and tolerance to EMI.
Features
CPU
Instruction system best suited to controller
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide
instructions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level language (C
language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
Increased processing speed
- 4-byte instruction queue
Serial interface
LIN-UART : 4 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial transmission
is available
I2C interface : 2 channels (only for devices with a C suffix in
the part number)
- Up to 400 kbps transfer rate
Interrupt controller
Powerful 8-level, 34-condition interrupt feature
Up to 16 external interrupts are supported
Automatic data transfer function independent of CPU
- Expanded intelligent I/O service function (EI2OS) : up to 16
channels
I/O ports
General-purpose input/output port (CMOS output)
- 80 ports (for devices without an S suffix in the part number -
i.e. devices that support the sub clock)
- 82 ports (for devices with an S suffix in the part number - i.e.
devices that do not support the sub clock)
8/10-bit A/D converter
16 channels (only for devices without a C suffix in the part
number)
24 channels (only for devices with a C suffix in the part
number)
Resolution is selectable between 8-bit and 10-bit.
Activation by external trigger input is allowed.
Conversion time : 3 s (at 24 MHz machine clock, including
sampling time)
Address match detection (program patch) func-
tion
Detects address matches against 6 address pointers
Timer
Time-base timer, watch timer, watchdog timer : 1 channel
8/16-bit PPG timer : 8-bit 16 channels, or 16-bit 8
channels
16-bit reload timer : 4 channels
16-bit input/output timer
- 16-bit free-run timer : 2 channels
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/
5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
Full-CAN controller
Up to 2 channels
Compliant with Ver2.0A and Ver2.0B CAN specifications
16 built-in message buffers
CAN wake-up function
Low power consumption (standby) mode
Sleep mode (a mode that halts CPU operating clock)
Timebase timer mode (a mode where only the oscillation
clock, sub clock, timebase timer and watch timer operate)
Watch mode (a mode that operates sub clock and watch
timer only)
Stop mode (a mode that stops oscillation clock and sub
clock)
CPU intermittent operation mode
Clock modulation circuit
Technology
CMOS technology
Document Number: 002-04498 Rev. *A Page 2 of 92
MB90340E Series
Contents
Product Lineup ................................................................3
Pin Assignments .............................................................. 6
Pin Description ...............................................................12
I/O Circuit Type ...............................................................19
Handling Devices ............................................................23
Block Diagrams ..............................................................26
Memory Map ....................................................................28
I/O Map ............................................................................30
CAN Controllers ..............................................................41
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 48
Electrical Characteristics ...............................................50
Absolute Maximum Ratings ....................................... 50
Recommended Operating Conditions ....................... 52
DC Characteristics ....................................................53
AC Characteristics .....................................................55
Clock Timing ..............................................................55
Reset Standby Input .................................................. 58
Power On Reset ........................................................59
Clock Output Timing .................................................. 59
Bus Timing (Read) .................................................... 60
Bus Timing (Write) ..................................................... 61
Ready Input Timing ................................................... 62
Hold Timing ............................................................... 63
LIN-UART0/1/2/3 ....................................................... 64
Trigger Input Timing .................................................. 69
Timer Related Resource Input Timing ....................... 70
Timer Related Resource Output Timing .................... 70
I2C Timing ................................................................. 71
A/D Converter ............................................................ 72
Definition of A/D Converter Terms ........................... 73
Notes on A/D Converter Section ............................... 74
Flash Memory Program/Erase Characteristics ......... 76
Example Characteristics ................................................ 77
Ordering Information ...................................................... 86
Package Dimensions ...................................................... 89
Major Changes ................................................................ 91
Document Number: 002-04498 Rev. *A Page 3 of 92
MB90340E Series
1. Product Lineup
(Continued)
Part Number
Parameter
MB90V340E-101,
MB90V340E-102
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
Type Evaluation products Flash memory products MASK ROM products
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL 6)
ROM External
512 Kbytes :
MB90F345E(S), MB90F345CE(S)
256 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90F349E(S), MB90F349CE(S)
128 Kbytes :
MB90F347E(S), MB90F347CE(S)
64 Kbytes :
MB90F346E(S), MB90F346CE(S)
256 Kbytes :
MB90342E(S), MB90342CE(S),
MB90349E(S), MB90349CE(S)
128 Kbytes :
MB90341E(S), MB90341CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S)
64 Kbytes :
MB90346E(S), MB90346CE(S)
RAM 30 Kbytes
20 Kbytes :
MB90F345E(S), MB90F345CE(S)
16 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90F349E(S), MB90F349CE(S)
6 Kbytes :
MB90F347E(S), MB90F347CE(S)
2 Kbytes :
MB90F346E(S), MB90F346CE(S)
16 Kbytes :
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
6 Kbytes :
MB90347E(S), MB90347CE(S)
2 Kbytes :
MB90346E(S), MB90346CE(S)
Emulator-specific power
supply* Yes
Technology
0.35 m CMOS with
regulator for built-in
power supply
0.35 m CMOS with built-in power supply regulator
Flash memory with Charge pump for programming voltage
Operating
voltage range 5 V 103.5 V to 5.5 V : When normal operating (not using A/D converter)
4.0 V to 5.5 V : When using the A/D converter/Flash programming
4.5 V to 5.5 V : When using the external bus
Temperature range 40°C to 105°C
Package PGA-299 QFP-100, LQFP-100
LIN-UART
5 channels 4 channels
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps) 2 channels Devices with a C suffix in the part number : 2 channels
Devices without a C suffix in the part number :
Document Number: 002-04498 Rev. *A Page 4 of 92
MB90340E Series
Part Number
Parameter
MB90V340E-101,
MB90V340E-102
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
A/D Converter
24 input channels Devices with a C suffix in the part number : 24 channels
Devices without a C suffix in the part number : 16 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function
16-bit Free-run
Timer (2 channels)
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock freq.)
Free-run Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
Free-run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(8 channels)
Generates an interrupt signal when one of the 16-bit free-run timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture
(8 channels)
Captures the value of the 16-bit free-run timer and generates an interrupt when triggered by a pin input (rising
edge, falling edge, or both rising and falling edges).
8/16-bit
Programmable Pulse
Generator
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN Interface
3 channels
2 channels :
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S)
1 channel :
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
2 channels :
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S)
1 channel :
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Document Number: 002-04498 Rev. *A Page 5 of 92
MB90340E Series
(Continued)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01-E) is used.
Please refer to the Emulator operation manual for details.
Part Number
Parameter
MB90V340E-101,
MB90V340E-102
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A Converter 2 channels
Sub clock
(maximum 100 kHz)
Only for
MB90V340E-102
Devices with sub clock : devices without an S suffix in the part number
Devices without sub clock : devices with an S suffix in the part number
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 cycles
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (except for
MB90F346E(S) and MB90F346CE (S) )
Document Number: 002-04498 Rev. *A Page 6 of 92
MB90340E Series
2. Pin Assignments
MB90341E(S), MB90342E(S), MB90F342E(S), MB90F345E(S), MB90346E(S), MB90F346E(S),
MB90347E(S), MB90F347E(S), MB90348E(S), MB90349E(S), MB90F349E(S)
(Continued)
(TOP VIEW)
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/INT7
P76/INT6
MD0
MD1
MD2
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P32/WRLX/WRX/INT10R
P34/HRQ/OUT4
P56/AN14
P55/AN13
P54/AN12/TOT3
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47
P46
P45/FRCK1
P44/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A *
P40/X0A *
P37/CLK/OUT7
P36/RDY/OUT6
QFP - 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
Document Number: 002-04498 Rev. *A Page 7 of 92
MB90340E Series
(Continued)
(TOP VIEW)
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P4 : devices with an S suffix in the part number
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/INT7
P76/INT6
MD0
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P32/WRL/WR/INT10R
P34/HRQ/OUT4
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47
P46
P45/FRCK1
P44/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
99
P24/A20/IN0
100
P25/A21/IN1
28 P56/AN14
27 P55/AN13
26 P54/AN12/TOT3
49 MD2
50 MD1
78
P03/AD03/INT11
77
P02/AD02/INT10
76
P01/AD01/INT9
LQFP - 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
12345678910111213141516171819202122232425
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
Document Number: 002-04498 Rev. *A Page 8 of 92
MB90340E Series
MB90341CE(S), MB90342CE(S), MB90F342CE(S), MB90F345CE(S), MB90346CE(S), MB90F346CE(S), MB90347CE(S),
MB90F347CE(S), MB90348CE(S), MB90349CE(S), MB90F349CE(S)
(Continued)
(TOP VIEW)
(FPT-100P-M06)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P75/AN21/INT5
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
MD1
MD2
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P56/AN14
P55/AN13
P54/AN12/TOT3
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
QFP - 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
123456789101112131415161718192021222324252627282930
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P61/AN1/PPG2(3)
AVss
P57/AN15
AVcc
P60/AN0/PPG0(1)
AVRL
AVRH
Vss
P62/AN2/PPG4(5)
P63/AN3/PPG6(7)
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
P32/WRL/WR/INT10R
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A Page 9 of 92
MB90340E Series
(Continued)
(TOP VIEW)
(FPT-100P-M20)
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
99P24/A20/IN0
100P25/A21/IN1
28 P56/AN14
27 P55/AN13
26 P54/AN12/TOT3
49 MD2
50 MD1
78P03/AD03/INT11
77P02/AD02/INT10
76P01/AD01/INT9
LQFP - 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
RST
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
P32/WRL/WR/INT10R
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A Page 10 of 92
MB90340E Series
MB90V340E-101/MB90V340E-102
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
(Continued)
(TOP VIEW)
(FPT-100P-M06)
*: X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15/SCK4
P16/AD14/SOT4
P15/AD13/SIN4
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
3018
P75/AN21/INT5
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
RST
MD0
MD1
MD2
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P34/HRQ/OUT4
P35/HAK/OUT5
P56/AN14/DA00
P55/AN13
P54/AN12/TOT3
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
QFP - 100
21201716 19181514131211 2625242322 27 28 29435629710
80 515871 70 67 6669 68 65 64 63 62 6176 75 74 73 72777879 54 535556 5259 5760
P57/AN15/DA01
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P60/AN0/PPG0(1)
P61/AN1/PPG2(3)
P62/AN2/PPG4(5)
P63/AN3/PPG6(7)
P64/AN4/PPG8(9)
P65/AN5/PPGA(B)
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
Vss
P70/AN16/INT0
P71/AN17/INT1
AVcc
AVRH
AVRL
AVss
Document Number: 002-04498 Rev. *A Page 11 of 92
MB90340E Series
(Continued)
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
(TOP VIEW)
(FPT-100P-M20)
*: X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
75
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P04/AD04/INT12
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P20/A16/PPG9(8)
P17/AD15/SCK4
P16/AD14/SOT4
P15/AD13/SIN4
X1
Vss
Vcc
P14/AD12/SCK3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P11/AD09/TOT1
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
X0
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA01
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
MD0
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P53/AN11/TIN3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P47/SCL1
P46/SDA1
P45/SCL0/FRCK1
P44/SDA0/FRCK0
P43/IN7/TX1
P42/IN6/RX1/INT9R
C
Vss
Vcc
P41/X1A*
P40/X0A*
P37/CLK/OUT7
P36/RDY/OUT6
LQFP - 100
99P24/A20/IN0
100P25/A21/IN1
28 P56/AN14/DA00
27 P55/AN13
26 P54/AN12/TOT3
49 MD2
50 MD1
78P03/AD03/INT11
77P02/AD02/INT10
76P01/AD01/INT9
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 5859 555657 54 53 52 51
1 2 3 4 5 6 7 8 9 10111213141516 1817 212019 22 23 24 25
RST
P31/RD/IN5
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P35/HAK/OUT5
Document Number: 002-04498 Rev. *A Page 12 of 92
MB90340E Series
3. Pin Description
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
1 to 4 99 to 2
P24 to P27
G
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O
port when the corresponding bit in the external address output control register
(HACR) is 1.
A20 to A23
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A20 to A23).
IN0 to IN3 Trigger input pins for input captures.
53
P30
G
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
ALE Address latch enable output pin. This function is enabled when the external bus
is enabled.
IN4 Trigger input pin for input capture.
64
P31
G
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
RD External read strobe output pin. This function is enabled when the external bus is
enabled.
IN5 Trigger input pin for input capture.
75
P32
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
WR/WRL pin output is disabled.
WR / WRL
Write strobe output pin for the external data bus. This function is enabled when
both the external bus and the WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
INT10R External interrupt request input pin.
86
P33
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.This function is enabled either in single-chip mode or when the
WRH pin output is disabled.
WRH
Write strobe output pin for the upper 8 bits of the external data bus. This function
is enabled when the external bus is enabled, when the external bus 16-bit mode
is selected, and when the WRH output pin is enabled.
Document Number: 002-04498 Rev. *A Page 13 of 92
MB90340E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
97
P34
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
HRQ Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
OUT4 Waveform output pin for output compare.
10 8
P35
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
HAK Hold acknowledge output pin. This function is enabled when both the external
bus and the hold function are enabled.
OUT5 Waveform output pin for output compare.
11 9
P36
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
external ready function is disabled.
RDY External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
OUT6 Waveform output pin for output compare.
12 10
P37
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
clock output is disabled.
CLK Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
OUT7 Waveform output pin for output compare
13, 14 11, 12
P40, P41 F General purpose I/O pins.
(devices with an S suffix in the part number and or MB90V340E-101)
X0A, X1A B Oscillation pins for sub clock
(devices without an S suffix in the part number and or MB90V340E-102)
15 13 VCC Power (3.5 V to 5.5 V) input pin
16 14 VSS GND pin
17 15 C K This is the power supply stabilization capacitor This pin should be connected
to a ceramic capacitor with a capacitance greater than or equal to 0.1 F.
18 16
P42
F
General purpose I/O pin.
IN6 Trigger input pin for input capture.
RX1 RX input pin for CAN1 Interface
(MB90341E/342E/F342E/F345E only)
INT9R External interrupt request input pin
Document Number: 002-04498 Rev. *A Page 14 of 92
MB90340E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
19 17
P43
F
General purpose I/O pin.
IN7 Trigger input pin for input capture.
TX1 TX Output pin for CAN1
(MB90341E/342E/F342E/F345E only)
20 18
P44
H
General purpose I/O pin.
SDA0 Serial data I/O pin for I2C (devices with a C suffix in the part number)
FRCK0 Input pin for the 16-bit Free-run Timer 0
21 19
P45
H
General purpose I/O pin.
SCL0 Serial clock I/O pin for I2C (devices with a C suffix in the part number)
FRCK1 Input pin for the 16-bit Free-run Timer
22 20 P46 HGeneral purpose I/O pin.
SDA1 Serial data I/O pin for I2C (devices with a C suffix in the part number)
23 21 P47 HGeneral purpose I/O pin.
SCL1 Serial clock I/O pin for I2C (devices with a C suffix in the part number)
24 22
P50
O
General purpose I/O pin.
AN8 Analog input pin for the A/D converter
SIN2 Serial data input pin for UART2
25 23
P51
I
General purpose I/O pin.
AN9 Analog input pin for the A/D converter
SOT2 Serial data output pin for UART2
26 24
P52
I
General purpose I/O pin.
AN10 Analog input pin for the A/D converter
SCK2 Clock I/O pin for UART2
27 25
P53
I
General purpose I/O pin.
AN11 Analog input pin for the A/D converter
TIN3 Event input pin for the reload timer
28 26
P54
I
General purpose I/O pin.
AN12 Analog input pin for the A/D converter
TOT3 Output pin for the reload timer
29 27 P55 IGeneral purpose I/O pin.
AN13 Analog input pin for the A/D converter
30, 31 28, 29 P56, P57 JGeneral purpose I/O pins.
AN14, AN15 Analog input pins for the A/D converter
32 30 AVCC K Analog power input pin for the A/D Converter
Document Number: 002-04498 Rev. *A Page 15 of 92
MB90340E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
33 31 AVRH L
Reference voltage input pin for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or equal to AVRH
is applied to AVCC.
34 32 AVRL K Lower reference voltage input pin for the A/D Converter
35 33 AVSS K Analog GND pin for the A/D Converter
36 to 43 34 to 41
P60 to P67
I
General purpose I/O pins.
AN0 to AN7 Analog input pins for the A/D converter
PPG0, 2, 4, 6, 8,
A, C, E Output pins for PPGs
44 42 VSS GND pin
45 to 50 43 to 48
P70 to P75
I
General purpose I/O pins.
AN16 to AN21 Analog input pins for the A/D converter (devices with a C suffix in the part
number)
INT0 to INT5 External interrupt request input pins
51 49 MD2 D Input pin for specifying the operating mode.
52, 53 50, 51 MD1, MD0 C Input pins for specifying the operating mode.
54 52 RST E Reset input pin
55, 56 53, 54
P76, P77
I
General purpose I/O pins.
AN22, AN23 Analog input pins for the A/D converter (devices with a C suffix in the part
number)
INT6, INT7 External interrupt request input pins
57 55
P80
F
General purpose I/O pin.
TIN0 Event input pin for the reload timer
ADTG Trigger input pin for the A/D converter
INT12R External interrupt request input pin
58 56
P81
F
General purpose I/O pin.
TOT0 Output pin for the reload timer
CKOT Output pin for the clock monitor
INT13R External interrupt request input pin
59 57
P82
M
General purpose I/O pin.
SIN0 Serial data input pin for UART0
TIN2 Event input pin for the reload timer
INT14R External interrupt request input pin
60 58
P83
F
General purpose I/O pin.
SOT0 Serial data output pin for UART0
TOT2 Output pin for the reload timer
Document Number: 002-04498 Rev. *A Page 16 of 92
MB90340E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
61 59
P84
F
General purpose I/O pin.
SCK0 Clock I/O pin for UART0
INT15R External interrupt request input pin
62 60 P85 MGeneral purpose I/O pin.
SIN1 Serial data input pin for UART1
63 61 P86 FGeneral purpose I/O pin.
SOT1 Serial data output pin for UART1
64 62 P87 FGeneral purpose I/O pin.
SCK1 Clock I/O pin for UART1
65 63 VCC Power (3.5 V to 5.5 V) input pin
66 64 VSS GND pin
67 to 70 65 to 68 P90 to P93 FGeneral purpose I/O pins
PPG1, 3, 5, 7 Output pins for PPGs
71 to 74 69 to 72
P94 to P97
F
General purpose I/O pins
OUT0 to OUT3 Waveform output pins for output compares. This function is enabled when
the OCU enables waveform output.
75 73
PA0
F
General purpose I/O pin.
RX0 RX input pin for CAN0 Interface
INT8R External interrupt request input pin
76 74 PA1 FGeneral purpose I/O pin.
TX0 TX Output pin for CAN0
77 to 84 75 to 82
P00 to P07
G
General purpose I/O pins. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
INT8 to INT15 External interrupt request input pins.
85 83
P10
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD08 I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
TIN1 Event input pin for the reload timer
Document Number: 002-04498 Rev. *A Page 17 of 92
MB90340E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
86 84
P11
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled in single-chip mode.
AD09 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
TOT1 Output pin for the reload timer
87 85
P12
N
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD10 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SIN3 Serial data input pin for UART3
INT11R External interrupt request input pin
88 86
P13
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD11 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SOT3 Serial data output pin for UART3
89 87
P14
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD12 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SCK3 Clock I/O pin for UART3
90 88 VCC Power (3.5 V to 5.5 V) input pin
91 89 VSS GND pin
92 90 X1 AMain clock output pin
93 91 X0 Main clock input pin
94 92
P15
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD13 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
95 93
P16
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD14 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
Document Number: 002-04498 Rev. *A Page 18 of 92
MB90340E Series
(Continued)
1 : FPT-100P-M06
2 : FPT-100P-M20
3 : For I/O circuit type, refer to “I/O Circuit Type”.
Pin No.
Pin name
I/O
Circuit
type*3Function
QFP100*1LQFP100*2
96 94
P17
G
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD15 I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
97 to 100 95 to 98
P20 to P23
G
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in the external address
output control register (HACR) is 1.
A16 to A19
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A16 to A19).
PPG9,PPGB,PP
GD,PPGF Output pins for PPGs
Document Number: 002-04498 Rev. *A Page 19 of 92
MB90340E Series
4. I/O Circuit Type
(Continued)
Type Circuit Remarks
A
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 M
B
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 M
C
MASK ROM and evaluation products:
CMOS hysteresis input pin
Flash memory products:
CMOS input pin
D
MASK ROM and evaluation products:
CMOS hysteresis input pin
Pull-down resistor value: approx. 50 k
Flash memory products:
CMOS input pin
No pull-down
E
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 k
Standby control signal
X1
X0
Xout
Standby control signal
X1A
X0A
Xout
CMOS hysteresis
inputs
R
Pull-down
Resistor
CMOS hysteresis
inputs
R
Pull-up
Resistor
CMOS hysteresis
inputs
R
Document Number: 002-04498 Rev. *A Page 20 of 92
MB90340E Series
(Continued)
Type Circuit Remarks
F
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
G
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
TTL input (with function to disconnect
input during standby)
Programmable pull-up resistor: 50 k
approx.
H
CMOS level output
(IOL = 3 mA, IOH 3 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Pull-up control
CMOS hysteresis
input
Automotive input
TTL input
Standby control for
input shutdown
Pout
Nout
R
P-ch
P-ch
N-ch
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Pout
Nout
R
N-ch
P-ch
Document Number: 002-04498 Rev. *A Page 21 of 92
MB90340E Series
Type Circuit Remarks
I
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
J
CMOS level output
(IOL = 4 mA, IOH 4 mA)
D/A analog output
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
K
Power supply input protection circuit
L
A/D converter reference voltage power supply input
pin, with the protection
circuit
Flash memory devices do not have a protection
circuit against VCC for pin AVRH
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Analog input
Pout
Nout
R
P-ch
N-ch
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Analog input
Analog output
Pout
Nout
R
P-ch
N-ch
N-ch
P-ch
ANE
AVR
ANE
N-ch
P-ch
Document Number: 002-04498 Rev. *A Page 22 of 92
MB90340E Series
(Continued)
Type Circuit Remarks
M
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
N
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
TTL input (with function to disconnect
input during standby)
Programmable pull-up resistor: 50 k
approx
O
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
CMOS input
Automotive input
Standby control for
input shutdown
Pout
Nout
R
P-ch
N-ch
Pull-up control
CMOS input
Automotive input
TTL input
Standby control for
input shutdown
Pout
Nout
R
N-ch
P-ch
P-ch
CMOS input
Automotive input
Standby control for
input shutdown
Analog input
Pout
Nout
R
N-ch
P-ch
Document Number: 002-04498 Rev. *A Page 23 of 92
MB90340E Series
5. Handling Devices
1.Preventing latch-up
CMOS IC may suffer latch-up under the following conditions:
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between VCC and VSS pins.
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage.
2.Handling unused pins
Leaving unused input terminals open may lead to permanent damage due to malfunction and latch-up; pull up or pull down the
terminals through the resistors of 2 k or more.
3.Power supply pins (VCC/VSS)
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected
inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the
standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.
As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 F as a bypass capacitor
between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
4.Mode Pins (MD0 to MD2)
Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance
connection.
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90340E
Series
Vcc Vss
Vcc
Vss
Document Number: 002-04498 Rev. *A Page 24 of 92
MB90340E Series
5. Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the
digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does
not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
6.Connection of Unused A/D Converter Pins when the A/D Converter is Used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH AVRL VSS.
7.Crystal Oscillator Circuit
The X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operation. Make sure to provide bypass capacitors via the
shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to
the utmost effort, that the oscillation circuit lines do not cross the lines of other circuits. It is highly recommended to provide a printed
circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation.
For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator you are using.
8. Pull-up/down resistors
The MB90340E Series does not support internal pull-up/down resistors (except for the pull-up resistors built into ports 0 to 3). Use
external components where needed.
9.Using external clock
To use an external clock, drive the X0 pin and leave the X1 pin open.
10.Precautions when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
11.Notes on operation in PLL clock mode
If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external
oscillator or the external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
12.Notes on Power-On
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 s or more (0.2 V to 2.7
V)
X0
X1
MB90340E Series
Open
Document Number: 002-04498 Rev. *A Page 25 of 92
MB90340E Series
13.Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range.
Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple
variations (peak- to-peak values) at commercial frequencies (50 MHz/60 MHz) fall below 10 of the standard VCC supply voltage
and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14.Port 0 to Port 3 Output During Power-on (External-bus Mode)
As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of Port 0 to Port 3 might
be unstable irrespective of the reset input.
15.Notes on Using the CAN Function
To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1.
16.Flash Security Function (except for MB90F346E)
A security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Refer to following table for the address of the security bit.
17.Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data
due to the noise.
Flash memory size Address of the security bit
MB90F347E Embedded 1 Mbit Flash Memory FE0001H
MB90F342E
MB90F349E Embedded 2 Mbits Flash Memory FC0001H
MB90F345E Embedded 4 Mbits Flash Memory F80001H
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
Port0 to Port3
VCC
1/2VCC
Document Number: 002-04498 Rev. *A Page 26 of 92
MB90340E Series
6. Block Diagrams
MB90V340E-101/102
RAM
LIN-UART
Prescaler
8/10-bit
24 channels
16-bit Reload
Free-run
Timer 0
Clock
Controller
Input
Capture
8 channels
Output
Compare
8 channels
CAN
Controller
External
Interrupt
16LX
CPU
F2MC-16 Bus
X0,X1
RST
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
TIN3 to TIN0
TOT3 to TOT0
IN7 to IN0
OUT7 to OUT0
RX2 to RX0
TX2 to TX0
INT15 to INT8
External
Bus
Interface
AD15 to AD00
A23 to A16
ALE
RD
WR/WRL
WRH
HRQ
HAK
RDY
CLK
X0A,X1A*
5 channels
10-bit
D/A converter
2 channels
DA01, DA00
FRCK0
FRCK1
8/16-bit
PPG
16/8 channels
PPGF to PPG0
I2C
Interface
SDA1, SDA0
SCL1, SCL0
3 channels
5 channels
2 channels
DMAC
* : Only for MB90V340E-102
Clock
Monitor CKOT
(INT15R to INT8R)
INT7 to INT0
A/D converter
30 Kbytes
16 channels
4 channels
Timer
Free-run
Timer 1
Document Number: 002-04498 Rev. *A Page 27 of 92
MB90340E Series
MB90341E(S), MB90341CE(S), MB90342E(S), MB90342CE(S), MB90F342E(S), MB90F342CE(S), MB90F345E(S),
MB90F345CE(S), MB90346E(S), MB90346CE(S), MB90F346E(S), MB90F346CE(S), MB90347E(S), MB90347CE(S),
MB90F347E(S), MB90F347CE(S), MB90348E(S), MB90348CE(S), MB90349E(S), MB90349CE(S), MB90F349E(S), MB90F349CE(S)
RAM
ROM/Flash
LIN-UART
Prescaler
8/10-bit
16/24
16-bit Reload
Free-run
Clock
Controller
Input
Capture
8 channels
Output
Compare
8 channels
CAN
Controller
External
Interrupt
16LX
CPU
F2MC-16 Bus
X0,X1
RST
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
AVCC
AVSS
AN15 to AN0
AVRH
AVRL
ADTG
TIN3 to TIN0
TOT3 to TOT0
IN7 to IN0
OUT7 to OUT0
RX0, RX1*3
TX0, TX1*3
INT15 to INT8
External
Bus
Interface
AD15 to AD00
A23 to A16
ALE
RD
WR/WRL
WRH
HRQ
HAK
RDY
CLK
X0A,X1A*1
64 K/128 K
4 channels
Free-run
FRCK0
FRCK1
8/16-bit
PPG
16/8 channels
PPGF to PPG0
4 channels
I2C
Interface
SDA1, SDA0*
2
SCL1, SCL0*
2
2 channels
AN23 to AN16*2
2 K/6 K/16 K/
20 Kbytes
256 K/384 K/
*1 : Only for devices with an S suffix in the part number
*2 : Only for devices with a C suffix in the part number
*3 : Only the MB90341E(S)/ 341CE(S)/ 342E(S)/ 342CE(S)/ F342E(S)/F342CE(S)/F345E(S)/ F345CE(S)
are equipped with 2 CAN channels
Clock
Monitor CKOT
(INT15R to INT8R)
INT7 to INT0
512 Kbytes
A/D Converter
16 channels
channels
Timer
4 channels
1/2 channels*3
Timer 0
Timer 1
DMAC
Document Number: 002-04498 Rev. *A Page 28 of 92
MB90340E Series
7. Memory Map
MB90V340E-101/102 MB90F345E(S)/F345CE(S)
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
FDFFFF
H
FD0000
H
FCFFFF
H
FC0000
H
FBFFFF
H
FB0000
H
FAFFFF
H
FA0000
H
F9FFFF
H
F90000
H
F8FFFF
H
F80000
H
00FFFF
H
008000
H
007FFF
H
007900
H
0078FF
H
000100
H
0000EF
H
000000
H
FFFFFF
H
FF0000
H
FEFFFF
H
FE0000
H
FDFFFF
H
FD0000
H
FCFFFF
H
FC0000
H
FBFFFF
H
FB0000
H
FAFFFF
H
FA0000
H
F9FFFF
H
F90000
H
F8FFFF
H
F80000
H
00FFFF
H
008000
H
007FFF
H
007900
H
0050FF
H
000100
H
0000EF
H
000000
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM
(image of FF bank)
Peripheral
RAM 30 Kbytes
Peripheral
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM
(image of FF bank)
Peripheral
RAM 20 Kbytes
Peripheral
External access area
External access area
External access areaExternal access area
: Not accessible
Document Number: 002-04498 Rev. *A Page 29 of 92
MB90340E Series
Note: :An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible for the C
compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the same as the lower 16 bits
of addresses in the 00 bank so that tables stored in the ROM can be accessed without using the far specifier in the pointer
declaration.
For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
As a result, the image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
MB90342E(S)/342CE(S)
MB90F342E(S)/F342CE(S)
MB90349E(S)/349CE(S)
MB90F349E(S)/F349CE(S)
MB90341E(S)/341CE(S)
MB90348E(S)/348CE(S)
MB90347E(S)/347CE(S)
MB90F347E(S)/F347CE(S)
MB90346E(S)/346CE(S)
MB90F346E(S)/F346CE(S)
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
003FFFH
000100H
008000H
FFFFFFH
FF0000H
FEFFFFH
FE0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
003FFFH
000100H
008000H
FFFFFFH
FF0000H
FEFFFFH
FE0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
0018FFH
000100H
008000H
FFFFFFH
FF0000H
FEFFFFH
FE0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
0008FFH
000100H
008000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
External
access area
ROM (image
of FF bank)
Peripheral
RAM 16 Kbytes
External access area
Peripheral
: Not accessible
External
access area
ROM (image
of FF bank)
Peripheral
RAM 16 Kbytes
External access area
Peripheral
External
access area
ROM (image
of FF bank)
Peripheral
RAM 6 Kbytes
External access area
Peripheral
External
access area
ROM (image
of FF bank)
Peripheral
RAM 2 Kbytes
External access area
Peripheral
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
Document Number: 002-04498 Rev. *A Page 30 of 92
MB90340E Series
8. I/O Map
(Continued)
Address Register Abbreviation Access Resource name Initial value
000000HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXXB
000001HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
000002HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
000003HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
000004HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
000005HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
000006HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
000007HPort 7 Data Register PDR7 R/W Port 7 XXXXXXXXB
000008HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXXB
000009HPort 9 Data Register PDR9 R/W Port 9 XXXXXXXXB
00000AHPort A Data Register PDRA R/W Port A XXXXXXXXB
00000BHPort 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111B
00000CHPort 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111B
00000DHPort 7 Analog Input Enable Register ADER7 R/W Port 7, A/D 11111111B
00000EHInput Level Select Register 0 ILSR0 R/W Ports XXXXXXXXB
00000FHInput Level Select Register 1 ILSR1 R/W Ports XXXX0XXXB
000010HPort 0 Direction Register DDR0 R/W Port 0 00000000B
000011HPort 1 Direction Register DDR1 R/W Port 1 00000000B
000012HPort 2 Direction Register DDR2 R/W Port 2 00000000B
000013HPort 3 Direction Register DDR3 R/W Port 3 00000000B
000014HPort 4 Direction Register DDR4 R/W Port 4 00000000B
000015HPort 5 Direction Register DDR5 R/W Port 5 00000000B
000016HPort 6 Direction Register DDR6 R/W Port 6 00000000B
000017HPort 7 Direction Register DDR7 R/W Port 7 00000000B
000018HPort 8 Direction Register DDR8 R/W Port 8 00000000B
000019HPort 9 Direction Register DDR9 R/W Port 9 00000000B
00001AHPort A Direction Register DDRA R/W Port A 00000100B
00001BHReserved
00001CHPort 0 Pull-up Control Register PUCR0 R/W Port 0 00000000B
00001DHPort 1 Pull-up Control Register PUCR1 R/W Port 1 00000000B
00001EHPort 2 Pull-up Control Register PUCR2 R/W Port 2 00000000B
00001FHPort 3 Pull-up Control Register PUCR3 W, R/W Port 3 00000000B
Document Number: 002-04498 Rev. *A Page 31 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
000020HSerial Mode Register 0 SMR0 W,R/W
UART0
00000000B
000021HSerial Control Register 0 SCR0 W,R/W 00000000B
000022HReception/Transmission Data Register 0 RDR0/TDR0 R/W 00000000B
000023HSerial Status Register 0 SSR0 R,R/W 00001000B
000024H
Extended Communication Control
Register 0 ECCR0 R,W,
R/W 000000XXB
000025HExtended Status/Control Register 0 ESCR0 R/W 00000100B
000026HBaud Rate Generator Register 00 BGR00 R/W 00000000B
000027HBaud Rate Generator Register 01 BGR01 R/W 00000000B
000028HSerial Mode Register 1 SMR1 W,R/W
UART1
00000000B
000029HSerial Control Register 1 SCR1 W,R/W 00000000B
00002AHReception/Transmission Data Register 1 RDR1/TDR1 R/W 00000000B
00002BHSerial Status Register 1 SSR1 R,R/W 00001000B
00002CH
Extended Communication Control
Register 1 ECCR1 R,W,
R/W 000000XXB
00002DHExtended Status/Control Register 1 ESCR1 R/W 00000100B
00002EHBaud Rate Generator Register 10 BGR10 R/W 00000000B
00002FHBaud Rate Generator Register 11 BGR11 R/W 00000000B
000030HPPG 0 Operation Mode Control Register PPGC0 W,R/W
16-bit PPG 0/1
0X000XX1B
000031HPPG 1 Operation Mode Control Register PPGC1 W,R/W 0X000001B
000032HPPG 0/PPG 1 Count Clock Select Register PPG01 R/W 000000X0B
000033HReserved
000034HPPG 2 Operation Mode Control Register PPGC2 W,R/W
16-bit PPG 2/3
0X000XX1B
000035HPPG 3 Operation Mode Control Register PPGC3 W,R/W 0X000001B
000036HPPG 2/PPG 3 Count Clock Select Register PPG23 R/W 000000X0B
000037HReserved
000038HPPG 4 Operation Mode Control Register PPGC4 W,R/W
16-bit PPG 4/5
0X000XX1B
000039HPPG 5 Operation Mode Control Register PPGC5 W,R/W 0X000001B
00003AHPPG 4/PPG 5 Clock Select Register PPG45 R/W 000000X0B
00003BHAddress Detect Control Register 1 PACSR1 R/W Address Match
Detection 1 00000000B
00003CHPPG 6 Operation Mode Control Register PPGC6 W,R/W
16-bit PPG 6/7
0X000XX1B
00003DHPPG 7 Operation Mode Control Register PPGC7 W,R/W 0X000001B
00003EHPPG 6/PPG 7 Count Clock Control Register PPG67 R/W 000000X0B
00003FHReserved
Document Number: 002-04498 Rev. *A Page 32 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
000040HPPG 8 Operation Mode Control Register PPGC8 W,R/W
16-bit PPG 8/9
0X000XX1B
000041HPPG 9 Operation Mode Control Register PPGC9 W,R/W 0X000001B
000042H
PPG 8/PPG 9 Count Clock Control
Register PPG89 R/W 000000X0B
000043HReserved
000044HPPG A Operation Mode Control Register PPGCA W,R/W
16-bit PPG A/B
0X000XX1B
000045HPPG B Operation Mode Control Register PPGCB W,R/W 0X000001B
000046H
PPG A/PPG B Count Clock Select
Register PPGAB R/W 000000X0B
000047HReserved
000048HPPG C Operation Mode Control Register PPGCC W,R/W
16-bit PPG C/D
0X000XX1B
000049HPPG D Operation Mode Control Register PPGCD W,R/W 0X000001B
00004AH
PPG C/PPG D Count Clock Select
Register PPGCD R/W 000000X0B
00004BHReserved
00004CHPPG E Operation Mode Control Register PPGCE W,R/W
16-bit PPG E/F
0X000XX1B
00004DHPPG F Operation Mode Control Register PPGCF W,R/W 0X000001B
00004EH
PPG E/PPG F Count Clock Select
Register PPGEF R/W 000000X0B
00004FHReserved
000050HInput Capture Control Status 0/1 ICS01 R/W Input Capture 0/1 00000000B
000051HInput Capture Edge 0/1 ICE01 R/W, R XXX0X0XXB
000052HInput Capture Control Status 2/3 ICS23 R/W Input Capture 2/3 00000000B
000053HInput Capture Edge 2/3 ICE23 R XXXXXXXXB
000054HInput Capture Control Status 4/5 ICS45 R/W Input Capture 4/5 00000000B
000055HInput Capture Edge 4/5 ICE45 R XXXXXXXXB
000056HInput Capture Control Status 6/7 ICS67 R/W Input Capture 6/7 00000000B
000057HInput Capture Edge 6/7 ICE67 R/W, R XXX000XXB
000058HOutput Compare Control Status 0 OCS0 R/W Output Compare 0/1 0000XX00B
000059HOutput Compare Control Status 1 OCS1 R/W 0XX00000B
00005AHOutput Compare Control Status 2 OCS2 R/W Output Compare 2/3 0000XX00B
00005BHOutput Compare Control Status 3 OCS3 R/W 0XX00000B
00005CHOutput Compare Control Status 4 OCS4 R/W Output Compare 4/5 0000XX00B
00005DHOutput Compare Control Status 5 OCS5 R/W 0XX00000B
00005EHOutput Compare Control Status 6 OCS6 R/W Output Compare 6/7 0000XX00B
00005FHOutput Compare Control Status 7 OCS7 R/W 0XX00000B
Document Number: 002-04498 Rev. *A Page 33 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
000060HTimer Control Status 0 TMCSR0 R/W 16-bit Reload
Timer 0
00000000B
000061HTimer Control Status 0 TMCSR0 R/W XXXX0000B
000062HTimer Control Status 1 TMCSR1 R/W 16-bit Reload
Timer 1
00000000B
000063HTimer Control Status 1 TMCSR1 R/W XXXX0000B
000064HTimer Control Status 2 TMCSR2 R/W 16-bit Reload
Timer 2
00000000B
000065HTimer Control Status 2 TMCSR2 R/W XXXX0000B
000066HTimer Control Status 3 TMCSR3 R/W 16-bit Reload
Timer 3
00000000B
000067HTimer Control Status 3 TMCSR3 R/W XXXX0000B
000068HA/D Control Status 0 ADCS0 R/W
A/D Converter
000XXXX0B
000069HA/D Control Status 1 ADCS1 R/W 0000000XB
00006AHA/D Data 0 ADCR0 R 00000000B
00006BHA/D Data 1 ADCR1 R XXXXXX00B
00006CHADC Setting 0 ADSR0 R/W 00000000B
00006DHADC Setting 1 ADSR1 R/W 00000000B
00006EHReserved
00006FHROM Mirror Function Select ROMM W ROM Mirror XXXXXXX1B
000070H
to
00008FH
Reserved for CAN Controller 0/1. Refer to “CAN Controllers”
000090H
to
00009AH
Reserved
00009BHDMA Descriptor Channel Specified
Register DCSR R/W
DMA
00000000B
00009CHDMA Status L Register DSRL R/W 00000000B
00009DHDMA Status H Register DSRH R/W 00000000B
00009EHAddress Detect Control Register 0 PACSR0 R/W Address Match
Detection 0 00000000B
00009FH
Delayed Interrupt Trigger/Release
Register DIRR R/W Delayed Interrupt XXXXXXX0B
0000A0HLow-power Mode Control Register LPMCR W,R/W Low Power
Control Circuit 00011000B
0000A1HClock Selection Register CKSCR R,R/W Low Power
Control Circuit 11111100B
0000A2H,
0000A3HReserved
0000A4HDMA Stop Status Register DSSR R/W DMA 00000000B
Document Number: 002-04498 Rev. *A Page 34 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
0000A5H
Automatic Ready Function Select
Register ARSR W
External Memory
Access
0011XX00B
0000A6H
External Address Output Control
Register HACR W 00000000B
0000A7HBus Control Signal Selection Register ECSR W 0000000XB
0000A8HWatchdog Control Register WDTC R,W Watchdog Timer XXXXX111B
0000A9HTime Base Timer Control Register TBTC W,R/W Time Base Timer 1XX00100B
0000AAHWatch Timer Control Register WTC R,R/W Watch Timer 1X001000B
0000ABHReserved
0000ACHDMA Enable L Register DERL R/W DMA 00000000B
0000ADHDMA Enable H Register DERH R/W 00000000B
0000AEH
Flash Control Status Register
(Flash memory devices only.
Otherwise reserved)
FMCS R,R/W Flash Memory 000X0000B
0000AFHReserved
0000B0HInterrupt Control Register 00 ICR00 W,R/W
Interrupt Control
00000111B
0000B1HInterrupt Control Register 01 ICR01 W,R/W 00000111B
0000B2HInterrupt Control Register 02 ICR02 W,R/W 00000111B
0000B3HInterrupt Control Register 03 ICR03 W,R/W 00000111B
0000B4HInterrupt Control Register 04 ICR04 W,R/W 00000111B
0000B5HInterrupt Control Register 05 ICR05 W,R/W 00000111B
0000B6HInterrupt Control Register 06 ICR06 W,R/W 00000111B
0000B7HInterrupt Control Register 07 ICR07 W,R/W 00000111B
0000B8HInterrupt Control Register 08 ICR08 W,R/W 00000111B
0000B9HInterrupt Control Register 09 ICR09 W,R/W 00000111B
0000BAHInterrupt Control Register 10 ICR10 W,R/W 00000111B
0000BBHInterrupt Control Register 11 ICR11 W,R/W 00000111B
0000BCHInterrupt Control Register 12 ICR12 W,R/W 00000111B
0000BDHInterrupt Control Register 13 ICR13 W,R/W 00000111B
0000BEHInterrupt Control Register 14 ICR14 W,R/W 00000111B
0000BFHInterrupt Control Register 15 ICR15 W,R/W 00000111B
0000C0HD/A Converter Data 0 DAT0 R/W
D/A Converter
XXXXXXXXB
0000C1HD/A Converter Data 1 DAT1 R/W XXXXXXXXB
0000C2HD/A Control 0 DACR0 R/W XXXXXXX0B
0000C3HD/A Control 1 DACR1 R/W XXXXXXX0B
Document Number: 002-04498 Rev. *A Page 35 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
0000C4H,
0000C5HReserved
0000C6HExternal Interrupt Enable 0 ENIR0 R/W
External Interrupt 0
00000000B
0000C7HExternal Interrupt Source 0 EIRR0 R/W XXXXXXXXB
0000C8HExternal Interrupt Level Setting 0 ELVR0 R/W 00000000B
0000C9HExternal Interrupt Level Setting 0 ELVR0 R/W 00000000B
0000CAHExternal Interrupt Enable 1 ENIR1 R/W
External Interrupt 1
00000000B
0000CBHExternal Interrupt Source 1 EIRR1 R/W XXXXXXXXB
0000CCHExternal Interrupt Level Setting 1 ELVR1 R/W 00000000B
0000CDHExternal Interrupt Level Setting 1 ELVR1 R/W 00000000B
0000CEHExternal Interrupt Source Select EISSR R/W 00000000B
0000CFHPLL/Sub clock Control Register PSCCR W PLL XXXX0000B
0000D0HDMA Buffer Address Pointer L Register BAPL R/W
DMA
XXXXXXXXB
0000D1HDMA Buffer Address Pointer M Register BAPM R/W XXXXXXXXB
0000D2HDMA Buffer Address Pointer H Register BAPH R/W XXXXXXXXB
0000D3HDMA Control Register DMACS R/W XXXXXXXXB
0000D4H
I/O Register Address Pointer L
Register IOAL R/W XXXXXXXXB
0000D5H
I/O Register Address Pointer H
Register IOAH R/W XXXXXXXXB
0000D6HData Counter L Register DCTL R/W XXXXXXXXB
0000D7HData Counter H Register DCTH R/W XXXXXXXXB
0000D8HSerial Mode Register 2 SMR2 W,R/W
UART2
00000000B
0000D9HSerial Control Register 2 SCR2 W,R/W 00000000B
0000DAH
Reception/Transmission Data
Register 2 RDR2/TDR2 R/W 00000000B
0000DBHSerial Status Register 2 SSR2 R,R/W 00001000B
0000DCH
Extended Communication Control
Register 2 ECCR2 R,W,
R/W 000000XXB
0000DDHExtended Status Control Register 2 ESCR2 R/W 00000100B
0000DEHBaud Rate Generator Register 20 BGR20 R/W 00000000B
0000DFHBaud Rate Generator Register 21 BGR21 R/W 00000000B
0000E0H
to
0000EFH
Reserved for CAN Controller 2. Refer to “CAN Controllers”
0000F0H
to
0000FFH
External
Document Number: 002-04498 Rev. *A Page 36 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
007900HReload Register L0 PRLL0 R/W
16-bit PPG 0/1
XXXXXXXXB
007901HReload Register H0 PRLH0 R/W XXXXXXXXB
007902HReload Register L1 PRLL1 R/W XXXXXXXXB
007903HReload Register H1 PRLH1 R/W XXXXXXXXB
007904HReload Register L2 PRLL2 R/W
16-bit PPG 2/3
XXXXXXXXB
007905HReload Register H2 PRLH2 R/W XXXXXXXXB
007906HReload Register L3 PRLL3 R/W XXXXXXXXB
007907HReload Register H3 PRLH3 R/W XXXXXXXXB
007908HReload Register L4 PRLL4 R/W
16-bit PPG 4/5
XXXXXXXXB
007909HReload Register H4 PRLH4 R/W XXXXXXXXB
00790AHReload Register L5 PRLL5 R/W XXXXXXXXB
00790BHReload Register H5 PRLH5 R/W XXXXXXXXB
00790CHReload Register L6 PRLL6 R/W
16-bit PPG 6/7
XXXXXXXXB
00790DHReload Register H6 PRLH6 R/W XXXXXXXXB
00790EHReload Register L7 PRLL7 R/W XXXXXXXXB
00790FHReload Register H7 PRLH7 R/W XXXXXXXXB
007910HReload Register L8 PRLL8 R/W
16-bit PPG 8/9
XXXXXXXXB
007911HReload Register H8 PRLH8 R/W XXXXXXXXB
007912HReload Register L9 PRLL9 R/W XXXXXXXXB
007913HReload Register H9 PRLH9 R/W XXXXXXXXB
007914HReload Register LA PRLLA R/W
16-bit PPG A/B
XXXXXXXXB
007915HReload Register HA PRLHA R/W XXXXXXXXB
007916HReload Register LB PRLLB R/W XXXXXXXXB
007917HReload Register HB PRLHB R/W XXXXXXXXB
007918HReload Register LC PRLLC R/W
16-bit PPG C/D
XXXXXXXXB
007919HReload Register HC PRLHC R/W XXXXXXXXB
00791AHReload Register LD PRLLD R/W XXXXXXXXB
00791BHReload Register HD PRLHD R/W XXXXXXXXB
00791CHReload Register LE PRLLE R/W
16-bit PPG E/F
XXXXXXXXB
00791DHReload Register HE PRLHE R/W XXXXXXXXB
00791EHReload Register LF PRLLF R/W XXXXXXXXB
00791FHReload Register HF PRLHF R/W XXXXXXXXB
007920HInput Capture 0 IPCP0 R
Input Capture 0/1
XXXXXXXXB
007921HInput Capture 0 IPCP0 R XXXXXXXXB
007922HInput Capture 1 IPCP1 R XXXXXXXXB
007923HInput Capture 1 IPCP1 R XXXXXXXXB
Document Number: 002-04498 Rev. *A Page 37 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
007924HInput Capture 2 IPCP2 R
Input Capture 2/3
XXXXXXXXB
007925HInput Capture 2 IPCP2 R XXXXXXXXB
007926HInput Capture 3 IPCP3 R XXXXXXXXB
007927HInput Capture 3 IPCP3 R XXXXXXXXB
007928HInput Capture 4 IPCP4 R
Input Capture 4/5
XXXXXXXXB
007929HInput Capture 4 IPCP4 R XXXXXXXXB
00792AHInput Capture 5 IPCP5 R XXXXXXXXB
00792BHInput Capture 5 IPCP5 R XXXXXXXXB
00792CHInput Capture 6 IPCP6 R
Input Capture 6/7
XXXXXXXXB
00792DHInput Capture 6 IPCP6 R XXXXXXXXB
00792EHInput Capture 7 IPCP7 R XXXXXXXXB
00792FHInput Capture 7 IPCP7 R XXXXXXXXB
007930HOutput Compare 0 OCCP0 R/W
Output Compare 0/1
XXXXXXXXB
007931HOutput Compare 0 OCCP0 R/W XXXXXXXXB
007932HOutput Compare 1 OCCP1 R/W XXXXXXXXB
007933HOutput Compare 1 OCCP1 R/W XXXXXXXXB
007934HOutput Compare 2 OCCP2 R/W
Output Compare 2/3
XXXXXXXXB
007935HOutput Compare 2 OCCP2 R/W XXXXXXXXB
007936HOutput Compare 3 OCCP3 R/W XXXXXXXXB
007937HOutput Compare 3 OCCP3 R/W XXXXXXXXB
007938HOutput Compare 4 OCCP4 R/W
Output Compare 4/5
XXXXXXXXB
007939HOutput Compare 4 OCCP4 R/W XXXXXXXXB
00793AHOutput Compare 5 OCCP5 R/W XXXXXXXXB
00793BHOutput Compare 5 OCCP5 R/W XXXXXXXXB
00793CHOutput Compare 6 OCCP6 R/W
Output Compare 6/7
XXXXXXXXB
00793DHOutput Compare 6 OCCP6 R/W XXXXXXXXB
00793EHOutput Compare 7 OCCP7 R/W XXXXXXXXB
00793FHOutput Compare 7 OCCP7 R/W XXXXXXXXB
007940HTimer Data 0 TCDT0 R/W
Free-run Timer 0
00000000B
007941HTimer Data 0 TCDT0 R/W 00000000B
007942HTimer Control Status 0 TCCSL0 R/W 00000000B
007943HTimer Control Status 0 TCCSH0 R/W 0XXXXXXXB
007944HTimer Data 1 TCDT1 R/W
Free-run Timer 1
00000000B
007945HTimer Data 1 TCDT1 R/W 00000000B
007946HTimer Control Status 1 TCCSL1 R/W 00000000B
007947HTimer Control Status 1 TCCSH1 R/W 0XXXXXXXB
Document Number: 002-04498 Rev. *A Page 38 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
007948HTimer 0/Reload 0 TMR0/TMRLR0 R/W 16-bit Reload
Timer 0
XXXXXXXXB
007949HR/W XXXXXXXXB
00794AHTimer 1/Reload 1 TMR1/TMRLR1 R/W 16-bit Reload
Timer 1
XXXXXXXXB
00794BHR/W XXXXXXXXB
00794CHTimer 2/Reload 2 TMR2/TMRLR2 R/W 16-bit Reload
Timer 2
XXXXXXXXB
00794DHR/W XXXXXXXXB
00794EHTimer 3/Reload 3 TMR3/TMRLR3 R/W 16-bit Reload
Timer 3
XXXXXXXXB
00794FHR/W XXXXXXXXB
007950HSerial Mode Register 3 SMR3 W,R/W
UART3
00000000B
007951HSerial Control Register 3 SCR3 W,R/W 00000000B
007952H
Reception/Transmission Data
Register 3 RDR3/TDR3 R/W 00000000B
007953HSerial Status Register 3 SSR3 R,R/W 00001000B
007954H
Extended Communication Control
Register 3 ECCR3 R,W,
R/W 000000XXB
007955HExtended Status Control Register ESCR3 R/W 00000100B
007956HBaud Rate Generator Register 30 BGR30 R/W 00000000B
007957HBaud Rate Generator Register 31 BGR31 R/W 00000000B
007958HSerial Mode Register 4 SMR4 W,R/W
UART4
00000000B
007959HSerial Control Register 4 SCR4 W,R/W 00000000B
00795AH
Reception/Transmission Data
Register 4 RDR4/TDR4 R/W 00000000B
00795BHSerial Status Register 4 SSR4 R,R/W 00001000B
00795CH
Extended Communication Control
Register 4 ECCR4 R,W,
R/W 000000XXB
00795DHExtended Status Control Register ESCR4 R/W 00000100B
00795EHBaud Rate Generator Register 40 BGR40 R/W 00000000B
00795FHBaud Rate Generator Register 41 BGR41 R/W 00000000B
007960H
to
00796BH
Reserved
00796CHClock Output Enable Register CLKR R/W Clock Monitor XXXX0000B
00796DHReserved
00796EHCAN Direct Mode Register CDMR R/W CAN Clock sync XXXXXXX0B
00796FHCAN Switch Register CANSWR R/W CAN 0/1 XXXXXX00B
Document Number: 002-04498 Rev. *A Page 39 of 92
MB90340E Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
007970HI2C Bus Status Register 0 IBSR0 R
I2C Interface 0
00000000B
007971HI2C Bus Control Register 0 IBCR0 W,R/W 00000000B
007972HI2C 10-bit Slave Address Register 0 ITBAL0 R/W 00000000B
007973HITBAH0 R/W 00000000B
007974HI2C 10-bit Slave Address Mask
Register 0
ITMKL0 R/W 11111111B
007975HITMKH0 R/W 00111111B
007976HI2C 7-bit Slave Address Register 0 ISBA0 R/W 00000000B
007977HI2C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111B
007978HI2C Data Register 0 IDAR0 R/W 00000000B
007979H,
00797AHReserved
00797BHI2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111B
00797CH
to
00797FH
Reserved
007980HI2C Bus Status Register 1 IBSR1 R
I2C Interface 1
00000000B
007981HI2C Bus Control Register 1 IBCR1 W,R/W 00000000B
007982HI2C 10-bit Slave Address Register 1 ITBAL1 R/W 00000000B
007983HITBAH1 R/W 00000000B
007984HI2C 10-bit Slave Address Mask
Register 1
ITMKL1 R/W 11111111B
007985HITMKH1 R/W 00111111B
007986HI2C 7-bit Slave Address Register 1 ISBA1 R/W 00000000B
007987HI2C 7-bit Slave Address Mask Register 1 ISMK1 R/W 01111111B
007988HI2C Data Register 1 IDAR1 R/W 00000000B
007989H,
00798AHReserved
00798BHI2C Clock Control Register 1 ICCR1 R/W I2C Interface 1 00011111B
00798CH
to
0079C1H
Reserved
0079C2HClock Modulator Control Register CMCR R, R/W Clock Modulator 0001X000B
0079C3H
to
0079DFH
Reserved
Document Number: 002-04498 Rev. *A Page 40 of 92
MB90340E Series
(Continued)
Note: Initial value of “X” represents unknown value.
Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
Address Register Abbreviation Access Resource name Initial value
0079E0HDetect Address Setting 0 PADR0 R/W
Address Match
Detection 0
XXXXXXXXB
0079E1HDetect Address Setting 0 PADR0 R/W XXXXXXXXB
0079E2HDetect Address Setting 0 PADR0 R/W XXXXXXXXB
0079E3HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E4HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E5HDetect Address Setting 1 PADR1 R/W XXXXXXXXB
0079E6HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E7HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E8HDetect Address Setting 2 PADR2 R/W XXXXXXXXB
0079E9H
to
0079EFH
Reserved
0079F0HDetect Address Setting 3 PADR3 R/W
Address Match
Detection 1
XXXXXXXXB
0079F1HDetect Address Setting 3 PADR3 R/W XXXXXXXXB
0079F2HDetect Address Setting 3 PADR3 R/W XXXXXXXXB
0079F3HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F4HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F5HDetect Address Setting 4 PADR4 R/W XXXXXXXXB
0079F6HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F7HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F8HDetect Address Setting 5 PADR5 R/W XXXXXXXXB
0079F9H
to
0079FFH
Reserved
007A00H
to
007AFFH
Reserved for CAN Controller 0. Refer to “CAN Controllers
007B00H
to
007BFFH
Reserved for CAN Controller 0. Refer to “CAN Controllers”
007C00H
to
007CFFH
Reserved for CAN Controller 1. Refer to “CAN Controllers”
007D00H
to
007DFFH
Reserved for CAN Controller 1. Refer to “CAN Controllers”
007E00H
to
007FFFH
Reserved
Document Number: 002-04498 Rev. *A Page 41 of 92
MB90340E Series
9. CAN Controllers
The CAN controller has the following features:
Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmission/reception message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID
acceptance mask
Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
000070H000080HMessage Buffer
Valid Register BVALR R/W 00000000B
00000000B
000071H000081H
000072H000082HTransmit Request
Register TREQR R/W 00000000B
00000000B
000073H000083H
000074H000084HTransmit Cancel
Register TCANR W 00000000B
00000000B
000075H000085H
000076H000086HTransmission
Complete Register TCR R/W 00000000B
00000000B
000077H000087H
000078H000088HReceive Complete
Register RCR R/W 00000000B
00000000B
000079H000089H
00007AH00008AHRemote Request
Receiving Register RRTRR R/W 00000000B
00000000B
00007BH00008BH
00007CH00008CHReceive Overrun
Register ROVRR R/W 00000000B
00000000B
00007DH00008DH
00007EH00008EHReception Interrupt
Enable Register RIER R/W 00000000B
00000000B
00007FH00008FH
Document Number: 002-04498 Rev. *A Page 42 of 92
MB90340E Series
List of Control Registers (2)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007B00H007D00HControl Status
Register CSR R/W, W
R/W, R
0XXXX0X1B
00XXX000B007B01H007D01H
007B02H007D02HLast Event
Indicator Register LEIR R/W 000X0000B
XXXXXXXXB
007B03H007D03H
007B04H007D04HReceive And Transmit
Error Counter RTEC R 00000000B
00000000B
007B05H007D05H
007B06H007D06HBit Timing
Register BTR R/W 11111111B
X1111111B
007B07H007D07H
007B08H007D08HIDE Register IDER R/W XXXXXXXXB
XXXXXXXXB
007B09H007D09H
007B0AH007D0AHTransmit RTR
Register TRTRR R/W 00000000B
00000000B
007B0BH007D0BH
007B0CH007D0CHRemote Frame
Receive Waiting
Register
RFWTR R/W XXXXXXXXB
XXXXXXXXB
007B0DH007D0DH
007B0EH007D0EHTransmit Interrupt
Enable Register TIER R/W 00000000B
00000000B
007B0FH007D0FH
007B10H007D10H
Acceptance Mask
Select Register AMSR R/W
XXXXXXXXB
XXXXXXXXB
007B11H007D11H
007B12H007D12HXXXXXXXXB
XXXXXXXXB
007B13H007D13H
007B14H007D14H
Acceptance Mask
Register 0 AMR0 R/W
XXXXXXXXB
XXXXXXXXB
007B15H007D15H
007B16H007D16HXXXXXXXXB
XXXXXXXXB007B17H007D17H
007B18H007D18H
Acceptance Mask
Register 1 AMR1 R/W
XXXXXXXXB
XXXXXXXXB
007B19H007D19H
007B1AH007D1AHXXXXXXXXB
XXXXXXXXB007B1BH007D1BH
Document Number: 002-04498 Rev. *A Page 43 of 92
MB90340E Series
List of Message Buffers (ID Registers) (1)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007A00H
to
007A1FH
007C00H
to
007C1FH
General-
Purpose RAM R/W
XXXXXXXXB
to
XXXXXXXXB
007A20H007C20H
ID Register 0 IDR0 R/W
XXXXXXXXB
XXXXXXXXB
007A21H007C21H
007A22H007C22HXXXXXXXXB
XXXXXXXXB007A23H007C23H
007A24H007C24H
ID Register 1 IDR1 R/W
XXXXXXXXB
XXXXXXXXB
007A25H007C25H
007A26H007C26HXXXXXXXXB
XXXXXXXXB
007A27H007C27H
007A28H007C28H
ID Register 2 IDR2 R/W
XXXXXXXXB
XXXXXXXXB
007A29H007C29H
007A2AH007C2AHXXXXXXXXB
XXXXXXXXB
007A2BH007C2BH
007A2CH007C2CH
ID Register 3 IDR3 R/W
XXXXXXXXB
XXXXXXXXB
007A2DH007C2DH
007A2EH007C2EHXXXXXXXXB
XXXXXXXXB
007A2FH007C2FH
007A30H007C30H
ID Register 4 IDR4 R/W
XXXXXXXXB
XXXXXXXXB
007A31H007C31H
007A32H007C32HXXXXXXXXB
XXXXXXXXB
007A33H007C33H
007A34H007C34H
ID Register 5 IDR5 R/W
XXXXXXXXB
XXXXXXXXB
007A35H007C35H
007A36H007C36HXXXXXXXXB
XXXXXXXXB
007A37H007C37H
007A38H007C38H
ID Register 6 IDR6 R/W
XXXXXXXXB
XXXXXXXXB
007A39H007C39H
007A3AH007C3AHXXXXXXXXB
XXXXXXXXB
007A3BH007C3BH
007A3CH007C3CH
ID Register 7 IDR7 R/W
XXXXXXXXB
XXXXXXXXB
007A3DH007C3DH
007A3EH007C3EHXXXXXXXXB
XXXXXXXXB
007A3FH007C3FH
Document Number: 002-04498 Rev. *A Page 44 of 92
MB90340E Series
List of Message Buffers (ID Registers) (2)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007A40H007C40H
ID Register 8 IDR8 R/W
XXXXXXXXB
XXXXXXXXB
007A41H007C41H
007A42H007C42HXXXXXXXXB
XXXXXXXXB
007A43H007C43H
007A44H007C44H
ID Register 9 IDR9 R/W
XXXXXXXXB
XXXXXXXXB
007A45H007C45H
007A46H007C46HXXXXXXXXB
XXXXXXXXB
007A47H007C47H
007A48H007C48H
ID Register 10 IDR10 R/W
XXXXXXXXB
XXXXXXXXB
007A49H007C49H
007A4AH007C4AHXXXXXXXXB
XXXXXXXXB
007A4BH007C4BH
007A4CH007C4CH
ID Register 11 IDR11 R/W
XXXXXXXXB
XXXXXXXXB
007A4DH007C4DH
007A4EH007C4EHXXXXXXXXB
XXXXXXXXB
007A4FH007C4FH
007A50H007C50H
ID Register 12 IDR12 R/W
XXXXXXXXB
XXXXXXXXB
007A51H007C51H
007A52H007C52HXXXXXXXXB
XXXXXXXXB
007A53H007C53H
007A54H007C54H
ID Register 13 IDR13 R/W
XXXXXXXXB
XXXXXXXXB
007A55H007C55H
007A56H007C56HXXXXXXXXB
XXXXXXXXB
007A57H007C57H
007A58H007C58H
ID Register 14 IDR14 R/W
XXXXXXXXB
XXXXXXXXB
007A59H007C59H
007A5AH007C5AHXXXXXXXXB
XXXXXXXXB
007A5BH007C5BH
007A5CH007C5CH
ID Register 15 IDR15 R/W
XXXXXXXXB
XXXXXXXXB
007A5DH007C5DH
007A5EH007C5EHXXXXXXXXB
XXXXXXXXB
007A5FH007C5FH
Document Number: 002-04498 Rev. *A Page 45 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007A60H007C60HDLC Register 0 DLCR0 R/W XXXXXXXXB
007A61H007C61H
007A62H007C62HDLC Register 1 DLCR1 R/W XXXXXXXXB
007A63H007C63H
007A64H007C64HDLC Register 2 DLCR2 R/W XXXXXXXXB
007A65H007C65H
007A66H007C66HDLC Register 3 DLCR3 R/W XXXXXXXXB
007A67H007C67H
007A68H007C68HDLC Register 4 DLCR4 R/W XXXXXXXXB
007A69H007C69H
007A6AH007C6AHDLC Register 5 DLCR5 R/W XXXXXXXXB
007A6BH007C6BH
007A6CH007C6CHDLC Register 6 DLCR6 R/W XXXXXXXXB
007A6DH007C6DH
007A6EH007C6EHDLC Register 7 DLCR7 R/W XXXXXXXXB
007A6FH007C6FH
007A70H007C70HDLC Register 8 DLCR8 R/W XXXXXXXXB
007A71H007C71H
007A72H007C72HDLC Register 9 DLCR9 R/W XXXXXXXXB
007A73H007C73H
007A74H007C74HDLC Register 10 DLCR10 R/W XXXXXXXXB
007A75H007C75H
007A76H007C76HDLC Register 11 DLCR11 R/W XXXXXXXXB
007A77H007C77H
007A78H007C78HDLC Register 12 DLCR12 R/W XXXXXXXXB
007A79H007C79H
007A7AH007C7AHDLC Register 13 DLCR13 R/W XXXXXXXXB
007A7BH007C7BH
007A7CH007C7CHDLC Register 14 DLCR14 R/W XXXXXXXXB
007A7DH007C7DH
007A7EH007C7EHDLC Register 15 DLCR15 R/W XXXXXXXXB
007A7FH007C7FH
Document Number: 002-04498 Rev. *A Page 46 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007A80H
to
007A87H
007C80H
to
007C87H
Data Register 0
(8 bytes) DTR0 R/W
XXXXXXXXB
to
XXXXXXXXB
007A88H
to
007A8FH
007C88H
to
007C8FH
Data Register 1
(8 bytes) DTR1 R/W
XXXXXXXXB
to
XXXXXXXXB
007A90H
to
007A97H
007C90H
to
007C97H
Data Register 2
(8 bytes) DTR2 R/W
XXXXXXXXB
to
XXXXXXXXB
007A98H
to
007A9FH
007C98H
to
007C9FH
Data Register 3
(8 bytes) DTR3 R/W
XXXXXXXXB
to
XXXXXXXXB
007AA0H
to
007AA7H
007CA0H
to
007CA7H
Data Register 4
(8 bytes) DTR4 R/W
XXXXXXXXB
to
XXXXXXXXB
007AA8H
to
007AAFH
007CA8H
to
007CAFH
Data Register 5
(8 bytes) DTR5 R/W
XXXXXXXXB
to
XXXXXXXXB
007AB0H
to
007AB7H
007CB0H
to
007CB7H
Data Register 6
(8 bytes) DTR6 R/W
XXXXXXXXB
to
XXXXXXXXB
007AB8H
to
007ABFH
007CB8H
to
007CBFH
Data Register 7
(8 bytes) DTR7 R/W
XXXXXXXXB
to
XXXXXXXXB
007AC0H
to
007AC7H
007CC0H
to
007CC7H
Data Register 8
(8 bytes) DTR8 R/W
XXXXXXXXB
to
XXXXXXXXB
007AC8H
to
007ACFH
007CC8H
to
007CCFH
Data Register 9
(8 bytes) DTR9 R/W
XXXXXXXXB
to
XXXXXXXXB
007AD0H
to
007AD7H
007CD0H
to
007CD7H
Data Register 10
(8 bytes) DTR10 R/W
XXXXXXXXB
to
XXXXXXXXB
007AD8H
to
007ADFH
007CD8H
to
007CDFH
Data Register 11
(8 bytes) DTR11 R/W
XXXXXXXXB
to
XXXXXXXXB
007AE0H
to
007AE7H
007CE0H
to
007CE7H
Data Register 12
(8 bytes) DTR12 R/W
XXXXXXXXB
to
XXXXXXXXB
007AE8H
to
007AEFH
007CE8H
to
007CEFH
Data Register 13
(8 bytes) DTR13 R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-04498 Rev. *A Page 47 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
007AF0H
to
007AF7H
007CF0H
to
007CF7H
Data Register 14
(8 bytes) DTR14 R/W
XXXXXXXXB
to
XXXXXXXXB
007AF8H
to
007AFFH
007CF8H
to
007CFFH
Data Register 15
(8 bytes) DTR15 R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-04498 Rev. *A Page 48 of 92
MB90340E Series
10. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
(Continued)
Interrupt cause EI2OS
Support
DMA
channel
number
Interrupt vector Interrupt control
register
Number Address Number Address
Reset N #08 FFFFDCH
INT9 instruction N #09 FFFFD8H
Exception N #10 FFFFD4H
CAN 0 RX N #11 FFFFD0HICR00 0000B0H
CAN 0 TX/NS N #12 FFFFCCH
CAN 1 RX / Input Capture 6 Y1 #13 FFFFC8HICR01 0000B1H
CAN 1 TX/NS / Input Capture 7 Y1 #14 FFFFC4H
CAN 2 RX / I2C0 N #15 FFFFC0HICR02 0000B2H
CAN 2 TX/NS N #16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8HICR03 0000B3H
16-bit Reload Timer 1 Y1 1 #18 FFFFB4H
16-bit Reload Timer 2 Y1 2 #19 FFFFB0HICR04 0000B4H
16-bit Reload Timer 3 Y1 #20 FFFFACH
PPG 0/1/4/5 N #21 FFFFA8HICR05 0000B5H
PPG 2/3/6/7 N #22 FFFFA4H
PPG 8/9/C/D N #23 FFFFA0HICR06 0000B6H
PPG A/B/E/F N #24 FFFF9CH
Time Base Timer N #25 FFFF98HICR07 0000B7H
External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N #27 FFFF90HICR08 0000B8H
External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8CH
A/D Converter Y1 5 #29 FFFF88HICR09 0000B9H
Free-run Timer 0 / Free-run Timer 1 N #30 FFFF84H
Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80HICR10 0000BAH
Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH
Input Capture 0 to 3 Y1 8 #33 FFFF78HICR11 0000BBH
Output Compare 2/3/6/7 Y1 9 #34 FFFF74H
UART 0 RX Y2 10 #35 FFFF70HICR12 0000BCH
UART 0 TX Y1 11 #36 FFFF6CH
UART 1 RX / UART 3 RX Y2 12 #37 FFFF68HICR13 0000BDH
UART 1 TX / UART 3 TX Y1 13 #38 FFFF64H
Document Number: 002-04498 Rev. *A Page 49 of 92
MB90340E Series
(Continued)
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Note: The peripheral resources sharing the ICR register have the same interrupt level.
When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
Interrupt cause EI2OS
Support
DMA
channel
number
Interrupt vector Interrupt control
register
Number Address Number Address
UART 2 RX / UART 4 RX Y2 14 #39 FFFF60HICR14 0000BEH
UART 2 TX / UART 4 TX Y1 15 #40 FFFF5CH
Flash Memory N #41 FFFF58HICR15 0000BFH
Delayed Interrupt N #42 FFFF54H
Document Number: 002-04498 Rev. *A Page 50 of 92
MB90340E Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does
not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an
input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0, PA1
*5: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (Evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
Use within recommended operating conditions.
Use with DC voltage (current)
The B signal should always be applied by using a limiting resistance placed between the B signal and the microcontroller.
The value of the limiting resistance should be set so that when the B signal is applied, the input current to
the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC VSS 0.3 VSS 6.0 V
AVCC VSS 0.3 VSS 6.0 V VCC AVCC*2
AVRH,
AVRL VSS 0.3 VSS 6.0 V AVCC AVRH, AVCC AVRL, AVRH
AVRL
Input voltage*1VIVSS 0.3 VSS 6.0 V *3
Output voltage*1VOVSS 0.3 VSS 6.0 V *3
Maximum Clamp Current ICLAMP 4.0 4.0 mA *5
Total Maximum Clamp Current |ICLAMP|40 mA *5
“L” level maximum output current IOL 15 mA *4, *6
“L” level average output current IOLAV 4mA*4, *7
“L” level maximum overall output current IOL 100 mA *4
“L” level average overall output current IOLAV 50 mA *4, *8
“H” level maximum output current IOH 15 mA *4, *6
“H” level average output current IOHAV 4mA*4, *7
“H” level maximum overall output current IOH 100 mA *4
“H” level average overall output current IOHAV 50 mA *4, *8
Power consumption PD450 mW
Operating temperature TA40 105 °C
Storage temperature TSTG 55 150 °C
Document Number: 002-04498 Rev. *A Page 51 of 92
MB90340E Series
(Continued)
Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the B input pin open.
Sample recommended circuits:
*6: The maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*7: The average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins.
*8: The average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
Input/output equivalent circuits
B input (0 V to 16 V)
Limiting
resistance
Protective diode
Document Number: 002-04498 Rev. *A Page 52 of 92
MB90340E Series
11.2 Recommended Operating Conditions
(VSS AVSS 0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC,
AVCC
4.0 5.0 5.5 V Under normal operation
3.5 5.0 5.5 V
Under normal operation, when not using the A/D
converter and not Flash
programming.
4.5 5.0 5.5 V When External bus is used.
3.0 5.5 V Maintains RAM data in stop mode
Smoothing capacitor CS0.1 1.0 F
Use a ceramic capacitor or capacitor of better AC
characteristics. Capacitor at the VCC should be
greater than this
capacitor.
Operating temperature TA40 105 °C
C
C
S
C Pin Connection Diagram
Document Number: 002-04498 Rev. *A Page 53 of 92
MB90340E Series
11.3 DC Characteristics
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
(Continued)
Parameter Symb
ol Pin Condition Value Unit Remarks
Min Typ Max
Input H
voltage
(At VCC
5 V 10)
VIHS 0.8 VCC VCC 0.3 V
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VIHA 0.8 VCC VCC 0.3 V Port inputs if
Automotive input levels are selected
VIHT 2.0 VCC 0.3 V Port inputs if TTL input levels are
selected
VIHS 0.7 VCC VCC 0.3 V
P12, P50, P82, P85
inputs if CMOS input levels are
selected
VIHI 0.7 VCC VCC 0.3 V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
VIHR 0.8 VCC VCC 0.3 V RST input pin
(CMOS hysteresis)
VIHM VCC 0.3 VCC 0.3 V MD input pin
Input L
voltage
(At VCC
5 V 10)
VILS VSS 0.3 0.2 VCC V
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VILA VSS 0.3 0.5 VCC VPort inputs if
Automotive input levels are selected
VILT VSS 0.3 0.8 V Port inputs if TTL
input levels are selected
VILS VSS 0.3 0.3 VCC V
P12, P50, P82, P85
inputs if CMOS input levels are
selected
VILI VSS 0.3 0.3 VCC V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
VILR VSS 0.3 0.2 VCC VRST input pin
(CMOS hysteresis)
VILM VSS 0.3 VSS 0.3 V MD input pin
Output H
voltage VOH
Normal
outputs
VCC 4.5 V,
IOH 4.0 mA VCC 0.5 V
Output H
voltage VOHI
I2C current
outputs
VCC 4.5 V,
IOH 3.0 mA VCC 0.5 V
Output L
voltage VOL
Normal
outputs
VCC 4.5 V,
IOL 4.0 mA 0.4 V
Output L
voltage VOLI
I2C current
outputs
VCC 4.5 V,
IOL 3.0 mA 0.4 V
Document Number: 002-04498 Rev. *A Page 54 of 92
MB90340E Series
(Continued)
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
* : The power supply current is measured with an external clock.
Parameter Symbo
lPin Condition Value Unit Remarks
Min Typ Max
Input leak current IIL VCC 5.5 V, VSS VI VCC 11A
Pull-up
resistance RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
25 50 100 k
Pull-down
resistance RDOWN MD2 25 50 100 kExcept Flash
memory
devices
Power supply
current*
ICC
VCC
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
55 70 mA
VCC 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
70 85 mA
Flash
memory
devices
VCC 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
75 90 mA
Flash
memory
devices
ICCS
VCC 5.0 V,
Internal frequency : 24 MHz,
In Sleep mode.
25 35 mA
ICTS
VCC 5.0 V,
Internal frequency : 2 MHz,
In Main Timer mode
0.3 0.8 mA
ICTSPLL6
VCC 5.0 V,
Internal frequency : 24 MHz,
In PLL Timer mode,
external frequency 4 MHz
47mA
ICCL
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub operation
TA = 25C
70 140 A
ICCLS
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub sleep
TA = 25C
20 50 A
ICCT
VCC = 5.0 V
Internal frequency : 8 kHz,
In watch mode
TA = 25C
10 35 A
ICCH
VCC 5.0 V,
In Stop mode,
TA 25C
725A
Input capacitance CIN
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS
515pF
Document Number: 002-04498 Rev. *A Page 55 of 92
MB90340E Series
11.4 AC Characteristics
11.4.1 Clock Timing
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within the range as
mentioned in “Relation between the external clock frequency and machine clock frequency”.
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Clock frequency fCX0, X1
316 MHz When using an oscillation circuit
416 MHz PLL multiplied by 1
When using an oscillation circuit
412 MHz PLL multiplied by 2
When using an oscillation circuit
48MHz
PLL multiplied by 3
When using an oscillation circuit
46MHz
PLL multiplied by 4
When using an oscillation circuit
4MHz
PLL multiplied by 6
When using an oscillation circuit
324 MHz When using an external clock*
fCL X0A, X1A — 32.768 100 kHz
Clock cycle time tCYL
X0, X1 62.5 333 ns When using an oscillation circuit
X0, X1 41.67 333 ns When using an external clock
tCYLL X0A, X1A 10 30.5 — s
Input clock pulse width PWH, PWL X0 10 ns Duty ratio is about 30 to 70.
PWHL, PWLL X0A 5 15.2 s
Input clock rise and fall time tCR, tCF X0 5 ns When using external clock
Internal operating clock
frequency (machine clock)
fCP 1.5 24 MHz When using main clock
fCPL 8.192 50 kHz When using sub clock
Internal operating clock
cycle time (machine clock)
tCP 41.67 666 ns When using main clock
tCPL 20 122.1 s When using sub clock
Document Number: 002-04498 Rev. *A Page 56 of 92
MB90340E Series
X0
t
CYL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WH
P
WL
X0A
t
CYLL
t
CF
t
CR
0.8 V
CC
0.2 V
CC
P
WHL
P
WLL
Clock Timing
Document Number: 002-04498 Rev. *A Page 57 of 92
MB90340E Series
Guaranteed PLL operation range
Guaranteed operation range of MB90340E series
* : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
24
5.5
3.5
1.5 4
Power supply voltage
VCC (V)
Guaranteed operation range
Guaranteed PLL operation range
4.0
Guaranteed A/D Converter
operation range
Machine clock fCP (MHz)
24
4.0
16
12
3412 24
Internal clock
fCP (MHz)
External clock fC (MHz) *
x 4 x 3 x 2 x 1
x 1/2
(PLL off)
8
8
Guaranteed oscillation frequency range
1.5
16
x 6
Document Number: 002-04498 Rev. *A Page 58 of 92
MB90340E Series
11.4.2 Reset Standby Input
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0.0 V)
* : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred s and several ms, and for an external clock, the time is 0 ms.
Parameter Symbol Pin Value Unit Remarks
Min Max
Reset input time tRSTL RST
500 ns Under normal operation
Oscillation time of oscillator*
100 ss
In Stop mode, Sub Clock mode,
Sub Sleep mode and Watch
mode
100 s In Time Timer mode
tRSTL
0.2 VCC 0.2 VCC
100 µs
RST
X0
90% of
amplitude
Instruction execution
Oscillation stabilization
waiting time
Oscillation time
of oscillator
Internal operation
clock
Internal reset
0.2 VCC
RST
tRSTL
0.2 VCC
Under normal operation:
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
Document Number: 002-04498 Rev. *A Page 59 of 92
MB90340E Series
11.4.3 Power On Reset
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0.0 V)
Note: : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup
smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below.
Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL
clock.
11.4.4 Clock Output Timing
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Power on rise time tRVCC 0.05 30 ms
Power off time tOFF VCC 1ms Waiting time until power-on
Parameter Symbol Pin Condition Value Unit Remarks
Min Max
Cycle time tCYC CLK 62.5 ns fCP 16 MHz
41.67 ns fCP 24 MHz
CLK CLK tCHCL CLK 20 ns fCP 16 MHz
13 ns fCP 24 MHz
V
CC
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
VCC
VSS
3 V Holds RAM data
We recommend a rise of
50 mV/ms maximum.
Document Number: 002-04498 Rev. *A Page 60 of 92
MB90340E Series
CLK 2.4 V
t
CYC
2.4 V
0.8 V
t
CHCL
Document Number: 002-04498 Rev. *A Page 61 of 92
MB90340E Series
11.4.5 Bus Timing (Read)
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Parameter Symbol Pin Condition Value Unit
Min Max
ALE pulse width tLHLL ALE
tCP/2 10 ns
Valid address
ALE time tAVLL ALE, A23 to A16, AD15 to
AD00 tCP/2 20 ns
ALE
Address valid time tLLAX ALE, AD15 to AD00 tCP/2 15 ns
Valid address
RD time tAVRL A23 to A16,
AD15 to AD00, RD tCP 15 ns
Valid address
Valid data input tAVDV A23 to A16,
AD15 to AD00 5 tCP/2 60 ns
RD pulse width tRLRH RD 3 tCP/2 20 ns
RD Valid data input tRLDV RD, AD15 to AD00 3 tCP/2 50 ns
RD Data hold time tRHDX RD, AD15 to AD00 0 ns
RD ALE time tRHLH RD, ALE tCP/2 15 ns
RD Address valid time tRHAX RD, A23 to A16 tCP/2 10 ns
Valid address
CLK time tAVCH A23 to A16,
AD15 to AD00, CLK tCP/2 16 ns
RD CLK time tRLCH RD, CLK tCP/2 15 ns
ALE RD time tLLRL ALE, RD tCP/2 15 ns
A23 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tRHAX
AD15 to AD00
0.8 V
2.4 V 2.4 V
0.8 V Address VIL
VIH VIH
VIL
Read data
tRHDX
tRLDV
tAVDV
CLK
tAVCH
2.4 V
tRLCH
2.4 V
ALE 2.4 V
tLHLL
2.4 V
tRHLH
0.8 V
tLLAX
2.4 V
tAVLL
RD
tLLRL
tRLRH
0.8 V
2.4 V
tAVRL
0.8 V
Document Number: 002-04498 Rev. *A Page 62 of 92
MB90340E Series
11.4.6 Bus Timing (Write)
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Parameter Symbol Pin Condition Value Unit
Min Max
Valid address WR time tAVWL A23 to A16, AD15
to AD00, WR
tCP15 ns
WR pulse width tWLWH WR 3 tCP/2 20 ns
Valid data output WR time tDVWH AD15 to AD00, WR 3 tCP/2 20 ns
WR Data hold time tWHDX AD15 to AD00, WR 15 ns
WR Address valid time tWHAX A23 to A16, WR tCP/2 10 ns
WR ALE time tWHLH WR, ALE tCP/2 15 ns
WR CLK time tWLCH WR, CLK tCP/2 15 ns
CLK
tWLCH
2.4 V
ALE
tWHLH
2.4 V
WR (WRL, WRH)
tWLWH
0.8 V
2.4 V
tAVWL
A23 to A16
0.8 V
2.4 V
2.4 V
0.8 V
tWHAX
AD15 to AD00 2.4 V
0.8 V Address 0.8 V
2.4 V
Write data
tDVWH
0.8 V
2.4 V
tWHDX
Document Number: 002-04498 Rev. *A Page 63 of 92
MB90340E Series
11.4.7 Ready Input Timing
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Note: : If the RDY setup time is insufficient, use the auto-ready function.
Parameter Symbol Pin Test
Condition
Rated Value Unit Remarks
Min Max
RDY setup time tRYHS RDY
45 ns fCP 16 MHz
32 ns fCP 24 MHz
RDY hold time tRYHH RDY 0 ns
CLK 2.4 V
ALE
RD/WR
RDY
When WAIT is not used.
VIH VIH
tRYHH
RDY
When WAIT is used.
tRYHS
VIL
Document Number: 002-04498 Rev. *A Page 64 of 92
MB90340E Series
11.4.8 Hold Timing
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Note: : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
Parameter Symbol Pin Condition Value Unit
Min Max
Pin floating HAK time tXHAL HAK 30 tCP ns
HAK time Pin valid time tHAHV HAK tCP 2 tCP ns
HAK
Each pin
Hi-Z
tHAHV
tXHAL
2.4 V
0.8 V
2.4 V 2.4 V
0.8 V 0.8 V
Document Number: 002-04498 Rev. *A Page 65 of 92
MB90340E Series
11.4.9 LIN-UART0/1/2/3
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Note: AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
Parameter Symbol Pin Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
5 tCP ns
SCK SOT delay time tSLOVI
SCK0 to SCK3,
SOT0 to SOT3 50 50 ns
Valid SIN SCK tIVSHI
SCK0 to SCK3,
SIN0 to SIN3 tCP + 80 ns
SCK Valid SIN hold time tSHIXI
SCK0 to SCK3,
SIN0 to SIN3 0ns
Serial clock “L” pulse width tSHSL SCK0 to SCK3
External shift clock
mode output pins are
CL 80 pF 1 TTL.
3 tCP - tRns
Serial clock “H” pulse width tSLSH SCK0 to SCK3 tCP + 10 ns
SCK SOT delay time tSLOVE
SCK0 to SCK3,
SOT0 to SOT3 2 tCP + 60 ns
Valid SIN SCK tIVSHE
SCK0 to SCK3,
SIN0 to SIN3 30 ns
SCK Valid SIN hold time tSHIXE
SCK0, SCK1,
SIN0 to SIN3 tCP + 30 ns
SCK fall time tFSCK0 to SCK3 10 ns
SCK rise time tRSCK0 to SCK3 10 ns
S
CK0 to SCK3
2.4 V
0.8 V
S
OT0 to SOT3
0.8 V
2.4 V
0.8 V
t
SLOVI
S
IN0 to SIN3
V
IL
V
IH
V
IL
V
IH
t
SCYC
t
IVSHI
t
SHIXI
Internal Shift Clock Mode
Document Number: 002-04498 Rev. *A Page 66 of 92
MB90340E Series
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Note: CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Parameter Symbol Pin Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
5 tCP ns
SCK SOT delay time tSHOVI
SCK0 to SCK3,
SOT0 to SOT3 50 50 ns
Valid SIN SCK tIVSLI
SCK0 to SCK3,
SIN0 to SIN3 tCP + 80 ns
SCK Valid SIN hold time tSLIXI
SCK0 to SCK3,
SIN0 to SIN3 0ns
Serial clock “H” pulse width tSHSL SCK0 to SCK3
External shift clock
mode output pins are
CL 80 pF 1 TTL.
3 tCP - tRns
Serial clock “L” pulse width tSLSH SCK0 to SCK3 tCP + 10 ns
SCK SOT delay time tSHOVE
SCK0 to SCK3,
SOT0 to SOT3 2 tCP + 60 ns
Valid SIN SCK tIVSLE
SCK0 to SCK3,
SIN0 to SIN3 30 ns
SCK Valid SIN hold time tSLIXE
SCK0 to SCK3,
SIN0 to SIN3 tCP + 30 ns
SCK fall time tFSCK0 to SCK3 10 ns
SCK rise time tRSCK0 to SCK3 10 ns
External Shift Clock Mode
SCK0 to SCK3
VIH
VIL
SOT0 to SOT3
0.8 V
2.4 V
tSLOVE
SIN0 to SIN3
VIL
VIH
VIL
VIH
VIH
VIL
tR
tF
tSHSL
tSLSH
tIVSHE tSHIXE
Document Number: 002-04498 Rev. *A Page 67 of 92
MB90340E Series
Internal Shift Clock Mode
SCK0 to SCK3 2.4 V
t
SCYC
0.8 V
SOT0 to SOT3 0.8 V
2.4 V
t
SHOVI
SIN0 to SIN3 V
IL
V
IH
t
IVSLI
V
IL
V
IH
t
SLIXI
External Shift Clock Mode
SCK0 to SCK3
V
IH
V
IL
SOT0 to SOT3
0.8 V
2.4 V
t
SHOVE
SIN0 to SIN3
V
IL
V
IH
t
IVSLE
V
IL
V
IH
t
SLIXE
V
IH
V
IL
t
SHSL
t
R
t
F
t
SLSH
Document Number: 002-04498 Rev. *A Page 68 of 92
MB90340E Series
Bit setting: ESCR:SCES 0, ECCR:SCDE 1
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Note: CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Parameter Symbol Pin Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal clock operation output
pins are
CL 80 pF 1 TTL.
5 tCP ns
SCK SOT delay time tSHOVI SCK0 to SCK3,
SOT0 to SOT3 50 50 ns
Valid SIN SCK tIVSLI SCK0 to SCK3,
SIN0 to SIN3 tCP 80 ns
SCK Valid SIN hold time tSLIXI SCK0 to SCK3,
SIN0 to SIN3 0ns
SOT SCK delay time tSOVLI SCK0 to SCK3,
SOT0 to SOT3 3 tCP 70 ns
S
CK0 to SCK3 2.4 V
t
SCYC
0.8 V
S
OT0 to SOT3 0.8 V
2.4 V
t
SOVLI
S
IN0 to SIN3 V
IL
V
IH
t
IVSLI
V
IL
V
IH
t
SLIXI
0.8 V
t
SHOVI
0.8 V
2.4 V
Document Number: 002-04498 Rev. *A Page 69 of 92
MB90340E Series
Bit setting: ESCR:SCES 1, ECCR:SCDE 1
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Note: CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Parameter Symbol Pin Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3
Internal clock operation
output pins are
CL 80 pF 1 TTL.
5 tCP ns
SCK SOT delay time tSLOVI SCK0 to SCK3,
SOT0 to SOT3 50 50 ns
Valid SIN SCK tIVSHI SCK0 to SCK3,
SIN0 to SIN3 tCP 80 ns
SCK Valid SIN hold time tSHIXI SCK0 to SCK3,
SIN0 to SIN3 0ns
SOT SCK delay time tSOVHI SCK0 to SCK3,
SOT0 to SOT3 3 tCP 70 ns
SCK0 to SCK3
2.4 V
tSCYC
2.4 V
SOT0 to SOT3
0.8 V
2.4 V
tSOVHI
SIN0 to SIN3
VIL
VIH
tIVSHI
VIL
VIH
tSHIXI
0.8 V
tSLOVI
0.8 V
2.4 V
Document Number: 002-04498 Rev. *A Page 70 of 92
MB90340E Series
11.4.10 Trigger Input Timing
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0.0 V)
Parameter Symbol Pin Condition Value Unit
Min Max
Input pulse width tTRGH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG 5 tCP ns
VIL
VIH
tTRGH
VIL
VIH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG
Document Number: 002-04498 Rev. *A Page 71 of 92
MB90340E Series
11.4.11 Timer Related Resource Input Timing
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
11.4.12 Timer Related Resource Output Timing
(TA = –40C to +105C, VCC 5.0 V 10, fCP 24 MHz, VSS = 0.0 V)
Parameter Symbol Pin Condition Value Unit
Min Max
Input pulse width tTIWH TIN0 to TIN3,
IN0 to IN7 4 tCP ns
tTIWL
Parameter Symbol Pin Condition Value Unit
Min Max
CLK TOUT change time tTO
TOT0 to TOT3,
PPG0 to PPGF 30 ns
VIL
VIH
tTIWH
VIL
VIH
tTIWL
TIN0 to TIN3,
IN0 to IN7
CLK 2.4 V
0.8 V
2.4 V
tTO
TOT0 to TOT3,
PPG0 to PPGF
Document Number: 002-04498 Rev. *A Page 72 of 92
MB90340E Series
11.4.13 I2C Timing
(TA –40C to +105C, VCC 5.0 V 10, VSS 0.0 V)
*1:For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2:R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3:The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4:A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be
met.
Parameter Symbol Condition Standard-mode Fast-mode*1
Unit
Min Max Min Max
SCL clock frequency fSCL
R 1.7 k,
C 50 pF*2
0 100 0 400 kHz
Hold time (repeated) START condition
SDA SCL tHDSTA 4.0 0.6 s
“L” width of the SCL clock tLOW 4.7 1.3 s
“H” width of the SCL clock tHIGH 4.0 0.6 s
Set-up time (repeated) START condition
SCL SDA tSUSTA 4.7 0.6 s
Data hold time
SCL SDA tHDDAT 03.45*
300.9*
4s
Data set-up time
SDA SCL tSUDAT 250 100 ns
Set-up time for STOP condition
SCL SDA tSUSTO 4.0 0.6 s
Bus free time between a STOP and START condition tBUS 4.7 1.3 s
SDA
SCL
t
LOW
t
SUDAT
t
HDSTA
t
BUS
t
HDSTA
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
t
HDDAT
t
HIGH
t
SUSTA
t
SUSTO
Document Number: 002-04498 Rev. *A Page 73 of 92
MB90340E Series
11.5 A/D Converter
(TA 40°C to 105°C, 3.0 V AVRH AVRL, VCC AVCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
*: If the A/D convertor is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Note: : The accuracy gets worse as |AVRH AVRL| becomes smaller.
Parameter Symbol Pin Value Unit Remarks
Min Typ Max
Resolution 10 bit
Total e r ror 3.0 LSB
Nonlinearity error 2.5 LSB
Differential
nonlinearity error 1.9 LSB
Zero reading
voltage VOT AN0 to AN23 AVRL
1.5 LSB
AVRL
0.5 LSB
AVRL
2.5 LSB V
Full scale reading
voltage VFST AN0 to AN23 AVRH
3.5 LSB
AVRH
1.5 LSB
AVRH
0.5 LSB V
Compare time 1.0 16500 s4.5 V AVCC 5.5 V
2.0 4.0 V AVCC < 4.5 V
Sampling time 0.5 s4.5 V AVCC 5.5 V
1.2 4.0 V AVCC < 4.5 V
Analog port input
current IAIN AN0 to AN23 0.3 0.3 A
Analog input
voltage range VAIN AN0 to AN23 AVRL AVRH V
Reference
voltage range
AVRH AVRL 2.7 AVCC V
AVRL 0 AVRH 2.7 V
Power supply
current
IAAVCC 3.5 7.5 mA
IAH AVCC 5A*
Reference
voltage current
IRAVRH 600 900 A
IRH AVRH 5A*
Offset between
input channels AN0 to AN23 4LSB
Document Number: 002-04498 Rev. *A Page 74 of 92
MB90340E Series
11.6 Definition of A/D Converter Terms
(Continued)
Resolution : Analog variation that is recognized by the A/D converter.
Non linearity
error
: The deviation between the actual conversion characteristics and a line that joins the
zero-transition line ( “00 0000 0000” “00 0000 0001” ) to the full-scale transition line
( “11 1111 1110” “11 1111 1111” ) .
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Total error : Difference between the actual value and the ideal value. The total error includes zero
transition error, full-scale transition error, and linear error.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVRL AVRH
VNT
1.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Actual conversion
characteristics
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
Digital output
Analog input
Total error
Total error of digital output “N” VNT {1 LSB (N 1) 0.5 LSB}
1 LSB [LSB]
1 LSB (Ideal value) AVRH AVRL
1024 [V]
VOT (Ideal value) AVRL 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VNT : A voltage at which the digital output transitions from (N 1)H to NH.
N : Value of the digital output from the A/D converter
Document Number: 002-04498 Rev. *A Page 75 of 92
MB90340E Series
(Continued)
11.7 Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 k or lower (4.0 V AVCC 5.5 V,
sampling period 0.5 s)
If an external capacitor is used, in consideration of the capacitive voltage dividing effect between the external capacitor and the
internal on-chip capacitor, it is recommended that the capacitance of the external capacitor be several thousand times greater than
the capacitance of the internal capacitor.
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVRL AVRH AVRL AVRH
(N + 1)H
NH
(N − 1)H
(N − 2)H
VOT (actual measurement value)
{1 LSB × (N − 1)
+ VOT }
Actual conversion
characteristics
VFST (actual
measurement
value)
VNT (actual
measurement value)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog inputAnalog input
VNT
(actual measurement value)
V (N + 1) T
(actual measurement
value)
Non linearity error Differential linearity error
Non linearity error of digital output N VNT {1 LSB (N 1) VOT}
1 LSB [LSB]
Differential linearity error of digital output N V (N+1) T VNT
1 LSB 1 LSB [LSB]
VFST VOT
1022 [V]
1 LSB
N : Value of the digital output from the A/D converter
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Document Number: 002-04498 Rev. *A Page 76 of 92
MB90340E Series
If the output impedance of the external circuit is too high, a sampling period for an analog voltage may be insufficient.
C
Comparator
Analog input R
4.5 V AVCC 5.5 V : R := 2.52 k, C := 10.7 pF
4.0 V AVCC < 4.5 V : R := 13.6 k, C := 10.7 pF
A Analog input circuit model
Note: : Use the values in the figure only as a guideline.
Document Number: 002-04498 Rev. *A Page 77 of 92
MB90340E Series
11.8 Flash Memory Program/Erase Characteristics
* : This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to translate high
temperature measurements into normalized value at 85°C) .
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
TA 25°C
VCC 5.0 V
115s
Excludes programming prior to
erasure
Chip erase time 9sExcludes programming prior to
erasure
Word (16-bit width)
programming time 16 3600 sExcept for the over head time of
the system
Program/Erase cycle 10000 cycle
Flash Data Retention Time Average
TA 85°C 20 year *
Document Number: 002-04498 Rev. *A Page 78 of 92
MB90340E Series
12. Example Characteristics
MB90F346E, MB90F346ES, MB90F346CE, MB90F346CES
ICC VCC ICCL VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, stopped
I
CC
(mA)
70
30
10
20
V
CC
(V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL ( A)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
I
CCS
(mA)
35
15
5
10
V
CC
(V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCLS
( A)
50
15
5
10
V
CC
(V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS ( A)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
I
CCT
( A)
20
10
6
8
V
CC
(V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
I
CCH
( A)
10
5
1
2
V
CC
(V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 79 of 92
MB90340E Series
MB90F347E, MB90F347ES, MB90F347CE, MB90F347CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
I
CC
(mA)
70
30
10
20
V
CC
(V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL ( A)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
I
CCS
(mA)
35
15
5
10
V
CC
(V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCLS
( A)
50
15
5
10
V
CC
(V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS ( A)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
I
CCT
( A)
20
10
6
8
V
CC
(V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
I
CCH
( A)
10
5
1
2
V
CC
(V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 80 of 92
MB90340E Series
MB90F349E, MB90F349ES, MB90F349CE, MB90F349CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL (µA)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
ICCS (mA)
35
15
5
10
VCC (V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCLS (µA)
50
15
5
10
VCC (V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS (µA)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
I
CCT
(µA)
20
10
6
8
V
CC
(V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
ICCH (µA)
10
5
1
2
VCC (V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 81 of 92
MB90340E Series
MB90F342E, MB90F342ES, MB90F342CE, MB90F342CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL (µA)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
ICCS (mA)
35
15
5
10
VCC (V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCLS (µA)
50
15
5
10
VCC (V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
ICTS (µA)
400
150
50
100
VCC (V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
I
CCT
(µA)
20
10
6
8
V
CC
(V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
ICCH (µA)
10
5
1
2
VCC (V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 82 of 92
MB90340E Series
MB90F345E, MB90F345ES, MB90F345CE, MB90F345CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCL
( A)
100
30
10
20
V
CC
(V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
I
CCS
(mA)
35
15
5
10
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCLS
( A)
50
15
5
10
V
CC
(V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
I
CTS
( A)
400
150
50
100
V
CC
(V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
ICCT ( A)
20
10
6
8
VCC (V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
I
CTSPLL6
(mA)
10
3
1
2
V
CC
(V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
ICCH ( A)
10
5
1
2
VCC (V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 83 of 92
MB90340E Series
MB90346E, MB90346ES, MB90346CE, MB90346CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL (µA)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
I
CCS
(mA)
35
15
5
10
V
CC
(V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCLS
(µA)
50
15
5
10
V
CC
(V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
I
CTS
(µA)
400
150
50
100
V
CC
(V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
ICCT (µA)
20
10
6
8
VCC (V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
I
CCH
(µA)
10
5
1
2
V
CC
(V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 84 of 92
MB90340E Series
MB90347E, MB90347ES, MB90347CE, MB90347CES
ICC VCC ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICCS VCC ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTS VCC ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
ICTSPLL6 VCC ICCH VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, stopped
ICC (mA)
70
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
ICCL (µA)
100
30
10
20
VCC (V)
0
40
50
60
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
90
70
80
I
CCS
(mA)
35
15
5
10
V
CC
(V)
0
20
25
30
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
I
CCLS
(µA)
50
15
5
10
V
CC
(V)
0
20
30
40
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
45
25
35
I
CTS
(µA)
400
150
50
100
V
CC
(V)
0
200
300
2.5 3.5 4.5 5.5 6.5
f = 2 MHz
350
250
ICCT (µA)
20
10
6
8
VCC (V)
0
12
16
2.5 3.5 4.5 5.5 6.5
f = 8 kHz
18
14
4
2
ICTSPLL6 (mA)
10
3
1
2
VCC (V)
0
4
8
2.5 3.5 4.5 5.5 6.5
f = 24 MHz
9
6
5
7
I
CCH
(µA)
10
5
1
2
V
CC
(V)
0
6
8
2.5 3.5 4.5 5.5 6.5
9
7
3
4
Document Number: 002-04498 Rev. *A Page 85 of 92
MB90340E Series
I/O characteristics
(VCCVOH) IOH VOL IOL
TA 25°C, VCC 4.5 V TA 25°C, VCC 4.5 V
Automotive VIN VCC CMOS VIN VCC
TA 25°C
Other than UART-SIN pin and I2C pin
TA 25°C
TTL VIN VCC CMOS VIN VCC
TA 25°C
UART-SIN pin, I2C pin
TA 25°C
VCC VOH (mV)
800
300
100
200
IOH (mA)
0
400
500
600
024 7 10
700
1365 89
V
OL
(mV)
1000
300
100
200
I
OL
(mA)
0
400
500
600
900
700
800
024 7 101365 89
VIN (V)
5.0
1.5
0.5
1.0
VCC (V)
0.0
2.0
3.0
3.5
2.5
2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0
4.0
4.5 VIHA
VILA
VIN (V)
5.0
2.5
1.5
2.0
VCC (V)
0.0
3.0
4.0
2.5 3.5 4.5 5.5 6.5
4.5
3.5
1.0
0.5
VIHS
VILS
3.0 4.0 5.0 6.0 7.0
VIN (V)
2.5
0.8
0.3
0.5
VCC (V)
0.0
1.0
2.0
2.5 3.5 4.5 5.5 6.5
2.3
1.5
1.3
1.8
3.0 4.0 5.0 6.0 7.0
VIHT
VILT
V
IN
(V)
5.0
2.5
0.5
1.0
V
CC
(V)
0.0
3.0
4.0
4.5
3.5
1.5
2.0
2.5 3.5 4.5 5.5 6.53.0 4.0 5.0 6.0 7.0
V
IHS
V
ILS
Document Number: 002-04498 Rev. *A Page 86 of 92
MB90340E Series
13. Ordering Information
(Continued)
Part number Package Remarks
MB90F342EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F342ESPF
MB90F342CEPF
MB90F342CESPF
MB90F342EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F342ESPMC
MB90F342CEPMC
MB90F342CESPMC
MB90F345EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F345ESPF
MB90F345CEPF
MB90F345CESPF
MB90F345EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F345ESPMC
MB90F345CEPMC
MB90F345CESPMC
MB90F346EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F346ESPF
MB90F346CEPF
MB90F346CESPF
MB90F346EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F346ESPMC
MB90F346CEPMC
MB90F346CESPMC
Document Number: 002-04498 Rev. *A Page 87 of 92
MB90340E Series
(Continued)
Part number Package Remarks
MB90F347EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F347ESPF
MB90F347CEPF
MB90F347CESPF
MB90F347EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F347ESPMC
MB90F347CEPMC
MB90F347CESPMC
MB90F349EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F349ESPF
MB90F349CEPF
MB90F349CESPF
MB90F349EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F349ESPMC
MB90F349CEPMC
MB90F349CESPMC
MB90341EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90341ESPF
MB90341CEPF
MB90341CESPF
MB90341EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90341ESPMC
MB90341CEPMC
MB90341CESPMC
MB90342EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90342ESPF
MB90342CEPF
MB90342CESPF
MB90342EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90342ESPMC
MB90342CEPMC
MB90342CESPMC
Document Number: 002-04498 Rev. *A Page 88 of 92
MB90340E Series
(Continued)
Part number Package Remarks
MB90346EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90346ESPF
MB90346CEPF
MB90346CESPF
MB90346EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90346ESPMC
MB90346CEPMC
MB90346CESPMC
MB90347EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90347ESPF
MB90347CEPF
MB90347CESPF
MB90347EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90347ESPMC
MB90347CEPMC
MB90347CESPMC
MB90348EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90348ESPF
MB90348CEPF
MB90348CESPF
MB90348EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90348ESPMC
MB90348CEPMC
MB90348CESPMC
MB90349EPF
100-pin plastic QFP
(FPT-100P-M06)
MB90349ESPF
MB90349CEPF
MB90349CESPF
MB90349EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90349ESPMC
MB90349CEPMC
MB90349CESPMC
MB90V340E-101CR 299-pin ceramic PGA
(PGA-299C-A01) For evaluation
MB90V340E-102CR
Document Number: 002-04498 Rev. *A Page 89 of 92
MB90340E Series
14. Package Dimensions
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 mm × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm Max
Weight 0.65 g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M20)
(FPT-100P-M20)
C
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003) 0.145±0.055
(.006±.002)
0.08(.003)
"A"
INDEX .059
–.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0°~8
°
0.50±0.20
(.020±.008)
(.024±.006)
0.60±0.15
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Document Number: 002-04498 Rev. *A Page 90 of 92
MB90340E Series
(Continued)
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(FPT-100P-M06)
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7
1 30
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002)
M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00
+0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8
°
*
*
14.00±0.20
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Document Number: 002-04498 Rev. *A Page 91 of 92
MB90340E Series
15. Major Changes
Spansiion Publication Number: DS07-13747-4E
NOTE: Please see “Document History” about later revised information.
Document History
Page Section Change Results
Deleted the part numbers;
MB90F343E(S), MB90F343CE(S)
51
Electrical
Characteristics
Absolute Maximum Ratings
Added “*6” in remark for “L" level maximum output current and “H” level maximum
output current.
Added “*7” in remark for “L" level average output current and “H” level average
output current.
Added “*8” in remark for “L"level average overall output current and “H” level
average overall output current.
52
Added as follows.
“*6:The maximum output current is defined as the peak value of the current of any
one of the corresponding pins.”
“*7:The average output current is defined as the value of the average current
flowing over 100 ms at any one of the corresponding pins.”
“*8:The average total output current is defined as the value of the average current
flowing over 100 ms at all of the corresponding pins.”
Document Title: MB90340E Series F2MC-16LX 16-bit Microcontroller Datasheet
Document Number: 002-04498
Revision ECN Orig. of
Change
Submission
Date Description of Change
** AKIH 08/23/2010 Migrated to Cypress and assigned document number 002-04498.
No change to document contents or format.
*A 5221535 AKIH 05/04/2016 Updated to Cypress template
Document Number: 002-04498 Rev. *A Revised May 4,2016 Page 92 of 92
MB90340E Series
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