REF102
SBVS022B – SEPTEMBER 2000 – REVISED JUNE 2009
FEATURES
●+10V ±0.0025V OUTPUT
●VERY LOW DRIFT: 2.5ppm/°C max
●EXCELLENT STABILITY:
5ppm/1000hr typ
●EXCELLENT LINE REGULATION:
1ppm/V max
●EXCELLENT LOAD REGULATION:
10ppm/mA max
●LOW NOISE: 5µVPP typ, 0.1Hz to 10Hz
●WIDE SUPPLY RANGE: 11.4VDC to 36VDC
●LOW QUIESCENT CURRENT: 1.4mA max
●PACKAGE OPTIONS: PLASTIC DIP, SO-8
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2009, Texas Instruments Incorporated
10V Precision
Voltage Reference
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
APPLICATIONS
●PRECISION-CALIBRATED VOLTAGE
STANDARD
●D/A AND A/D CONVERTER REFERENCE
●PRECISION CURRENT REFERENCE
●ACCURATE COMPARATOR THRESHOLD
REFERENCE
●DIGITAL VOLTMETER
●TEST EQUIPMENT
●PC-BASED INSTRUMENTATION
DESCRIPTION
The REF102 is a precision 10V voltage reference. The drift
is laser-trimmed to 2.5ppm/°C max C-grade over the indus-
trial temperature range. The REF102 achieves its precision
without a heater. This results in low power, fast warm-up,
excellent stability, and low noise. The output voltage is
extremely insensitive to both line and load variations and can
be externally adjusted with minimal effect on drift and
stability. Single-supply operation from 11.4V to 36V and
excellent overall specifications make the REF102 an ideal
choice for demanding instrumentation and system reference
applications.
–
+A
R2R3
R4
R6
R1
R5
1
50kΩ
22kΩ
7kΩ
4kΩ
8kΩ
DZ1
Noise
ReductionCommon
VOUT
V+
Trim
14kΩ
52
6
84
REF102
REF102
www.ti.com
REF102
2SBVS022B
www.ti.com
MAX INITIAL MAX DRIFT PACKAGE PACKAGE
PRODUCT ERROR (mV) (PPM/
°
C) PACKAGE-LEAD DESIGNATOR MARKING
REF102AU ±10 ±10 SO-8 D REF102AU
REF102AP ±10 ±10 DIP-8 P REF102AP
REF102BU ±5±5 SO-8 D REF102BU
REF102BP ±5±5 DIP-8 P REF102BP
REF102CU ±2.5 ±2.5 SO-8 D REF102CU
REF102CP ±2.5 ±2.5 DIP-8 P REF102CP
PIN CONFIGURATIONS
Top View DIP, SO
Input Voltage...................................................................................... +40V
Operating Temperature
P, U ................................................................................. –25°C to +85°C
Storage Temperature Range
P, U ............................................................................... –40°C to +125°C
Short-Circuit Protection to Common or V+ .............................. Continuous
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.
8
7
6
5
1
2
3
4
NC = Not Connected
Noise Reduction
NC
V
OUT
Trim
NC
V+
Com
NC
REF102 3
SBVS022B www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C and VS = +15V power supply, unless otherwise noted.
REF102A REF102B REF102C
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
OUTPUT VOLTAGE
Initial TA = 25°C 9.99 10.01 9.995 10.005 9.9975 10.0025 V
vs Temperature (1) 10 5 2.5 ppm/°C
vs Supply
(Line Regulation) VS = 11.4V to 36V 2 1 1 ppm/V
vs Output Current
(Load Regulation) IL = 0mA to +10mA 20 10 10 ppm/mA
IL = 0mA to –5mA 40 20 20 ppm/mA
vs Time TA = +25°C
M Package 5 ✻✻ppm/1000hr
P, U Packages (2) 20 ✻ppm/1000hr
Trim Range (3) ±3✻✻ %
Capacitive Load, max 1000 ✻✻pF
NOISE 0.1Hz to 10Hz 5 ✻✻µVPP
OUTPUT CURRENT +10, –5✻✻ mA
INPUT VOLTAGE
RANGE +11.4 +36 ✻✻✻ ✻V
QUIESCENT CURRENT IOUT = 0 +1.4 ✻✻mA
WARM-UP TIME (4) To 0.1% 15 ✻✻µs
TEMPERATURE
RANGE
Specification
REF102A, B, C –25 +85 ✻✻✻ ✻°C
✻ Specifications same as REF102A.
NOTES: (1) The
box
method is used to specify output voltage drift vs temperature; see the Discussion of Performance section.
(2) Typically 5ppm/1000hrs after 168hr powered stabilization.
(3) Trimming the offset voltage affects drift slightly. See Installation and Operating Instructions for details.
(4) With noise reduction pin floating. See Typical Characteristics for details.
REF102
4SBVS022B
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +15V, unless otherwise noted.
POWER TURN-ON RESPONSE
VOUT
VIN
Time (5µs/div)
Power Turn-On
POWER TURN-ON RESPONSE with 1µF C
N
V
OUT
V
IN
Time (10ms/div)
Power Turn-On
POWER SUPPLY REJECTION vs FREQUENCY
130
120
110
100
90
80
70
60 1 100 1k 10k
Frequency (Hz)
Power Supply Rejection (dB)
LOAD REGULATION
+1.5
+1.0
+0.5
0
−0.5
−1.0
−1.5 –5 0 +5 +10
Output Current (mA)
Output Voltage Change (mV)
RESPONSE TO THERMAL SHOCK
30 45 60150
+600
+300
0
–300
–600
TA =
+25°C
REF102C Immersed in +85°C Fluorinert Bath
Output Voltage Change (µV)
Time (s)
TA = +85°C
QUIESCENT CURRENT vs TEMPERATURE
1.6
1.4
1.2
1.0
0.8 −50 −25 0 +25 +50 +75 +100 +125
Temperature (°C)
Quiescent Current (mA)
−75
REF102 5
SBVS022B www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +15V, unless otherwise noted.
TYPICAL REF102 REFERENCE NOISE
6
4
2
0
−2
−4
−6
Low Frequency Noise (1s/div)
(See Noise Test Circuit)
Noise Voltage (µV)
–
+
OPA227
DUT
Noise Test Circuit.
100µF
15.8kΩ
20Ω2kΩ
8kΩ
2µF
Oscilloscope
Gain = 100V/V
f = 0.1Hz and 10Hz
−3dB
THEORY OF OPERATION
Refer to the diagram on the first page of this data sheet. The
10V output is derived from a compensated buried zener
diode DZ1, op amp A1, and resistor network R1 – R6.
Approximately 8.2V is applied to the non-inverting input of A1
by DZ1. R1, R2, and R3 are laser-trimmed to produce an exact
10V output. The zener bias current is established from the
regulated output voltage through R4. R5 allows user-trimming
of the output voltage by providing for small external adjust-
ment of the amplifier gain. Because the temperature coeffi-
cient (TCR) of of R5 closely matches the TCR of R1, R2 and
R3 , the voltage trim has minimal effect on the reference drift.
The output voltage noise of the REF102 is dominated by the
noise of the zener diode. A capacitor can be connected
between the Noise Reduction pin and ground to form a low-
pass filter with R6 and roll off the high-frequency noise of the
zener.
DISCUSSION
OF PERFORMANCE
The REF102 is designed for applications requiring a preci-
sion voltage reference where both the initial value at room
temperature and the drift over temperature are of importance
to the user. Two basic methods of specifying voltage refer-
ence drift versus temperature are in common usage in the
industry—the
butterfly method
and the
box method
. The
REF102 is specified by the more commonly-used
box method.
The
box
is formed by the high and low specification tempera-
tures and a diagonal, the slope of which is equal to the
maximum specified drift.
Since the shape of the actual drift curve is not known, the
vertical position of the box is not known, either. It is, however,
bounded by VUPPER BOUND and VLOWER BOUND (see Figure 1).
Figure 1 uses the REF102CU as an example. It has a drift
specification of 2.5ppm/°C maximum and a specification
temperature range of –25°C to +85°C. The
box
height,
V1 to V2, is 2.75mV.
REF102CU V
UPPER BOUND
+10.00275
V1
V
NOMINAL
+10.0000
2.75mV
Worst-case
∆V
OUT
for
REF102CU
V2
+9.99725 REF102CU V
LOWER BOUND
−25 0 +25 +50 +85
Output Voltage (V)
Temperature (°C)
FIGURE 1. REF102CU Output Voltage Drift.
REF102
6SBVS022B
www.ti.com
INSTALLATION AND
OPERATING INSTRUCTIONS
BASIC CIRCUIT CONNECTION
Figure 2 shows the proper connection of the REF102. To
achieve the specified performance, pay careful attention to
layout. A low resistance star configuration will reduce voltage
errors, noise pickup, and noise coupled from the power
supply. Commons should be connected as indicated, being
sure to minimize interconnection resistances.
OPTIONAL OUTPUT VOLTAGE ADJUSTMENT
Optional output voltage adjustment circuits are shown in
Figures 3 and 4. Trimming the output voltage will change the
voltage drift by approximately 0.008ppm/°C per mV of trimmed
voltage. In the circuit in Figure 3, any mismatch in TCR
between the two sections of the potentiometer will also affect
drift, but the effect of the ∆TCR is reduced by a factor of five
by the internal resistor divider. A high quality potentiometer,
with good mechanical stability, such as a cermet, should be
REF102
1µF
Tantalum
+
R
L 1
R
L 2
R
L 3
V+
(1)
2
(2)
(2)
(1)
4
6
NOTES: (1) Lead resistances here of up to a few ohms have
negligible effect on performance. (2) A resistance of 0.1Ω in
series with these leads will cause a 1mV error when the load
current is at its maximum of 10mA. This results in a 0.01%
error of 10V.
FIGURE 2. REF102 Installation.
REF102
1µF
Tantalum
+
V+
2
4
20k
Output
Voltage
Adjust
Minimum range (±300mV) and minimal
degradation of drift.
Ω+10V
5
VTRIM
6
VOUT
FIGURE 3. REF102 Optional Output Voltage Adjust.
REF102
V+
2
4
20k
Output
Voltage
Adjust
Higher resolution, reduced range (typically ±25mV).
Ω+10V
5
VTRIM
6
VOUT
RS
1M Ω
1µF
Tantalum
+
FIGURE 4. REF102 Optional Output Voltage, Fine Adjust.
used. The circuit in Figure 3 has a minimum trim range of
±300mV. The circuit in Figure 4 has less range but provides
higher resolution. The mismatch in TCR between RS and the
internal resistors can introduce some slight drift. This effect
is minimized if RS is kept significantly larger than the 50kΩ
internal resistor. A TCR of 100ppm/°C is normally sufficient.
REF102 7
SBVS022B www.ti.com
OPTIONAL NOISE REDUCTION
The high-frequency noise of the REF102 is dominated by the
zener diode noise. This noise can be greatly reduced by
connecting a capacitor between the Noise Reduction pin and
ground. The capacitor forms a low-pass filter with R6 (refer to
the figure on page 1) and attenuates the high-frequency
noise generated by the zener. Figure 5 shows the effect of a
1µF noise reduction capacitor on the high-frequency noise of
the REF102. R6 is typically 7kΩ so the filter has a –3dB
frequency of about 22Hz. The result is a reduction in noise
from about 800µVPP to under 200µVPP. If further noise
reduction is required, use the circuit in Figure 14.
APPLICATIONS INFORMATION
High accuracy, extremely low drift, outstanding stability, and
low cost make the REF102 an ideal choice for all instrumen-
tation and system reference applications. Figures 6 through
14 show a variety of useful application circuits.
6
b) Precision –10V Reference.
a) Resistor Biased –10V Reference
RSIL
4
REF102
2
−10V Out
See SBVA008 for more detail.
V+ (1.4V to 26V)
1.4mA < < 5.4mA
(5V −IL)
RS
2
6
4
10V
OPA227
R1
2kΩ
C
1000pF
1
−10V Out
−15V
REF102
V+ (1.4V to 26V)
FIGURE 6. –10V Reference Using a) Resistor or b) OPA227.
NO
C
N
C
N
= 1µF
FIGURE 5. Effect of 1µF Noise Reduction Capacitor on
Broadband Noise (f–3dB = 1MHz)
REF102
8SBVS022B
www.ti.com
FIGURE 7. +10V Reference With Output Current Boosted to: a) ±20mA, b) +100mA, and c) IL (TYP) +10mA, –5A.
Ω
–
+
OPA227
6
220
+10V
IL
6+10V
IL
2N2905
6+10V
IL
4
REF102
V+
a) −20mA < IL < +20mA
(OPA227 also improves transient immunity) b) −5mA < IL < +100mA c) IL (MAX) = IL (TYP) +10mA
IL (MIN) = IL (TYP) −5mA
VCC − 10V
IL (TYP)
R1 =
2
4
REF102
V+
2
4
REF102
V+
2
–
+
INA126 V
x100
2
4
6
+15V
−
5V
–15V
357
1/2W
Ω
2
3
OPA227
–
+
357
1/2W
Ω28mA
28.5mA +5V
350 Strain
Gauge Bridge
Ω
5
10
8
R
GOUT
6
REF102
V+
REF102 6
4
2
3
See SBVA007 for more details.
1
25kΩ
25kΩ25kΩ
25kΩINA105
5
6
+10V
Out
−10V
Out
2
–
+
LOAD
I
OUT
Can be connected
to ground or −V .
S
V+
REF102
2
6
4OPA277
R
I
OUT
= , R ≥ 1kΩ
See SBVA001 for more details and I
SINK
Circuit.
10V
R
FIGURE 8. Strain Gauge Conditioner for 350Ω Bridge.
FIGURE 9. ±10V Reference. FIGURE 10. Positive Precision Current Source.
REF102 9
SBVS022B www.ti.com
+30V
6
31.4V to 56V
2
4
6
2
6
2
4
+20V
+10V
REF102
4
REF102
REF102
NOTES: (1) REF102s can be stacked to obtain voltages in multiples of 10V.
(2) The supply voltage should be between 10n + 1.4 and 10n + 26, where
n
is
the number of REF102s. (3) Output current of each REF102 must not exceed
its rated output current of +10, −5mA. This includes the current delivered to
the lower REF102.
–
+
2
4
6+5V
Out
INA105
2
5
13
6
–5V
Out
REF102
V+
–
+
2
4
6+10V
+5V
INA105
5
1
36
2
REF102
V+
Ω
–
+
OPA227
62k
+10V
REF102
(2)
2
R
1k
1
4
V
OUT 2
Ω
REF
V
C
1
1µF
C
2
1µF
R
2
2kΩ
V
REF
=(V
01
+ V
02
… V
OUT
N
)
N
e
N
= 5µV
PP
(f = 0.1Hz to 1MHz)
See SBVA002 for more details.
√N
2
3
Ω
62k
REF102
(1)
2
4
V
OUT 1
Ω
62k
V
OUT N
V+
REF102
(N)
2
4
V+
V+
FIGURE 11. Stacked References.
FIGURE 12. ±5V Reference.
FIGURE 13. +5V and +10V Reference.
FIGURE 14. Precision Voltage Reference with Extremely
Low Noise.
REF102
10 SBVS022B
www.ti.com
Revision History
DATE REVISION PAGE SECTION DESCRIPTION
Absolute Maximum Ratings Deleted lead temperature rating.
Package/Ordering Information Changed Package Ordering Information table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
6/09 B
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
REF102AM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102AP ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102APG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102AU ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102AU/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102AUG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102BM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102BP ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102BPG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102BU ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102BUG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102CM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102CP ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102CPG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
REF102CU ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102CU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102CUG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REF102RM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
REF102SM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jun-2009
Addendum-Page 1
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jun-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
REF102AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
REF102CU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
REF102AU/2K5 SOIC D 8 2500 367.0 367.0 35.0
REF102CU/2K5 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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