ATSAMD21J17A-AFT - Atmel - Datasheet.Directory

32-bit ARM-Based

Microcontrollers

SAM D21E / SAM D21G /SAM D21J Summary

Introduction

The SAM D21 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor,

and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM D21 operate at a

maximum frequency of 48MHz and reach 2.46 CoreMark®/MHz. They are designed for simple and

intuitive migration with identical peripheral modules, hex compatible code, identical linear address map

and pin compatible migration paths between all devices in the product series. All devices include

intelligent and flexible peripherals, Event System for inter-peripheral signaling, and support for capacitive

touch button, slider and wheel user interfaces.

Features

• Processor

– ARM Cortex-M0+ CPU running at up to 48MHz

• Single-cycle hardware multiplier

• Micro Trace Buffer (MTB)

• Memories

– 32/64/128/256KB in-system self-programmable Flash

– 4/8/16/32KB SRAM Memory

• System

– Power-on reset (POR) and brown-out detection (BOD)

– Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)

and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M)

– External Interrupt Controller (EIC)

– 16 external interrupts

– One non-maskable interrupt

– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power

– Idle and standby sleep modes

– SleepWalking peripherals

• Peripherals

– 12-channel Direct Memory Access Controller (DMAC)

– 12-channel Event System

– Up to five 16-bit Timer/Counters (TC), configurable as either:

• One 16-bit TC with two compare/capture channels

• One 8-bit TC with two compare/capture channels

• One 32-bit TC with two compare/capture channels, by using two TCs

– Three 24-bit Timer/Counters for Control (TCC), with extended functions:

This is a summary document. A

complete document is available on

our Web site at www.microchip.com

• Up to four compare channels with optional complementary output

• Generation of synchronized pulse width modulation (PWM) pattern across port pins

• Deterministic fault protection, fast decay and configurable dead-time between

complementary output

• Dithering that increase resolution with up to 5 bit and reduce quantization error

– 32-bit Real Time Counter (RTC) with clock/calendar function

– Watchdog Timer (WDT)

– CRC-32 generator

– One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface

• Embedded host and device function

• Eight endpoints

– Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:

• USART with full-duplex and single-wire half-duplex configuration

• I2C up to 3.4MHz

• SPI

• LIN slave

– One two-channel Inter-IC Sound (I2S) interface

– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels

• Differential and single-ended input

• 1/2x to 16x programmable gain stage

• Automatic offset and gain error compensation

• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution

– 10-bit, 350ksps Digital-to-Analog Converter (DAC)

– Two Analog Comparators (AC) with window compare function

– Peripheral Touch Controller (PTC)

• 256-Channel capacitive touch and proximity sensing

• I/O

– Up to 52 programmable I/O pins

• Drop in compatible with SAM D20

• Packages

– 64-pin TQFP, QFN, UFBGA

– 48-pin TQFP, QFN, WLCSP

– 32-pin TQFP, QFN, WLCSP

• Operating Voltage

– 1.62V – 3.63V

32-bit ARM-Based Microcontrollers

Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description.................................................................................................................5

2. Configuration Summary.............................................................................................6

3. Ordering Information..................................................................................................8

3.1. SAM D21E....................................................................................................................................8

3.2. SAM D21G................................................................................................................................. 11

3.3. SAM D21J.................................................................................................................................. 13

3.4. Device Identification................................................................................................................... 15

4. Block Diagram......................................................................................................... 17

5. Pinout...................................................................................................................... 18

5.1. SAM D21J.................................................................................................................................. 18

5.2. SAM D21G................................................................................................................................. 20

5.3. SAM D21E..................................................................................................................................22

6. Product Mapping..................................................................................................... 24

7. Processor And Architecture.....................................................................................25

7.1. Cortex M0+ Processor............................................................................................................... 25

7.2. Nested Vector Interrupt Controller..............................................................................................26

7.3. Micro Trace Buffer...................................................................................................................... 28

7.4. High-Speed Bus System............................................................................................................ 29

7.5. AHB-APB Bridge........................................................................................................................ 31

7.6. PAC - Peripheral Access Controller........................................................................................... 32

8. Packaging Information.............................................................................................43

8.1. Thermal Considerations............................................................................................................. 43

8.2. Package Drawings..................................................................................................................... 44

8.3. Soldering Profile......................................................................................................................... 55

The Microchip Web Site................................................................................................ 56

Customer Change Notification Service..........................................................................56

Customer Support......................................................................................................... 56

Product Identification System........................................................................................56

Microchip Devices Code Protection Feature................................................................. 57

Legal Notice...................................................................................................................57

Trademarks................................................................................................................... 58

Quality Management System Certified by DNV.............................................................58

Worldwide Sales and Service........................................................................................59

32-bit ARM-Based Microcontrollers

1. Description

The SAM D21 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor,

and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM D21 operate at a

maximum frequency of 48MHz and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive

migration with identical peripheral modules, hex compatible code, identical linear address map and pin

compatible migration paths between all devices in the product series. All devices include intelligent and

flexible peripherals, Event System for inter-peripheral signaling, and support for capacitive touch button,

slider and wheel user interfaces.

The SAM D21 provide the following features: In-system programmable Flash, twelve-channel direct

memory access (DMA) controller, 12 channel Event System, programmable interrupt controller, up to 52

programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and

three 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency

and waveform generation, accurate program execution timing or input capture with time and frequency

measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded

to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and

other control applications. The series provide one full-speed USB 2.0 embedded host and device

interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an

USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; two-channel I2S interface; up to

twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation

supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode,

Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels and proximity sensing;

programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug

(SWD) program and debug interface.

All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a

source for the system clock. Different clock domains can be independently configured to run at different

frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus

maintaining a high CPU frequency while reducing power consumption.

The SAM D21 have two software-selectable sleep modes, idle and standby. In idle mode the CPU is

stopped while all other functions can be kept running. In standby all clocks and functions are stopped

expect those selected to continue running. The device supports SleepWalking. This feature allows the

peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up

only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports

synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in

standby mode.

The Flash program memory can be reprogrammed in-system through the SWD interface. The same

interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the

device can use any communication interface to download and upgrade the application program in the

Flash memory.

The SAM D21 microcontrollers are supported with a full suite of program and system development tools,

including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation

kits.

32-bit ARM-Based Microcontrollers

2. Configuration Summary

SAM D21J SAM D21G SAM D21E

Pins 64 48 (45 for WLCSP) 32 (35 for WLCSP)

General Purpose I/O-pins

(GPIOs)

52 38 26

Flash 256/128/64/32KB 256/128/64/32KB 256/128/64/32KB

SRAM 32/16/8/4KB 32/16/8/4KB 32/16/8/4KB

Timer Counter (TC)

instances

5 3 3

Waveform output channels

per TC instance

2 2 2

Timer Counter for Control

(TCC) instances

3 3 3

Waveform output channels

per TCC

8/4/2 8/4/2 6/4/2

DMA channels 12 12 12

USB interface 1 1 1

Serial Communication

Interface (SERCOM)

instances

6 6 4

Inter-IC Sound (I2S)

interface

1 1 1

Analog-to-Digital Converter

(ADC) channels

20 14 10

Analog Comparators (AC) 2 2 2

Digital-to-Analog Converter

(DAC) channels

1 1 1

Real-Time Counter (RTC) Yes Yes Yes

RTC alarms 1 1 1

RTC compare values One 32-bit value or

two 16-bit values

One 32-bit value or

two 16-bit values

One 32-bit value or

two 16-bit values

External Interrupt lines 16 16 16

Peripheral Touch Controller

(PTC) X and Y lines

16x16 12x10 10x6

Maximum CPU frequency 48MHz

32-bit ARM-Based Microcontrollers

SAM D21J SAM D21G SAM D21E

Packages QFN

TQFP

UFBGA

QFN

TQFP

WLCSP

QFN

TQFP

WLCSP

Oscillators 32.768kHz crystal oscillator (XOSC32K)

0.4-32MHz crystal oscillator (XOSC)

32.768kHz internal oscillator (OSC32K)

32KHz ultra-low-power internal oscillator (OSCULP32K)

8MHz high-accuracy internal oscillator (OSC8M)

48MHz Digital Frequency Locked Loop (DFLL48M)

96MHz Fractional Digital Phased Locked Loop (FDPLL96M)

Event System channels 12 12 12

SW Debug Interface Yes Yes Yes

Watchdog Timer (WDT) Yes Yes Yes

32-bit ARM-Based Microcontrollers

3. Ordering Information

SAMD 21 E 15 A - M U T

Product Family

SAMD = General Purpose Microcontroller

21 = Cortex M0 + CPU, Basic Feature Set

E = 32 Pins (35 Pins for WLCSP)

G = 48 Pins (45 Pins for WLCSP)

J = 64 Pins

No character = Tray (Default)

T = Tape and Reel

U = -40 - 85OC Matte Sn Plating

F = -40 - 125OC Matte Sn Plating

A = TQFP

M = QFN

U = WLCSP

C = UFBGA

+ DMA + USB

Product Series

Flash Memory Density

Device Variant

A = Default Variant

B = Added RWW support for 32KB and 64KB memory options

C = Silicon revision F for WLCSP35 package option.

Pin Count

Package Carrier

Package Grade

18 = 256KB

17 = 128KB

16 = 64KB

15 = 32KB

Package Type

3.1 SAM D21E

Table 3-1. Device Variant A

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21E15A-AU 32K 4K TQFP32 Tray

ATSAMD21E15A-AUT Tape & Reel

ATSAMD21E15A-AF Tray

ATSAMD21E15A-AFT Tape & Reel

ATSAMD21E15A-MU QFN32 Tray

ATSAMD21E15A-MUT Tape & Reel

ATSAMD21E15A-MF Tray

ATSAMD21E15A-MFT Tape & Reel

32-bit ARM-Based Microcontrollers

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21E16A-AU 64K 8K TQFP32 Tray

ATSAMD21E16A-AUT Tape & Reel

ATSAMD21E16A-AF Tray

ATSAMD21E16A-AFT Tape & Reel

ATSAMD21E16A-MU QFN32 Tray

ATSAMD21E16A-MUT Tape & Reel

ATSAMD21E16A-MF Tray

ATSAMD21E16A-MFT Tape & Reel

ATSAMD21E17A-AU 128K 16K TQFP32 Tray

ATSAMD21E17A-AUT Tape & Reel

ATSAMD21E17A-AF Tray

ATSAMD21E17A-AFT Tape & Reel

ATSAMD21E17A-MU QFN32 Tray

ATSAMD21E17A-MUT Tape & Reel

ATSAMD21E17A-MF Tray

ATSAMD21E17A-MFT Tape & Reel

ATSAMD21E18A-AU 256K 32K TQFP32 Tray

ATSAMD21E18A-AUT Tape & Reel

ATSAMD21E18A-AF Tray

ATSAMD21E18A-AFT Tape & Reel

ATSAMD21E18A-MU QFN32 Tray

ATSAMD21E18A-MUT Tape & Reel

ATSAMD21E18A-MF Tray

ATSAMD21E18A-MFT Tape & Reel

32-bit ARM-Based Microcontrollers

Table 3-2. Device Variant B

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21E15B-AU 32K 4K TQFP32 Tray

ATSAMD21E15B-AUT Tape & Reel

ATSAMD21E15B-AF Tray

ATSAMD21E15B-AFT Tape & Reel

ATSAMD21E15B-MU QFN32 Tray

ATSAMD21E15B-MUT Tape & Reel

ATSAMD21E15B-MF Tray

ATSAMD21E15B-MFT Tape & Reel

ATSAMD21E15B-UUT WLCSP35 (GJR) Tape & Reel

ATSAMD21E16B-AU 64K 8K TQFP32 Tray

ATSAMD21E16B-AUT Tape & Reel

ATSAMD21E16B-AF Tray

ATSAMD21E16B-AFT Tape & Reel

ATSAMD21E16B-MU QFN32 Tray

ATSAMD21E16B-MUT Tape & Reel

ATSAMD21E16B-MF Tray

ATSAMD21E16B-MFT Tape & Reel

ATSAMD21E16B-UUT 64K 8K WLCSP35 (GJR) Tape & Reel

Table 3-3. Device Variant C

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21E15C-UUT 32K 4K WLCSP35 (GJS) Tape & Reel

ATSAMD21E16C-UUT 64K 8K WLCSP35 (GJS) Tape & Reel

32-bit ARM-Based Microcontrollers

3.2 SAM D21G

Table 3-4. Device Variant A

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21G15A-AU 32K 4K TQFP48 Tray

ATSAMD21G15A-AUT Tape & Reel

ATSAMD21G15A-AF Tray

ATSAMD21G15A-AFT Tape & Reel

ATSAMD21G15A-MU QFN48 Tray

ATSAMD21G15A-MUT Tape & Reel

ATSAMD21G15A-MF Tray

ATSAMD21G15A-MFT Tape & Reel

ATSAMD21G16A-AU 64K 8K TQFP48 Tray

ATSAMD21G16A-AUT Tape & Reel

ATSAMD21G16A-AF Tray

ATSAMD21G16A-AFT Tape & Reel

ATSAMD21G16A-MU QFN48 Tray

ATSAMD21G16A-MUT Tape & Reel

ATSAMD21G16A-MF Tray

ATSAMD21G16A-MFT Tape & Reel

ATSAMD21G17A-AU 128K 16K TQFP48 Tray

ATSAMD21G17A-AUT Tape & Reel

ATSAMD21G17A-AF Tray

ATSAMD21G17A-AFT Tape & Reel

ATSAMD21G17A-MU QFN48 Tray

ATSAMD21G17A-MUT Tape & Reel

ATSAMD21G17A-MF Tray

ATSAMD21G17A-MFT Tape & Reel

ATSAMD21G17A-UUT WLCSP45 Tape & Reel

32-bit ARM-Based Microcontrollers

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21G18A-AU 256K 32K TQFP48 Tray

ATSAMD21G18A-AUT Tape & Reel

ATSAMD21G18A-AF Tray

ATSAMD21G18A-AFT Tape & Reel

ATSAMD21G18A-MU QFN48 Tray

ATSAMD21G18A-MUT Tape & Reel

ATSAMD21G18A-MF Tray

ATSAMD21G18A-MFT Tape & Reel

ATSAMD21G18A-UUT WLCSP45 Tape & Reel

Table 3-5. Device Variant B

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21G15B-AU 32K 4K TQFP48 Tray

ATSAMD21G15B-AUT Tape & Reel

ATSAMD21G15B-AF Tray

ATSAMD21G15B-AFT Tape & Reel

ATSAMD21G15B-MU QFN48 Tray

ATSAMD21G15B-MUT Tape & Reel

ATSAMD21G15B-MF Tray

ATSAMD21G15B-MFT Tape & Reel

ATSAMD21G16B-AU 64K 8K TQFP48 Tray

ATSAMD21G16B-AUT Tape & Reel

ATSAMD21G16B-AF Tray

ATSAMD21G16B-AFT Tape & Reel

ATSAMD21G16B-MU QFN48 Tray

ATSAMD21G16B-MUT Tape & Reel

ATSAMD21G16B-MF Tray

ATSAMD21G16B-MFT Tape & Reel

32-bit ARM-Based Microcontrollers

3.3 SAM D21J

Table 3-6. Device Variant A

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21J15A-AU 32K 4K TQFP64 Tray

ATSAMD21J15A-AUT Tape & Reel

ATSAMD21J15A-AF Tray

ATSAMD21J15A-AFT Tape & Reel

ATSAMD21J15A-MU QFN64 Tray

ATSAMD21J15A-MUT Tape & Reel

ATSAMD21J15A-MF Tray

ATSAMD21J15A-MFT Tape & Reel

ATSAMD21J16A-AU 64K 8K TQFP64 Tray

ATSAMD21J16A-AUT Tape & Reel

ATSAMD21J16A-AF Tray

ATSAMD21J16A-AFT Tape & Reel

ATSAMD21J16A-MU QFN64 Tray

ATSAMD21J16A-MUT Tape & Reel

ATSAMD21J16A-MF Tray

ATSAMD21J16A-MFT Tape & Reel

ATSAMD21J16A-CU UFBGA64 Tray

ATSAMD21J16A-CUT Tape & Reel

ATSAMD21J17A-AU 128K 16K TQFP64 Tray

ATSAMD21J17A-AUT Tape & Reel

ATSAMD21J17A-AF Tray

ATSAMD21J17A-AFT Tape & Reel

ATSAMD21J17A-MU QFN64 Tray

ATSAMD21J17A-MUT Tape & Reel

ATSAMD21J17A-MF Tray

ATSAMD21J17A-MFT Tape & Reel

ATSAMD21J17A-CU UFBGA64 Tray

ATSAMD21J17A-CUT Tape & Reel

32-bit ARM-Based Microcontrollers

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21J18A-AU 256K 32K TQFP64 Tray

ATSAMD21J18A-AUT Tape & Reel

ATSAMD21J18A-AF Tray

ATSAMD21J18A-AFT Tape & Reel

ATSAMD21J18A-MU QFN64 Tray

ATSAMD21J18A-MUT Tape & Reel

ATSAMD21J18A-MF Tray

ATSAMD21J18A-MFT Tape & Reel

ATSAMD21J18A-CU UFBGA64 Tray

ATSAMD21J18A-CUT Tape & Reel

Table 3-7. Device Variant B

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

ATSAMD21J15B-AU 32K 4K TQFP64 Tray

ATSAMD21J15B-AUT Tape & Reel

ATSAMD21J15B-AF Tray

ATSAMD21J15B-AFT Tape & Reel

ATSAMD21J15B-MU QFN64 Tray

ATSAMD21J15B-MUT Tape & Reel

ATSAMD21J15B-MF Tray

ATSAMD21J15B-MFT Tape & Reel

ATSAMD21J16B-AU 64K 8K TQFP64 Tray

ATSAMD21J16B-AUT Tape & Reel

ATSAMD21J16B-AF Tray

ATSAMD21J16B-AFT Tape & Reel

ATSAMD21J16B-MU QFN64 Tray

ATSAMD21J16B-MUT Tape & Reel

ATSAMD21J16B-MF Tray

ATSAMD21J16B-MFT Tape & Reel

ATSAMD21J16B-CU UFBGA64 Tray

ATSAMD21J16B-CUT Tape & Reel

32-bit ARM-Based Microcontrollers

3.4 Device Identification

The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification

value of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the

device selection ('xx').

Table 3-8. SAM D21 Device Identification Values

Device Variant DID.DEVSEL Device ID (DID)

SAMD21J18A 0x00 0x10010000

SAMD21J17A 0x01 0x10010001

SAMD21J16A 0x02 0x10010002

SAMD21J15A 0x03 0x10010003

Reserved 0x04

SAMD21G18A 0x05 0x10010005

SAMD21G17A 0x06 0x10010006

SAMD21G16A 0x07 0x10010007

SAMD21G15A 0x08 0x10010008

Reserved 0x09

SAMD21E18A 0x0A 0x1001000A

SAMD21E17A 0x0B 0x1001000B

SAMD21E16A 0x0C 0x1001000C

SAMD21E15A 0x0D 0x1001000D

Reserved 0x0E

SAMD21G18A (WLCSP) 0x0F 0x1001000F

SAMD21G17A (WLCSP) 0x10 0x10010010

Reserved 0x11 - 0x1F

SAMD21J16B 0x20 0x10011420

SAMD21J15B 0x21 0x10011421

Reserved 0x22

SAMD21G16B 0x23 0x10011423

SAMD21G15B 0x24 0x10011424

Reserved 0x25

SAMD21E16B 0x26 0x10011426

SAMD21E15B 0x27 0x10011427

Reserved 0x28-0x54

32-bit ARM-Based Microcontrollers

Device Variant DID.DEVSEL Device ID (DID)

SAMD21E16B (WLCSP) 0x55 0x10011455

SAMD21E15B (WLCSP) 0x56 0x10011456

Reserved 0x57 - 0x61

SAMD21E16C (WLCSP) 0x62 0x10011562

SAMD21E15C (WLCSP) 0x63 0x10011563

Reserved 0x64-0xFF

Note: The device variant (last letter of the ordering number) is independent of the die revision

(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks

evolution of the die. The device variant denotes functional differences, whereas the die revision marks

evolution of the die.

32-bit ARM-Based Microcontrollers

4. Block Diagram

6 x SERCOM

8 x Timer Counter

REAL TIME

COUNTER

AHB-APB

BRIDGE C

HIGH SPEED

BUS MATRIX

PORT

WATCHDOG

TIMER

SERIAL

WIRE

SWDIO

CORTEX-M0+

PROCESSOR

Fmax 48 MHz

SWCLK

DEVICE

SERVICE

UNIT

AHB-APB

BRIDGE A

20-CHANNEL

12-bit ADC 350KSPS

AIN[19..0]

VREFA

AIN[3..0]

SRAM

CONTROLLER

32/16/8/4KB

RAM

RESET

CONTROLLER

SLEEP

CONTROLLER

CLOCK

CONTROLLER

POWER MANAGER

RESETN

5 x TIMER / COUNTER

EVENT SYSTEM

6 x SERCOM

2 ANALOG

COMPARATORS

SYSTEM CONTROLLER

XOUT

XIN

XOUT32

XIN32

OSCULP32K

OSC32K

OSC8M

DFLL48M

BOD33

XOSC32K

XOSC

VREF

X[15..0]

Y[15..0]

PERIPHERAL

TOUCH

CONTROLLER

PERIPHERAL

ACCESS CONTROLLER

AHB-APB

BRIDGE B

VREFA

VOUT

10-bit DAC

EXTERNAL INTERRUPT

CONTROLLER

PERIPHERAL

ACCESS CONTROLLER

PERIPHERAL

ACCESS CONTROLLER

EXTINT[15..0]

NMI

GCLK_IO[7..0]

PAD0

WO1

PAD1

PAD2

PAD3

WO0

VREFB

256/128/64/32KB

NVM

CONTROLLER

Cache

DMA

USB FS

DEVICE

MINI-HOST

3x TIMER / COUNTER

FOR CONTROL

WOn

IOBUS

FDPLL96M

DMA

MCK[1..0]

SCK[1..0]

INTER-IC

SOUND

CONTROLLER

SD[1..0]

FS[1..0]

DMA

MICRO

TRACE BUFFER

SOF 1KHZ

WO0

WO1

(2)

GENERIC CLOCK

CONTROLLER

CMP[1..0]

1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC

signals and ADC signals. Refer to the Configuration Summary for details.

2. The three TCC instances have different configurations, including the number of Waveform Output

(WO) lines. Refer to the TCC Configuration for details.

32-bit ARM-Based Microcontrollers

5. Pinout

5.1 SAM D21J

5.1.1 QFN64 / TQFP64

PA00 1

PA01 2

PA02 3

PA03 4

PB04 5

PB05 6

GNDANA 7

VDDANA 8

PB06 9

PB07 10

PB08 11

PB09 12

PA04 13

PA05 14

PA06 15

PA07 16

PA08 17

PA09 18

PA10 19

PA11 20

VDDIO 21

GND 22

PB10 23

PB11 24

PB12 25

PB13 26

PB14 27

PB15 28

PA12 29

PA13 30

PA14 31

PA15 32

VDDIO48

GND47

PA2546

PA2445

PA2344

PA2243

PA2142

PA2041

PB1740

PB1639

PA1938

PA1837

PA1736

PA1635

VDDIO34

GND33

PB22

PB23

PA27

RESET

PA28

GND

VDDCORE

VDDIN

PA30

PA31

PB30

PB31

PB0061

PB0162

PB02

PB03

DIGITAL PIN

ANALOG PIN

OSCILLATOR

GROUND

INPUT SUPPLY

REGULATED OUTPUT SUPPLY

RESET PIN

32-bit ARM-Based Microcontrollers

5.1.2 UFBGA64

32-bit ARM-Based Microcontrollers

5.2 SAM D21G

5.2.1 QFN48 / TQFP48

PA21

PA00 1

PA01 2

PA02 3

PA03 4

GNDANA 5

VDDANA 6

PB08 7

PB09 8

PA04 9

PA05 10

PA06 11

PA07 12

PA08 13

PA09 14

PA10 15

PA11 16

VDDIO 17

GND 18

PB10 19

PB11 20

PA12 21

PA13 22

PA14 23

PA15 24

VDDIO36

GND35

PA2534

PA2433

PA2332

PA2231

PA2029

PA1928

PA1827

PA1726

PA1625

PB22

PB2338

PA27

RESET

PA28

GND

VDDCORE

VDDIN

PA30

PA31

PB02

PB03

DIGITAL PIN

ANALOG PIN

OSCILLATOR

GROUND

INPUT SUPPLY

REGULATED OUTPUT SUPPLY

RESET PIN

32-bit ARM-Based Microcontrollers

5.2.2 WLCSP45

32-bit ARM-Based Microcontrollers

5.3 SAM D21E

5.3.1 QFN32 / TQFP32

PA00 1

PA01 2

PA02 3

PA03 4

PA04 5

PA05 6

PA06 7

PA07 8

VDDANA 9

GND 10

PA08 11

PA09 12

PA10 13

PA11 14

PA14 15

PA15 16

PA25

PA24

PA23

PA22

PA19

PA18

PA17

PA16

PA27

RESET

PA28

GND

VDDCORE

VDDIN

PA30

PA31

DIGITAL PIN

ANALOG PIN

OSCILLATOR

GROUND

INPUT SUPPLY

REGULATED OUTPUT SUPPLY

RESET PIN

32-bit ARM-Based Microcontrollers

5.3.2 WLCSP35

PA00

PA01

GNDANA

VDDANA

PA06

VDDIO

PA15

PA18

PA19

PA23

PA24

PA25

PA14

PA16

PA17

PA22

PA27

RESET

PA03

PA05

PA10

PA08

VDDIN

VDDCORE

PA02

PA04

PA07

PA31

PA30

PA11

PA09

PA28

GND

A B C D E F

32-bit ARM-Based Microcontrollers

6. Product Mapping

Figure 6-1. SAM D21 Product Mapping

Code

SRAM

Undefined

Peripherals

Reserved

Undefined

Global Memory Space

0x00000000

0x20000000

0x20008000

0x40000000

0x43000000

0x60000000

Internal SRAM

SRAM

AHB-APB

Bridge A

AHB-APB

Bridge B

AHB-APB

Bridge C

AHB-APB

Internal Flash

Reserved

Code

0x00000000

0x00040000

0x1FFFFFFF

0x20000000

0x20007FFF

0x40000000

0x41000000

0x42000000

0x42FFFFFF

Reserved

PAC0

SYSCTRL

GCLK

WDT

RTC

EIC

AHB-APB Bridge A

0x40000000

0x40000400

0x40000800

0x40000C00

0x40001000

0x40001400

0x40001800

0x40FFFFFF

0x40001C00

AHB-APB Bridge B

Reserved

PAC1

DSU

NVMCTRL

PORT

0x41000000

0x41002000

0x41004000

0x41004400

0x41FFFFFF

0x41007000

SERCOM5

PAC2

EVSYS

SERCOM0

SERCOM1

SERCOM2

SERCOM3

SERCOM4

AHB-APB Bridge C

TC7

TCC0

TCC1

TCC2

TC3

TC4

TC5

TC6

ADC

0x42000000

0x42000400

0x42000800

0x42000C00

0x42001000

0x42001400

0x42001800

0x42002000

0x42001C00

0x42003000

0x42003400

0x42003800

0x42003C00

0x42004000

0x42004400

0x42004800

Reserved

0x42FFFFFF

0x60000200

0xFFFFFFFF

Reserved

System

0xE0000000

DAC

0x42004C00

0x42002400

0x42002800

0x42002C00

PTC

0x42005400

0x42005000

I2S

DMAC

USB

MTB

0x41004800

0x41005000

0x41006000

0xE0000000

0xE000E000

0xE000F000

0xE00FF000

0xE0100000

0xFFFFFFFF

System

Reserved

SCS

Reserved

ROMTable

Reserved

Internal Flash

0x00000000

0x00010000

0x1FFFFFFF

Internal

RWW section

Device Variant A Device Variant B

This figure represents the full configuration of the SAM D21 with maximum flash and SRAM capabilities

and a full set of peripherals. Refer to the Configuration Summary for details.

32-bit ARM-Based Microcontrollers

7. Processor And Architecture

7.1 Cortex M0+ Processor

The SAM D21 implements the ARM® Cortex®-M0+ processor, based on the ARMv6 Architecture and

Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0

core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision

r0p1. For more information refer to http://www.arm.com.

7.1.1 Cortex M0+ Configuration

Table 7-1. Cortex M0+ Configuration

Features Configurable option Device configuration

Interrupts External interrupts 0-32 28

Data endianness Little-endian or big-endian Little-endian

SysTick timer Present or absent Present

Number of watchpoint comparators 0, 1, 2 2

Number of breakpoint comparators 0, 1, 2, 3, 4 4

Halting debug support Present or absent Present

Multiplier Fast or small Fast (single cycle)

Single-cycle I/O port Present or absent Present

Wake-up interrupt controller Supported or not supported Not supported

Vector Table Offset Register Present or absent Present

Unprivileged/Privileged support Present or absent Absent(1)

Memory Protection Unit Not present or 8-region Not present

Reset all registers Present or absent Absent

Instruction fetch width 16-bit only or mostly 32-bit 32-bit

Note:

1. All software run in privileged mode only.

The ARM Cortex-M0+ core has two bus interfaces:

• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all

system memory, which includes flash and RAM.

• Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.

7.1.2 Cortex-M0+ Peripherals

• System Control Space (SCS)

– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+

Technical Reference Manual for details (www.arm.com).

• System Timer (SysTick)

32-bit ARM-Based Microcontrollers

– The System Timer is a 24-bit timer that extends the functionality of both the processor and the

NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).

• Nested Vectored Interrupt Controller (NVIC)

– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.

Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core

are closely coupled, providing low latency interrupt processing and efficient processing of late

arriving interrupts. Refer to Nested Vector Interrupt Controller and the Cortex-M0+ Technical

Reference Manual for details (www.arm.com).

• System Control Block (SCB)

– The System Control Block provides system implementation information, and system control.

This includes configuration, control, and reporting of the system exceptions. Refer to the

Cortex-M0+ Devices Generic User Guide for details (www.arm.com).

• Micro Trace Buffer (MTB)

– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-

M0+ processor. Refer to section Micro Trace Buffer and the CoreSight MTB-M0+ Technical

Reference Manual for details (www.arm.com).

7.1.3 Cortex-M0+ Address Map

Table 7-2. Cortex-M0+ Address Map

Address Peripheral

0xE000E000 System Control Space (SCS)

0xE000E010 System Timer (SysTick)

0xE000E100 Nested Vectored Interrupt Controller (NVIC)

0xE000ED00 System Control Block (SCB)

0x41006000 (see also Product Mapping) Micro Trace Buffer (MTB)

7.1.4 I/O Interface

7.1.4.1 Overview

Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently,

the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single

cycle I/O accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information.

7.1.4.2 Description

Direct access to PORT registers.

7.2 Nested Vector Interrupt Controller

7.2.1 Overview

The Nested Vectored Interrupt Controller (NVIC) in the SAM D21 supports 32 interrupt lines with four

different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual

(www.arm.com).

7.2.2 Interrupt Line Mapping

Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each

peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear

32-bit ARM-Based Microcontrollers

(INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the

peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s

Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the

peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the

peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests

for one peripheral are ORed together on system level, generating one interrupt request for each

peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt

pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it

must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC

interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

Table 7-3. Interrupt Line Mapping

Peripheral Source NVIC Line

EIC NMI – External Interrupt Controller NMI

PM – Power Manager 0

SYSCTRL – System Control 1

WDT – Watchdog Timer 2

RTC – Real Time Counter 3

EIC – External Interrupt Controller 4

NVMCTRL – Non-Volatile Memory Controller 5

DMAC - Direct Memory Access Controller 6

USB - Universal Serial Bus 7

EVSYS – Event System 8

SERCOM0 – Serial Communication Interface 0 9

SERCOM1 – Serial Communication Interface 1 10

SERCOM2 – Serial Communication Interface 2 11

SERCOM3 – Serial Communication Interface 3 12

SERCOM4 – Serial Communication Interface 4 13

SERCOM5 – Serial Communication Interface 5 14

TCC0 – Timer Counter for Control 0 15

TCC1 – Timer Counter for Control 1 16

TCC2 – Timer Counter for Control 2 17

TC3 – Timer Counter 3 18

TC4 – Timer Counter 4 19

TC5 – Timer Counter 5 20

TC6 – Timer Counter 6 21

TC7 – Timer Counter 7 22

ADC – Analog-to-Digital Converter 23

32-bit ARM-Based Microcontrollers

Peripheral Source NVIC Line

AC – Analog Comparator 24

DAC – Digital-to-Analog Converter 25

PTC – Peripheral Touch Controller 26

I2S - Inter IC Sound 27

7.3 Micro Trace Buffer

7.3.1 Features

• Program flow tracing for the Cortex-M0+ processor

• MTB SRAM can be used for both trace and general purpose storage by the processor

• The position and size of the trace buffer in SRAM is configurable by software

• CoreSight compliant

7.3.2 Overview

When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over

the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+.

This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the

trace information using the Debug Access Port to read the trace information from the SRAM. The

debugger can then reconstruct the program flow from this information.

The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the

SRAM. The MTB ensures that trace write accesses have priority over processor accesses.

The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the

processor PC value changes non-sequentially. A non-sequential PC change can occur during branch

instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more

details on the MTB execution trace packet format.

Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various

ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical

Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s

MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a

specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the

watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around

overwriting previous trace packets.

The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM

Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-

M0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the

trace features:

• POSITION: Contains the trace write pointer and the wrap bit,

• MASTER: Contains the main trace enable bit and other trace control fields,

• FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,

• BASE: Indicates where the SRAM is located in the processor memory map. This register is

provided to enable auto discovery of the MTB SRAM location, by a debug agent.

See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.

32-bit ARM-Based Microcontrollers

7.4 High-Speed Bus System

7.4.1 Features

High-Speed Bus Matrix has the following features:

• Symmetric crossbar bus switch implementation

• Allows concurrent accesses from different masters to different slaves

• 32-bit data bus

• Operation at a one-to-one clock frequency with the bus masters

7.4.2 Configuration

CM0+ 0

DSU 1

High-Speed Bus SLAVES

Internal Flash

AHB-APB Bridge A

AHB-APB Bridge B

AHB-APB Bridge C

MTB

Multi-Slave

MASTERS

USB

DMAC WB

DMAC Fetch

CM0+

DMAC Data

DSU

SRAM

DSU 1

MTB

USB

DMAC WB

DMAC Fetch

Priviledged SRAM-access

MASTERS

DSU 2

DMAC Data

0123 65

SLAVE ID

SRAM PORT ID

MASTER ID

Table 7-4. Bus Matrix Masters

Bus Matrix Masters Master ID

CM0+ - Cortex M0+ Processor 0

DSU - Device Service Unit 1

32-bit ARM-Based Microcontrollers

Table 7-5. Bus Matrix Slaves

Bus Matrix Slaves Slave ID

Internal Flash Memory 0

AHB-APB Bridge A 1

AHB-APB Bridge B 2

AHB-APB Bridge C 3

SRAM Port 4 - CM0+ Access 4

SRAM Port 5 - DMAC Data Access 5

SRAM Port 6 - DSU Access 6

Table 7-6. SRAM Port Connection

SRAM Port Connection Port ID Connection Type

MTB - Micro Trace Buffer 0 Direct

USB - Universal Serial Bus 1 Direct

DMAC - Direct Memory Access Controller - Write-Back Access 2 Direct

DMAC - Direct Memory Access Controller - Fetch Access 3 Direct

CM0+ - Cortex M0+ Processor 4 Bus Matrix

DMAC - Direct Memory Access Controller - Data Access 5 Bus Matrix

DSU - Device Service Unit 6 Bus Matrix

7.4.3 SRAM Quality of Service

To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different

masters can be configured to have a given priority for different type of access.

The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any

access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit

values for the QoS level configuration is shown in Table. Quality of Service.

Table 7-7. Quality of Service

Value Name Description

00 DISABLE Background (no sensitive operation)

01 LOW Sensitive Bandwidth

10 MEDIUM Sensitive Latency

11 HIGH Critical Latency

If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the

RAM access.

The priority order for concurrent accesses are decided by two factors. First the QoS level for the master

and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID

has the highest static priority.

32-bit ARM-Based Microcontrollers

The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.

The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.

Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).

7.5 AHB-APB Bridge

The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and

the low-power APB domain. It is used to provide access to the programmable control registers of

peripherals.

AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:

• Wait state support

• Error reporting

• Transaction protection

• Sparse data transfer (byte, half-word and word)

Additional enhancements:

• Address and data cycles merged into a single cycle

• Sparse data transfer also apply to read access

to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See PM – Power

Manager for details.

Figure 7-1. APB Write Access.

T0 T1 T2 T3

Addr 1

Data 1

PADDR

PWRITE

PCLK

PSEL

PENABLE

PWDATA

PREADY

T0 T1 T2 T3

Addr 1

Data 1

PADDR

PWRITE

PCLK

PSEL

PENABLE

PWDATA

PREADY

T4 T5

Wait statesNo wait states

32-bit ARM-Based Microcontrollers

Figure 7-2. APB Read Access.

T0 T1 T2 T3

Addr 1

Data 1

PADDR

PWRITE

PCLK

PSEL

PENABLE

PRDATA

PREADY

T0 T1 T2 T3

Addr 1

Data 1

PADDR

PWRITE

PCLK

PSEL

PENABLE

PRDATA

PREADY

T4 T5

Wait statesNo wait states

Related Links

Product Mapping

7.6 PAC - Peripheral Access Controller

7.6.1 Overview

There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for

registers of each peripheral connected on the same bridge.

The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager.

CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset.

Refer to PM – Power Manager for details. The PAC will continue to operate in any sleep mode where the

selected clock source is running. Write-protection does not apply for debugger access. When the

debugger makes an access to a peripheral, write-protection is ignored so that the debugger can update

the register.

Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a

read-modify-write operation. These registers are mapped into two I/O memory locations, one for clearing

and one for setting the register bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will

clear the corresponding bit in both registers (WPCLR and WPSET) and disable the write-protection for

the corresponding peripheral, while writing a one to a bit in the Write Protect Set (WPSET) register will set

the corresponding bit in both registers (WPCLR and WPSET) and enable the write-protection for the

corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when read.

If a peripheral is write-protected, and if a write access is performed, data will not be written, and the

peripheral will return an access error (CPU exception).

The PAC also offers a safety feature for correct program execution, with a CPU exception generated on

double write-protection or double unprotection of a peripheral. If a peripheral n is write-protected and a

write to one in WPSET[n] is detected, the PAC returns an error. This can be used to ensure that the

application follows the intended program flow by always following a write-protect with an unprotect, and

vice versa. However, in applications where a write-protected peripheral is used in several contexts, e.g.,

interrupts, care should be taken so that either the interrupt can not happen while the main application or

other interrupt levels manipulate the write-protection status, or when the interrupt handler needs to

unprotect the peripheral, based on the current protection status, by reading WPSET.

32-bit ARM-Based Microcontrollers

7.6.2 Register Description

Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-

bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Refer to the Product

Mapping for PAC locations.

7.6.2.1 PAC0 Register Description

Write Protect Clear

Name: WPCLR

Offset: 0x00

Reset: 0x000000

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

Access

Reset

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

EIC RTC WDT GCLK SYSCTRL PM

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 6 – EIC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 5 – RTC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

32-bit ARM-Based Microcontrollers

Bit 4 – WDT:

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 3 – GCLK

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 2 – SYSCTRL

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 1 – PM

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Write Protect Set

Name: WPSET

Offset: 0x04

Reset: 0x000000

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

Access

Reset

32-bit ARM-Based Microcontrollers

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

EIC RTC WDT GCLK SYSCTRL PM

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 6 – EIC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 5 – RTC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 4 – WDT:

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 3 – GCLK

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 2 – SYSCTRL

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

32-bit ARM-Based Microcontrollers

Bit 1 – PM

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

7.6.2.2 PAC1 Register Description

Write Protect Clear

Name: WPCLR

Offset: 0x00

Reset: 0x000002

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

Access

Reset

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

MTB USB PORT NVMCTRL DSU

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 1

Bit 6 – MTB

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 5 – USB

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

32-bit ARM-Based Microcontrollers

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 3 – PORT

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 2 – NVMCTRL

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 1 – DSU

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Write Protect Set

Name: WPSET

Offset: 0x04

Reset: 0x000002

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

Access

Reset

Bit 15 14 13 12 11 10 9 8

Access

Reset

32-bit ARM-Based Microcontrollers

Bit 7 6 5 4 3 2 1 0

MTB USB PORT NVMCTRL DSU

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 1

Bit 6 – MTB

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 5 – USB

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 3 – PORT

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 2 – NVMCTRL

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 1 – DSU

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

7.6.2.3 PAC2 Register Description

Write Protect Clear

Name: WPCLR

Offset: 0x00

32-bit ARM-Based Microcontrollers

Reset: 0x00800000

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

I2S PTC DAC AC ADC

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TC7 TC4 TC5 TC4 TC3 TCC2 TCC1 TCC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

EVSYS

Access R/W

Reset 0

Bit 20 – I2S

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 19 – PTC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 18 – DAC:

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 17 – AC

Writing a zero to these bits has no effect.

32-bit ARM-Based Microcontrollers

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 16 – ADC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 11, 12, 13, 14, 15 – TC3, TC4, TC5, TC4, TC7

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 8, 9, 10 – TCCn

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 1 – EVSYS

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 0:1, 2:3, 4:5, 6:7, 8:9, 10:11 – SERCOMn

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Write Protect Set

Name: WPSET

Offset: 0x04

Reset: 0x00800000

32-bit ARM-Based Microcontrollers

Property:

–

Bit 31 30 29 28 27 26 25 24

Access

Reset

Bit 23 22 21 20 19 18 17 16

I2S PTC DAC AC ADC

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 20 – I2S

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 19 – PTC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 18 – DAC:

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 17 – AC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

32-bit ARM-Based Microcontrollers

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 16 – ADC

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 11, 12, 13, 14, 15 – TC3, TC4, TC5, TC6, TC7

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 8, 9, 10 – TCCn

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bits 2, 3, 4, 5, 6, 7 – SERCOMn

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

Bit 1 – EVSYS

Writing a zero to these bits has no effect.

Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.

Value Description

0 Write-protection is disabled.

1 Write-protection is enabled.

32-bit ARM-Based Microcontrollers

8. Packaging Information

8.1 Thermal Considerations

Related Links

Junction Temperature

8.1.1 Thermal Resistance Data

The following Table summarizes the thermal resistance data depending on the package.

Table 8-1. Thermal Resistance Data

Package Type θJA θJC

32-pin TQFP 64.7°C/W 23.1°C/W

48-pin TQFP 63.6°C/W 12.2°C/W

64-pin TQFP 60.9°C/W 12.2°C/W

32-pin QFN 40.9°C/W 15.2°C/W

48-pin QFN 32.0°C/W 10.9°C/W

64-pin QFN 32.5°C/W 10.7°C/W

35-ball WLCSP 41.8°C/W 2.26°C/W

8.1.2 Junction Temperature

The average chip-junction temperature, TJ, in °C can be obtained from the following:

1. TJ = TA + (PD x θJA)

2. TJ = TA + (PD x (θHEATSINK + θJC))

where:

• θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data

• θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal

Resistance Data

• θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device

• PD = Device power consumption (W)

• TA = Ambient temperature (°C)

From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling

device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be

used to compute the resulting average chip-junction temperature TJ in °C.

Related Links

Thermal Considerations

32-bit ARM-Based Microcontrollers

8.2 Package Drawings

8.2.1 64 pin TQFP

Table 8-2. Device and Package Maximum Weight

300 mg

Table 8-3. Package Characteristics

Moisture Sensitivity Level MSL3

32-bit ARM-Based Microcontrollers

Table 8-4. Package Reference

JEDEC Drawing Reference MS-026

JESD97 Classification E3

8.2.2 64 pin QFN

Note: The exposed die attach pad is not connected electrically inside the device.

32-bit ARM-Based Microcontrollers

Table 8-5. Device and Package Maximum Weight

200 mg

Table 8-6. Package Charateristics

Moisture Sensitivity Level MSL3

Table 8-7. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E3

8.2.3 64-ball UFBGA

Table 8-8. Device and Package Maximum Weight

27.4 mg

32-bit ARM-Based Microcontrollers

Table 8-9. Package Characteristics

Moisture Sensitivity Level MSL3

Table 8-10. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E8

8.2.4 48 pin TQFP

32-bit ARM-Based Microcontrollers

Table 8-11. Device and Package Maximum Weight

140 mg

Table 8-12. Package Characteristics

Moisture Sensitivity Level MSL3

Table 8-13. Package Reference

JEDEC Drawing Reference MS-026

JESD97 Classification E3

32-bit ARM-Based Microcontrollers

8.2.5 48 pin QFN

Note: The exposed die attach pad is not connected electrically inside the device.

Table 8-14. Device and Package Maximum Weight

140 mg

Table 8-15. Package Characteristics

Moisture Sensitivity Level MSL3

32-bit ARM-Based Microcontrollers

Table 8-16. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E3

8.2.6 45-ball WLCSP

Table 8-17. Device and Package Maximum Weight

7.3 mg

Table 8-18. Package Characteristics

Moisture Sensitivity Level MSL1

Table 8-19. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E1

32-bit ARM-Based Microcontrollers

8.2.7 32 pin TQFP

Table 8-20. Device and Package Maximum Weight

100 mg

Table 8-21. Package Charateristics

Moisture Sensitivity Level MSL3

32-bit ARM-Based Microcontrollers

Table 8-22. Package Reference

JEDEC Drawing Reference MS-026

JESD97 Classification E3

8.2.8 32 pin QFN

Note: The exposed die attach pad is connected inside the device to GND and GNDANA.

Table 8-23. Device and Package Maximum Weight

90 mg

32-bit ARM-Based Microcontrollers

Table 8-24. Package Characteristics

Moisture Sensitivity Level MSL3

Table 8-25. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E3

8.2.9 35 ball WLCSP (Device Variant B)

Table 8-26. Device and Package Maximum Weight

6.2 mg

32-bit ARM-Based Microcontrollers

Table 8-27. Package Characteristics

Moisture Sensitivity Level MSL1

Table 8-28. Package Reference

JEDEC Drawing Reference MO-220

JESD97 Classification E1

8.2.10 35 ball WLCSP (Device Variant C)

32-bit ARM-Based Microcontrollers

Table 8-29. Device and Package Maximum Weight

6.22 mg

Table 8-30. Package Characteristics

Moisture Sensitivity Level MSL1

Table 8-31. Package Reference

JEDEC Drawing Reference N/A

JESD97 Classification e1

8.3 Soldering Profile

The following table gives the recommended soldering profile from J-STD-20.

Table 8-32.

Profile Feature Green Package

Average Ramp-up Rate (217°C to peak) 3°C/s max.

Preheat Temperature 175°C ±25°C 150-200°C

Time Maintained Above 217°C 60-150s

Time within 5°C of Actual Peak Temperature 30s

Peak Temperature Range 260°C

Ramp-down Rate 6°C/s max.

Time 25°C to Peak Temperature 8 minutes max.

A maximum of three reflow passes is allowed per component.

32-bit ARM-Based Microcontrollers

The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as

a means to make files and information easily available to customers. Accessible by using your favorite

Internet browser, the web site contains the following information:

•Product Support – Data sheets and errata, application notes and sample programs, design

resources, user’s guides and hardware support documents, latest software releases and archived

software

•General Technical Support – Frequently Asked Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant program member listing

•Business of Microchip – Product selector and ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Microchip sales offices, distributors and factory

representatives

Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products.

Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata

related to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Design Support”, click on

“Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.

Local sales offices are also available to help customers. A listing of sales offices and locations is included

in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

Related Links

Worldwide Sales and Service

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

32-bit ARM-Based Microcontrollers

SAMD 21 E 15 L - M F T

Product Family

SAMD = General Purpose Microcontroller

21 = Cortex M0 + CPU, Basic Feature Set

E = 32 Pins

G = 48 Pins

No character = Tray (Default)

T = Tape and Reel

U = -40 - 85OC Matte Sn Plating

N = -40 - 105oC Matte Sn Plating

F = -40 - 125OC Matte Sn Plating

A = TQFP

M = QFN

+ DMA + Analog/PWM Optimized

Product Series

Flash Memory Density

Device Variant

A = Default Variant

L = Pinout optimized for analog and PWM

Pin Count

Package Carrier

Package Grade

16 = 64KB

15 = 32KB

Package Type

Note:

1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used

for ordering purposes and is not printed on the device package. Check with your Microchip Sales

Office for package availability with the Tape and Reel option.

2. Small form-factor packaging options may be available. Please check http://www.microchip.com/

packaging for small-form factor package availability, or contact your local Sales Office.

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the

operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is

engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their

code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the

code protection features of our products. Attempts to break Microchip’s code protection feature may be a

violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software

or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for

your convenience and may be superseded by updates. It is your responsibility to ensure that your

application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

32-bit ARM-Based Microcontrollers

WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS

CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life

support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

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from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,

BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,

SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of

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ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight

Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,

chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient

Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL

ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-1347-9

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ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer

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DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

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systems is ISO 9001:2000 certified.

32-bit ARM-Based Microcontrollers

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