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LM6181

SNOS634C –MAY 1998–REVISED SEPTEMBER 2014

LM6181 100 mA, 100 MHz Current Feedback Amplifier

1 Features(1) 3 Description

The LM6181 current-feedback amplifier offers an

1• Slew Rate: 2000 V/μsunparalleled combination of bandwidth, slew-rate,

• Settling Time (0.1%): 50 ns and output current. The amplifier can directly drive up

• Characterized for Supply Ranges: to 100 pF capacitive loads without oscillating and a

± 5 V and ±15 V 10-V signal into a 50-Ωor 75-Ωback-terminated coax

cable system over the full industrial temperature

• Low Differential Gain and Phase Error: range. This represents a radical enhancement in

0.05%, 0.04° output drive capability for an 8-pin PDIP high-speed

• High Output Drive: ±10 V into 100 Ωamplifier making it ideal for video applications.

• Ensured Bandwidth and Slew Rate Built on TI's advanced high-speed VIP™ II (Vertically

• Improved Performance Over EL2020, OP160, Integrated PNP) process, the LM6181 employs

AD844, LT1223 and HA5004 current-feedback providing bandwidth that does not

vary dramatically with gain; 100 MHz at AV=−1,

60 MHz at AV=−10. With a slew rate of 2000V/μs,

(1) Typical, unless otherwise noted 2nd harmonic distortion of −50 dBc at 10 MHz and

settling time of 50 ns (0.1%) the LM6181 dynamic

2 Applications performance makes it ideal for data acquisition, high

speed ATE, and precision pulse amplifier

• Coax Cable Driver applications.

• Video Amplifier

• Flash ADC Buffer Device Information(1)

• High Frequency Filter PART NUMBER PACKAGE BODY SIZE (NOM)

• Scanner and Imaging Systems LM6181 PDIP (8) 9.81 mm × 6.35 mm

LM6181 CDIP (8) 10.16 mm × 6.502 mm

LM6181 SOIC (16) 9.90 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Cable Driver Step Response

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM6181

SNOS634C –MAY 1998–REVISED SEPTEMBER 2014

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Table of Contents

1 Features.................................................................. 17 Typical Applications............................................ 22

7.1 Current Feedback Topology ................................... 22

2 Applications ........................................................... 17.2 Power Supply Bypassing and Layout

3 Description............................................................. 1Considerations......................................................... 23

4 Revision History..................................................... 27.3 Feedback Resistor Selection: Rf............................. 23

5 Pin Configuration and Functions......................... 37.4 Slew Rate Considerations....................................... 24

6 Specifications......................................................... 47.5 Driving Capacitive Loads ........................................ 25

6.1 Absolute Maximum Ratings ...................................... 47.6 Capacitive Feedback............................................... 27

6.2 Handling Ratings....................................................... 48 Application and Implementation ........................ 28

6.3 Recommended Operating Conditions....................... 48.1 Typical Application ................................................. 28

6.4 Thermal Information.................................................. 49 Device and Documentation Support.................. 32

6.5 ±15V DC Electrical Characteristics........................... 59.1 Trademarks............................................................. 32

6.6 ±15V AC Electrical Characteristics........................... 69.2 Electrostatic Discharge Caution.............................. 32

6.7 ±5V DC Electrical Characteristics............................. 79.3 Glossary.................................................................. 32

6.8 ±5V AC Electrical Characteristics............................. 810 Mechanical, Packaging, and Orderable

6.9 Typical Performance Characteristics ........................ 9Information ........................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2013) to Revision C Page

• Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device

Information Table, Pin Configuration and Functions, Application and Implementation; Device and Documentation

Support; Mechanical, Packaging, and Ordering Information. Updated selected plots for readability. .................................. 1

• Changed "Junction Temperature Range" to " Operating Temperature Range" and deleted TJ............................................ 4

• Deleted TJ= 25°C for Electrical Characteristics tables.......................................................................................................... 5

Changes from Revision A (May 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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SNOS634C –MAY 1998–REVISED SEPTEMBER 2014

5 Pin Configuration and Functions

* indicates heat sinking pins(1)

8–Pin CDIP, PDIP, or SOIC 16-Pin SOIC

Package NAB, P, or D Package D

(Top View) (Top View)

Pin Functions

NUMBER I/O DESCRIPTION

NAME NAB, P, D (8) D (16)

-IN 2 2 I Inverting Input

+IN 3 3 I Non-inverting Input

5, 6, 7

N/C 1, 5, 8 –– No Connection

12, 13, 14, 15

OUTPUT 6 10 O Output

V- 4 1, 4, 8, 9, 16 I Negative Supply

V+ 7 11 I Positive Supply

(1) The typical junction-to-ambient thermal resistance of the molded PDIP package soldered directly into a PC board is 102°C/W. The

junction-to-ambient thermal resistance of the SOIC package mounted flush to the PC board is 70°C/W when pins 1, 4, 8, 9 and 16 are

soldered to a total 2 in21 oz. copper trace. The 16-pin SOIC package must have pin 4 and at least one of pins 1, 8, 9, or 16 connected

to V−for proper operation. The typical junction-to-ambient thermal resistance of the SOIC package soldered directly into a PC board is

153°C/W.

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6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply Voltage ±18 V

Differential Input Voltage ±6 V

Input Voltage ±Supply V

Voltage

Inverting Input Current 15 mA

PDIP Package Soldering (10 sec) 260 °C

Soldering Information Vapor Phase (60 seconds) 215 °C

SOIC Package Infrared (15 seconds) 220 °C

Output Short Circuit See(3)

Maximum Junction Temperature 150 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions the

device is intended to be functional, but device parameter specifications may not be ensured under these conditions. For ensured

specifications and test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature

of 150°C. Output currents in excess of ±130 mA over a long term basis may adversely affect reliability.

6.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range −65 +150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all ±3000

V(ESD) Electrostatic discharge V

pins(1)

(1) JEDEC document JEP155 states that 3000-V HBM allows safe manufacturing with a standard ESD control process. Human body model

100 pF and 1.5 kΩ.

6.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply Voltage Range 7 32 V

LM6181AM −55 +125 °C

Operating Temperature Range LM6181AI, LM6181I −40 +85 °C

(1) For ensured Military Temperature Range parameters see RETS6181X.

6.4 Thermal Information P D D

(PDIP) (SOIC) (SOIC)

THERMAL METRIC(1)(2) UNIT

8 PINS 8 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 102 153 70 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 42 42 38

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The typical junction-to-ambient thermal resistance of the molded PDIP package soldered directly into a PC board is 102°C/W. The

junction-to-ambient thermal resistance of the SOIC package mounted flush to the PC board is 70°C/W when pins 1, 4, 8, 9 and 16 are

soldered to a total 2 in2 1 oz. copper trace. The 16-pin SOIC package must have pin 4 and at least one of pins 1, 8, 9, or 16 connected

to V−for proper operation. The typical junction-to-ambient thermal resistance of the SOIC package soldered directly into a PC board is

153°C/W."

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SNOS634C –MAY 1998–REVISED SEPTEMBER 2014

6.5 ±15V DC Electrical Characteristics

The following specifications apply for Supply Voltage = ±15V, RF= 820 Ω, and RL= 1 kΩunless otherwise noted. Boldface

limits apply at the temperature extremes.

PARAMETER TEST CONDITIONS LM6181AM LM6181AI LM6181I UNIT

TYP(1) LIMIT(2) TYP(1) LIMIT(2) TYP(1) LIMIT(2)

VOS Input Offset Voltage 3.0 3.0 5.0 mV

2.0 2.0 3.5

4.0 3.5 5.5 max

TC VOS Input Offset Voltage Drift 5.0 5.0 5.0 μV/°C

IBInverting Input Bias 5.0 5.0 10

2.0 2.0 5.0

Current 12.0 12.0 17.0 μA

max

Non-Inverting Input Bias 1.5 1.5 3.0

0.5 0.5 2.0

Current 3.0 3.0 5.0

TC IBInverting Input Bias 30 30 30

Current Drift nA/°C

Non-Inverting Input Bias 10 10 10

Current Drift

IBInverting Input Bias VS= ±4.5V, ±16V 0.5 0.5 0.75

PSR Current Power Supply 0.3 0.3 0.3

3.0 3.0 4.5

Rejection

Non-Inverting Input Bias VS= ±4.5V, ±16V 0.5 0.5 0.5

Current Power Supply 0.05 0.05 0.05

1.5 1.5 3.0

Rejection μA/V

max

IBInverting Input Bias −10V ≤VCM ≤+10V 0.5 0.5 0.75

CMR Current Common Mode 0.3 0.3 0.3

0.75 0.75 1.0

Rejection

Non-Inverting Input Bias −10V ≤VCM ≤+10V 0.5 0.5 0.5

Current Common Mode 0.1 0.1 0.1

0.5 0.5 0.5

Rejection

CMRR Common Mode −10V ≤VCM ≤+10V 50 50 50 dB

60 60 60

Rejection Ratio 50 50 50 min

PSRR Power Supply Rejection VS= ±4.5V, ±16V 70 70 70 dB

80 80 80

Ratio 70 70 65 min

ROOutput Resistance AV=−1, f = 300 kHz 0.2 0.2 0.2 Ω

RIN Non-Inverting Input MΩ

10 10 10

Resistance min

VOOutput Voltage Swing RL= 1 kΩ11 11 11

12 12 12

11 11 11 V

min

RL= 100Ω10 10 10

11 11 11

7.5 8.0 8.0

ISC Output Short Circuit 100 100 100 mA

130 130 130

Current 75 85 85 min

ZTTransimpedance RL= 1 kΩ1.0 1.0 0.8

1.8 1.8 1.8

0.5 0.5 0.4 MΩ

min

RL= 100Ω0.8 0.8 0.7

1.4 1.4 1.4

0.4 0.4 0.35

ISSupply Current No Load, VO= 0V 10 10 10 mA

7.5 7.5 7.5

10 10 10 max

VCM Input Common Mode V+−1.7 V+−1.7 V+−1.7 V

Voltage Range V−+ 1.7 V−+ 1.7 V−+ 1.7

(1) Typical values represent the most likely parametric norm.

(2) All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).

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6.6 ±15V AC Electrical Characteristics

The following specifications apply for Supply Voltage = ±15V, RF= 820 Ω, RL= 1 kΩunless otherwise noted. Boldface limits

apply at the temperature extremes.

PARAMETER TEST CONDITIONS LM6181AM LM6181AI LM6181I UNIT

TYP(1) LIMIT(2) TYP(1) LIMIT(2) TYP(1) LIMIT(2)

AV= +2 100 100 100

Closed Loop AV= +10 80 80 80

BW Bandwidth MHz

AV=−1 100 80 100 80 100 80

−3 dB min

AV=−10 60 60 60

PBW Power Bandwidth AV=−1, VO= 5 VPP 60 60 60

Overdriven 2000 2000 2000 V/μs

SR Slew Rate AV=−1, VO= ±10V, min

1400 1000 1400 1000 1400 1000

RL= 150Ω(3)

Settling Time AV=−1, VO= ±5V

ts50 50 50

(0.1%) RL= 150Ω

tr, tfRise and Fall Time VO= 1 VPP 5 5 5 ns

Propagation Delay VO= 1 VPP

tp6 6 6

Time

Non-Inverting Input f = 1 kHz

in(+) Noise 3 3 3 pA/√Hz

Current Density

Inverting Input f = 1 kHz

in(−)Noise 16 16 16 pA/√Hz

Current Density

Input Noise f = 1 kHz

enVoltage 4 4 4 pA/√Hz

Density

Second Harmonic 2 VPP, 10 MHz −50 −50 −50

Distortion dBc

Third Harmonic 2 VPP, 10 MHz −55 −55 −50

Distortion

Differential Gain RL= 150Ω, AV= +2, NTSC 0.05% 0.05% 0.05%

Differential Phase RL= 150Ω, AV= +2, NTSC 0.04 0.04 0.04 Deg

(1) Typical values represent the most likely parametric norm.

(2) All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).

(3) Measured from +25% to +75% of output waveform.

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SNOS634C –MAY 1998–REVISED SEPTEMBER 2014

6.7 ±5V DC Electrical Characteristics

The following specifications apply for Supply Voltage = ±5V, RF= 820 Ω, and RL= 1 kΩunless otherwise noted. Boldface

limits apply at the temperature extremes.

PARAMETER TEST CONDITIONS LM6181AM LM6181AI LM6181I UNIT

TYP(1) LIMIT(2) TYP(1) LIMIT(2) TYP(1) LIMIT(2)

VOS Input Offset Voltage 2.0 2.0 3.0 mV

1.0 1.0 1.0

3.0 2.5 3.5 max

TC VOS Input Offset Voltage Drift 2.5 2.5 2.5 μV/°C

IBInverting Input 10 10 17.5

5.0 5.0 5.0

Bias Current 22 22 27.0 μA

max

Non-Inverting Input 1.5 1.5 3.0

0.25 0.25 0.25

Bias Current 1.5 1.5 5.0

TC IBInverting Input Bias 50 50 50

Current Drift nA/°C

Non-Inverting Input 3.0 3.0 3.0

Bias Current Drift

IBInverting Input Bias VS= ±4.0V, ±6.0V 0.5 0.5 1.0

PSR Current 0.3 0.3 0.3

0.5 0.5 1.0

Power Supply Rejection

Non-Inverting Input VS= ±4.0V, ±6.0V 0.5 0.5 0.5

Bias Current 0.05 0.05 0.05

0.5 0.5 0.5

Power Supply Rejection μA/V

max

IBInverting Input Bias −2.5V ≤VCM ≤+2.5V 0.5 0.5 1.0

CMR Current 0.3 0.3 0.3

1.0 1.0 1.5

Common Mode Rejection

Non-Inverting Input −2.5V ≤VCM ≤+2.5V 0.5 0.5 0.5

Bias Current 0.12 0.12 0.12

1.0 0.5 0.5

Common Mode Rejection

CMRR Common Mode −2.5V ≤VCM ≤+2.5V 50 50 50

57 57 57

Rejection Ratio 47 47 47 dB

min

PSRR Power Supply VS= ±4.0V, ±6.0V 70 70 64

80 80 80

Rejection Ratio 70 70 64

ROOutput Resistance AV=−1, f = 300 kHz 0.25 0.25 0.25 Ω

RIN Non-Inverting MΩ

8 8 8

Input Resistance min

VOOutput Voltage Swing RL= 1 kΩ2.25 2.25 2.25

2.6 2.6 2.6

2.2 2.25 2.25 V

min

RL= 100Ω2.0 2.0 2.0

2.2 2.2 2.2

2.0 2.0 2.0

ISC Output Short 75 75 75 mA

100 100 100

Circuit Current 70 70 70 min

ZTTransimpedance RL= 1 kΩ0.75 0.75 0.6

1.4 1.4 1.0

0.35 0.4 0.3 MΩ

min

RL= 100Ω0.5 0.5 0.4

1.0 1.0 1.0

0.25 0.25 0.2

ISSupply Current No Load, VO= 0V 8.5 8.5 8.5 mA

6.5 6.5 6.5

8.5 8.5 8.5 max

VCM Input Common Mode V+−1.7 V+−1.7 V+−1.7 V

Voltage Range V−+ 1.7 V−+ 1.7 V−+ 1.7

(1) Typical values represent the most likely parametric norm.

(2) All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).

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6.8 ±5V AC Electrical Characteristics

The following specifications apply for Supply Voltage = ±5V, RF= 820 Ω, and RL= 1 kΩunless otherwise noted. Boldface

limits apply at the temperature extremes.

PARAMETER TEST CONDITIONS LM6181AM LM6181AI LM6181I UNIT

TYP(1) LIMIT(2) TYP(1) LIMIT(2) TYP(1) LIMIT(2)

BW Closed Loop AV= +2 50 50 50

Bandwidth −3 dB AV= +10 40 40 40 MHz

AV=−1 55 35 55 35 55 35 min

AV=−10 35 35 35

PBW Power Bandwidth AV=−1, VO= 4 VPP 40 40 40

SR Slew Rate AV=−1, VO= ±2V, V/μs

500 375 500 375 500 375

RL= 150Ω(3) min

tsSettling Time (0.1%) AV=−1, VO= ±2V 50 50 50

RL= 150Ω

tr, tfRise and Fall Time VO= 1 VPP 8.5 8.5 8.5 ns

tpPropagation Delay VO= 1 VPP 8 8 8

Time

in(+) Non-Inverting Input f = 1 kHz

Noise 3 3 3 pA/√Hz

Current Density

in(−)Inverting Input Noise f = 1 kHz 16 16 16 pA/√Hz

Current Density

enInput Noise Voltage f = 1 kHz 4 4 4 pA/√Hz

Density

Second Harmonic 2 VPP, 10 MHz −45 −45 −45

Distortion dBc

Third Harmonic 2 VPP, 10 MHz −55 −55 −55

Distortion

Differential Gain RL= 150 Ω, AV= +2, 0.063% 0.063% 0.063%

NTSC

Differential Phase RL= 150 Ω, AV= +2, 0.16 0.16 0.16 Deg

NTSC

(1) Typical values represent the most likely parametric norm.

(2) All limits ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).

(3) Measured from +25% to +75% of output waveform.

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6.9 Typical Performance Characteristics

TA= 25°C unless otherwise noted

Figure 1. Closed-loop Frequency Response VS= ±15V; Figure 2. Closed-loop Frequency Response VS= ±15V;

Rf= 820 Ω; RL= 1 kΩRf= 820 Ω; RL= 150Ω

Figure 3. Unity Gain Frequency Response VS= ±15V; Figure 4. Unit Gain Frequency Response VS= ±5V;

AV= +1; Rf= 820 ΩAV= +1; Rf= 820 Ω

Figure 5. Frequency Response Vs Supply Voltage AV=−1; Figure 6. Frequency Response vs. Supply Voltage AV=−1;

Rf= 820 Ω; RL= 1 kΩRf= 820 Ω; RL= 150 Ω

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 7. Inverting Gain Frequency Response VS= ±15V; Figure 8. Inverting Gain Frequency Response VS= ±5V;

AV=−1; Rf= 820 ΩAV=−1; Rf= 82 0Ω

Figure 9. Non-inverting Gain Frequency Response Figure 10. Non-inverting Gain Frequency Response

VS= ±15V; AV= +2; Rf= 820 ΩVS= ±5V; AV= +2; Rf= 820 Ω

Figure 11. Inverting Gain Frequency Response Figure 12. Inverting Gain Frequency Response

VS= ±15V; AV=−10; Rf= 820 ΩVS= ±5V; AV=−10; Rf= 820 Ω

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 13. Non-inverting Gain Frequency Response Figure 14. Non-inverting Gain Frequency Response

VS= ±15V; AV= +10; Rf= 820 ΩVS= ±5V; AV= +10; Rf= 820 Ω

Figure 15. Non-inverting Gain Frequency Compensation

VS= ±15V; AV= +2; RL= 150 ΩFigure 16. Bandwidth vs Rf& RSAV=−1, RL= 1 kΩ

Figure 18. Transimpedance vs Frequency

Figure 17. Output Swing vs RLOAD Pulsed, VS= ±15V RL= 1 kΩ

VS= ±15V, IIN = ±200 μA, VIN+ = 0V

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 19. Transimpedance vs Frequency Figure 20. Transimpedance vs Frequency

VS= ±15V RL= 100ΩVS= ±5V RL= 1 kΩ

Figure 21. Settling Response VS= ±15V; Figure 22. Settling Response VS= ±5V;

RL= 150Ω; VO= ±5V; AV=−1 RL= 150 Ω; VO= ±2V; AV=−1

Figure 24. Transimpedance vs Frequency

VS= ±5V RL= 100Ω

Figure 23. Suggested Rfand RSfor CLAV=−1; RL= 150Ω

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 25. Suggested Rfand RSfor CLAV=−1 Figure 26. Suggested Rfand RSfor CLAV= +2; RL= 150Ω

Figure 28. Output Impedance vs Freq

Figure 27. Suggested Rfand RSfor CLAV= +2 VS= ±15V; AV=−1 Rf= 820 Ω

Figure 29. Output Impedance vs Freq Figure 30. PSRR (VS+) vs Frequency

VS= ±5V; AV=−1 Rf= 820 Ω

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 31. PSRR (VS−) vs Frequency Figure 32. CMRR vs Frequency

Figure 33. Input Voltage Noise vs Frequency Figure 34. Input Current Noise vs Frequency

Figure 35. Slew Rate vs Temperature AV=−1; Figure 36. Slew Rate vs Temperature AV=−1;

RL= 150 Ω, VS= ±15V RL= 150 Ω, VS= ±5V

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 37. −3 dB Bandwidth vs Temperature AV=−1 Figure 38. Small Signal Pulse response vs Temp,

AV= +1 VS= ±15V; RL= 1 kΩ

Figure 39. Small Signal Pulse Response vs Temp, Figure 40. Small Signal Pulse Response vs Temp,

AV= +1 VS= ±15V; RL= 100ΩAV= +1 VS= ±5V; RL= 1 kΩ

Figure 41. Small Signal Pulse Response vs Temp, Figure 42. Small Signal Pulse Response vs Temp,

AV= +1 VS= ±5V; RL= 100ΩAV=−1 VS= ±15V; RL= 1 kΩ

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 43. Small Signal Pulse Response vs Temp, Figure 44. Small Signal Pulse Response vs Temp,

AV=−1 VS= ±15V; RL= 100ΩAV=−1 VS= ±5V; RL= 1 kΩ

Figure 46. Small Signal Pulse Response vs Temp,

Figure 45. Small Signal Pulse Response vs Temp, AV= +2 VS= ±15V; RL= 1 kΩ

AV=−1 VS= ±5V; RL= 100 Ω

Figure 47. Small Signal Pulse Response vs Temp, Figure 48. Small Signal Pulse Response vs Temp,

AV= +2 VS= ±15V; RL= 100 ΩAV= +2 VS= ±5V; RL= 1 kΩ

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 49. Small Signal Pulse Response vs Temp, Figure 50. Small Signal Pulse Response vs Temp,

AV= +2 VS= ±5V; RL= 100 ΩAV=−10 VS= ±15V; RL= 1 kΩ

Figure 51. Small Signal Pulse Response vs Temp, Figure 52. Small Signal Pulse Response vs Temp,

AV=−10 VS= ±15V; RL= 100ΩAV=−10 VS= ±5V; RL= 1 kΩ

Figure 53. Small Signal Pulse Response vs Temp, Figure 54. Small Signal Pulse Response Vs Temp,

AV=−10 VS= ±5V; RL= 100ΩAV= +10 VS= ±15V; RL= 1 kΩ

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 55. Small Signal Pulse Response vs Temp, Figure 56. Small Signal Pulse Response vs Temp,

AV= +10 VS= ±15V; RL= 100ΩAV= +10 VS= ±5V; RL= 1 kΩ

Figure 57. Small Signal Pulse Response vs Temp, Figure 58. Offset Voltage vs temperature

AV= +10 VS= ±5V; RL= 100Ω

Figure 59. Offset Voltage vs Temperature Figure 60. Transimpedance vs Temperature

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 61. Transimpedance vs Temperature Figure 62. Quiescent Current vs Temperature

Figure 63. PSRR vs Temperature Figure 64. CMRR vs Temperature

Figure 65. Non-inverting Bias Current vs Temperature Figure 66. Inverting Bias Current vs Temperature

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

Figure 67. PSR IB(+) vs Temperature Figure 68. PSR IB(−)vs Temperature

Figure 69. CMR IB(+) vs Temperature Figure 70. CMR IB(−)vs Temperature

Figure 71. ISC(+) vs Temperature Figure 72. ISC(−)vs Temperature

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Typical Performance Characteristics (continued)

TA= 25°C unless otherwise noted

*θJA = Thermal Resistance with 2 square inches of 1 ounce

Copper tied to Pins 1, 8, 9 and 16.

Figure 74. Absolute Maximum Power Derating:

Figure 73. Absolute Maximum Power Derating: SOIC-16 package

PDIP Package

Figure 75. Absolute Maximum Power Derating:

SOIC-8 package

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Time (5 ns/div)

(0.1 V/div)

OUT

Time (5 ns/div)

(0.1 V/div)

OUT

LM6181

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7 Typical Applications

7.1 Current Feedback Topology

For a conventional voltage feedback amplifier the resulting small-signal bandwidth is inversely proportional to the

desired gain to a first order approximation based on the gain-bandwidth concept. In contrast, the current

feedback amplifier topology, such as the LM6181, transcends this limitation to offer a signal bandwidth that is

relatively independent of the closed-loop gain. Figure 76 and Figure 77 illustrate that for closed loop gains of −1

and −5 the resulting pulse fidelity suggests quite similar bandwidths for both configurations.

Figure 76. Step Response, Av = -1V/V

Variation of Closed Loop Gain

from −1 to −5 Yields Similar Responses

Figure 77. Step Response, Av = -5V/V

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Current Feedback Topology (continued)

The closed-loop bandwidth of the LM6181 depends on the feedback resistance, Rf. Therefore, RSand not Rf,

must be varied to adjust for the desired closed-loop gain as in Figure 78.

Figure 78. RSIs Adjusted to Obtain

the Desired Closed Loop Gain, AVCL

7.2 Power Supply Bypassing and Layout Considerations

A fundamental requirement for high-speed amplifier design is adequate bypassing of the power supply. It is

critical to maintain a wideband low-impedance to ground at the amplifiers supply pins to insure the fidelity of high

speed amplifier transient signals. 10 μF tantalum and 0.1 μF ceramic bypass capacitors are recommended for

each supply pin. The bypass capacitors should be placed as close to the amplifier pins as possible (0.5″or less).

7.3 Feedback Resistor Selection: Rf

Selecting the feedback resistor, Rf, is a dominant factor in compensating the LM6181. For general applications

the LM6181 will maintain specified performance with an 820Ωfeedback resistor. Although this value will provide

good results for most applications, it may be advantageous to adjust this value slightly. Consider, for instance,

the effect on pulse responses with two different configurations where both the closed-loop gains are 2 and the

feedback resistors are 820Ωand 1640Ω, respectively. Figure 79 and Figure 80 illustrate the effect of increasing

Rfwhile maintaining the same closed-loop gain—the amplifier bandwidth decreases. Accordingly, larger

feedback resistors can be used to slow down the LM6181 (see −3 dB bandwidth vs Rftypical curves) and reduce

overshoot in the time domain response. Conversely, smaller feedback resistance values than 820Ωcan be used

to compensate for the reduction of bandwidth at high closed loop gains, due to 2nd order effects. For example

Figure 81 illustrates reducing Rfto 500Ωto establish the desired small signal response in an amplifier configured

for a closed loop gain of 25.

Figure 79. Step Response with Rf = 820 Ω

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Feedback Resistor Selection: Rf(continued)

Increasing Compensation with Increasing Rf

Figure 80. Step Response with Rf = 1640 Ω

Figure 81. Reducing Rffor Large

Closed Loop Gains, Rf= 500 Ω

7.4 Slew Rate Considerations

The slew rate characteristics of current feedback amplifiers are different than traditional voltage feedback

amplifiers. In voltage feedback amplifiers slew rate limiting or non-linear amplifier behavior is dominated by the

finite availability of the 1st stage tail current charging the compensation capacitor. The slew rate of current

feedback amplifiers, in contrast, is not constant. Transient current at the inverting input determines slew rate for

both inverting and non-inverting gains. The non-inverting configuration slew rate is also determined by input

stage limitations. Accordingly, variations of slew rates occur for different circuit topologies.

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7.5 Driving Capacitive Loads

The LM6181 can drive significantly larger capacitive loads than many current feedback amplifiers. Although the

LM6181 can directly drive as much as 100 pF without oscillating, the resulting response will be a function of the

feedback resistor value. Figure 83 illustrates the small-signal pulse response of the LM6181 while driving a 50 pF

load. Ringing persists for approximately 70 ns. To achieve pulse responses with less ringing either the feedback

resistor can be increased (see Figure 23,Figure 25, and Figure 26), or resistive isolation can be used (10 Ω–51

Ωtypically works well). Either technique, however, results in lowering the system bandwidth.

Figure 85 illustrates the improvement obtained with using a 47Ωisolation resistor.

Figure 82. Cap Load Direct Drive

Figure 83. AV=−1, LM6181 Can Directly

Drive 50 pF of Load Capacitance with 70 ns

of Ringing Resulting in Pulse Response

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Driving Capacitive Loads (continued)

Figure 84. Cap Load Drive with Isolation Resistor

Rfand RSCould Be Increased to Maintain AV=−1

and Improve Pulse Response Characteristics.

Figure 85. Resistive Isolation of CL

Provides Higher Fidelity Pulse Response

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7.6 Capacitive Feedback

For voltage feedback amplifiers it is quite common to place a small lead compensation capacitor in parallel with

feedback resistance, Rf. This compensation serves to reduce the amplifier's peaking in the frequency domain

which equivalently tames the transient response. To limit the bandwidth of current feedback amplifiers, do not

use a capacitor across Rf. The dynamic impedance of capacitors in the feedback loop reduces the amplifier's

stability. Instead, reduced peaking in the frequency response, and bandwidth limiting can be accomplished by

adding an RC circuit, as illustrated in Figure 87.

Figure 86. Using RC on Input to Affect Frequency Response

(1)

Figure 87. RC Limits Amplifier

Bandwidth to 50 MHz, Eliminating

Peaking in the Resulting Pulse Response

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Typical Application

Figure 88. LM6181 Simplified Schematic

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Typical Application (continued)

8.1.1 Typical Performance Characteristics

8.1.1.1 Overdrive Recovery

When the output or input voltage range of a high speed amplifier is exceeded, the amplifier must recover from an

overdrive condition. The typical recovery times for open-loop, closed-loop, and input common-mode voltage

range overdrive conditions are illustrated in Figure 90,Figure 92, and Figure 93, respectively.

The open-loop circuit of Figure 89 generates an overdrive response by allowing the ±0.5V input to exceed the

linear input range of the amplifier. Typical positive and negative overdrive recovery times shown in Figure 90 are

5 ns and 25 ns, respectively.

Figure 89. Open Loop Input Overdrive Test Circuit

Figure 90. Open-Loop Overdrive Recovery Time of 5 ns,

and 25 ns from Test Circuit in Figure 89

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Typical Application (continued)

The large closed-loop gain configuration in Figure 91 forces the amplifier output into overdrive. Figure 92

displays the typical 30 ns recovery time to a linear output value.

Figure 91. Overdrive Recovery Circuit under Large Closed Loop Gain Condition

Figure 92. Closed-Loop Overdrive Recovery

Time of 30 ns from Exceeding Output

Voltage Range from Circuit in Figure 91

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Typical Application (continued)

The common-mode input of the circuit in Figure 91 is exceeded by a 5V pulse resulting in a typical recovery time

of 310 ns shown in Figure 93. The LM6181 supply voltage is ±5V.

Figure 93. Exceptional Output

Recovery from an Input that

Exceeds the Common-Mode Range

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9 Device and Documentation Support

9.1 Trademarks

VIP is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

9.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

9.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LM6181

PACKAGE OPTION ADDENDUM

www.ti.com 15-Aug-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM6181IM-8/NOPB LIFEBUY SOIC D 8 95 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM618

1IM8

LM6181IMX-8/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM618

1IM8

LM6181IN/NOPB LIFEBUY PDIP P 8 40 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6181IN

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 15-Aug-2017

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM6181IMX-8/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM6181IMX-8/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2014

Pack Materials-Page 2

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