Rev. 1.7 (May 2011) 1 © DLP Design, Inc.
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FEATURES:
• Xilinx XC3S200A-4FTG256C FPGA utilized on the DLP-HS-FPGA
• Xilinx XC3S400A-4FTG256C FPGA utilized on the DLP-HS-FPGA2
• Micron 32M x 8 DDR2 SDRAM Memory
• Built-In Configuration Loader; Writes the Bit File Directly to SPI Flash via High-Speed USB 2.0
Interface
• 63 User I/O Channels: 24 Differential Pairs and 8 Global Clocks
• 66 MHz Oscillator
• 133 MHz DDR2 Interface Reference Design Provided
• USB Port Powered or 5V External Power Barrel Jack
• USB 1.1 and 2.0 Compatible Interface
• Small Footprint: 3.0 x 1.2-Inch PCB and Standard 50-Pin, 0.9-Inch DIP Interface
Rev. 1.7 (May 2011) 2 © DLP Design, Inc.
APPLICATIONS:
• Rapid Prototyping
• Educational Tool
• Industrial/Process Control
• Data Acquisition/Processing
• Embedded Processor
1.0 INTRODUCTION
The DLP-HS-FPGA module is a low-cost, compact prototyping tool that can be used for rapid proof of
concept or within educational environments. The module is based on the Xilinx Spartan™ 3A and
Future Technology Devices International’s FT2232H Dual-Channel High-Speed USB IC. The
DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to
developing FPGA-based designs. When combined with the free ISE™ WebPACK™ tools from Xilinx,
this module is more than sufficient for creating anything from basic logical functions to a highly
complex system controller.
As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files
directly to the SPI Flash—no external programmer is required. This represents a savings of as much
as $200 in that no additional programming cable is required for configuring the FPGA. All that is
needed to load bit files to the DLP-HS-FPGA is a Windows software utility (free with purchase), a
Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool
environment using a Xilinx programming cable (purchased separately).
The DLP-HS-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE
WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and
simulation, implementation, device fitting and JTAG programming.
The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages
from a single 5-volt source. Power for the module can be taken from either the host USB port or from
a user-supplied, external 5-volt power supply via an onboard standard barrel connector.
Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025-square
inch post DIP header on the bottom of the board and a 26-pin, 0.05-inch wide top side 2x13 header.
The bottom side 50-pin header provides access to 41 of the FPGA user input/output pins. The top
side header provides access to 22 of the FPGA user input/output pins. The bottom side header mates
with a user-supplied, standard, 50-pin, 0.9-inch spaced DIP socket. The top side header mates with a
Rev. 1.7 (May 2011) 3 © DLP Design, Inc.
user-supplied, 0.05-inch spaced, 2x13 connector such as the FFSD-13-D-xx.xx-01 (xx.xx = cable
length) ribbon cable assembly from Samtec.
DIP Socket Ribbon Cable
Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects and both
JTAG and SPI Flash interface ports for connection to Xilinx programming tools.
2.0 REFERENCE DESIGN
A 10,000-line reference design is available for the Spartan™ 3A FPGA on the DLP-HS-FPGA to those
who purchase the module. The design was written in VHDL and built using the free Xilinx ISE™
WebPACK™ tools. The reference design consists of the following blocks:
It contains a USB Interface Block, a User I/0 Block, a DDR2 SDRAM interface, a Heartbeat Pulse
Generator and a Clock Generator. The SPI Flash is used to store the design’s FPGA configuration
file.
The USB interface captures, interprets and returns command and data information sent from the host
PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback
Data, Set a User I/O Pin High or Low, Read a User I/O Pin, Initialize the DDR2 SDRAM Memory and
Read or Write the DDR2 SDRAM Memory. ( Section 11 explains these in detail.)
Rev. 1.7 (May 2011) 4 © DLP Design, Inc.
The User I/O Block controls access to the 63 user I/O pins accessible through the top- and bottom-
side headers. Every one of these pins can be either an input or an output. The User I/O Block can
configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a
side note, 48 of these user I/O pins can be configured as 24 differential pairs, 8 can be configured as
global clock inputs and 6 can be configured as regional clock inputs.)
The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle and the
read and write access. Read and write access is available in 4-byte bursts. The traces between the
DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266
Mbit/s (clocked at 133MHz). The interface creates and aligns the Data Strobes (DQS) based on an
external feedback trace that matches two times the trace length between the FPGA and the DDR2
SDRAM. The Initialization, Read and Write commands are initiated by the USB interface block and
executed by the DDR2 SDRAM interface block.
The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the
onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second.
The Clock Generator Block receives the 66-MHz clock and produces both the 133-MHz clocks
required to run the DDR2 SDRAM memory device and the 100-MHz clock for the remaining internal
logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks.
The design occupies the following FPGA resources on the DLP-HS-FPGA module’s XC3S200A:
The design occupies the following FPGA resources on the DLP-HS-FPGA2 module’s XC3S400A:
Rev. 1.7 (May 2011) 5 © DLP Design, Inc.
More reference designs are planned. Please contact DLP Design with any specific requests.
3.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan™ 3A: XC3S200A-4FTG256
• Part Number: XC3S200A-4FTG256C
• System Gates: 200,000
• Equivalent Logic Cells: 4,032
• CLB Array:
Rows: 32
Columns: 16
Total CLB’s: 448
Total Slices: 1,792
Total Flip Flops: 3,584
Total 4-Input LUT’s: 3,584
• Distributed RAM Bits: 28K
• Block RAM Bits: 288K
• Dedicated Multipliers: 16
• DCM’s: 4
Rev. 1.7 (May 2011) 6 © DLP Design, Inc.
The FPGA device used on the DLP-HS-FPGA2 is the Xilinx Spartan™ 3A: XC3S400A-4FTG256
• Part Number: XC3S400A-4FTG256C
• System Gates: 400,000
• Equivalent Logic Cells: 8,064
• CLB Array:
Rows: 40
Columns: 24
Total CLB’s: 896
Total Slices: 3,584
Total Flip Flops: 7,168
Total 4-Input LUT’s: 7,168
• Distributed RAM Bits: 56K
• Block RAM Bits: 360K
• Dedicated Multipliers: 20
• DCM’s: 4
4.0 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed here may cause permanent damage to the DLP-HS-FPGA:
Operating Temperature: 0-70°C
Voltage on Digital Inputs with Respect to Ground: -0.5V to +4.1 V
Sink/Source Current on Any I/O: 24 mA (using LVTTL as the FPGA I/O standard)
5.0 WARNINGS
• Unplug from the host PC and power adapter before connecting to I/O on the DLP-HS-FPGA.
• Isolate the bottom of the board from all conductive surfaces.
• Observe static precautions to prevent damage to the DLP-HS-FPGA module.
6.0 BITLOADAPP SOFTWARE
Windows software is provided for use with the DLP-HS-FPGA that will load an FPGA configuration
(*.bit) file directly to the SPI Flash device via the USB interface. This application (illustrated below) will
allow the user to erase the Flash, verify the erasure and then program and verify the Flash:
Rev. 1.7 (May 2011) 7 © DLP Design, Inc.
7.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp
software then select and program a file from the local hard drive directly to the SPI Flash. Once
written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-HS-FPGA giving the user access to the
specific pins required by the development tools. (Refer to the schematic contained within this
datasheet for details.)
8.0 EEPROM SETUP / MPROG
The DLP-HS-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively
to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module or when the PROG Pin is driven low
and then released by the application software. Channel B is used for communication between the
FPGA and host PC at run time. A 93LC56B EEPROM connected to the USB interface IC is used to
store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID
(VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port
type (UART serial or FIFO parallel).
As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI
Flash, and Channel B is used for communication between the host PC and the DLP-HS-FPGA. As
such, the D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel A.
Channel B must use the 245 FIFO mode, but it can use either the VCP or D2XX drivers. The VCP
drivers make the DLP-HS-FPGA appear as an RS232 port to the host application. The D2XX drivers
provide faster throughput, but require working with a *.lib or *.dll library in the host application.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com.
Rev. 1.7 (May 2011) 8 © DLP Design, Inc.
9.0 TEST BIT FILE
A test file is provided as a download from the DLP Design website that provides rudimentary access
to the I/O features of the DLP-HS-FPGA. The following features are provided:
• Ping
• Read the High/Low State of the Input-Only Pins
• Drive I/O Pins High/Low or Read their High/Low State
• Simple Loopback on Channel B
• 4 Byte Read/Write Access of Row, Column, and Bank Address in the DDR2 SDRAM
This bit file is available from the DLP-HS-FPGA’s download page. The command structure that
supports these features is explained in Section 11.
Rev. 1.7 (May 2011) 9 © DLP Design, Inc.
10.0 USB DRIVERS
USB drivers for the following operating systems are available for download from the DLP Design
website at www.dlpdesign.com:
OPERATING SYSTEM SUPPORT
Windows 7 32-bit Windows 7 64-bit
Windows Vista, Vista x64 Mac OSX
Windows XP, XP x64 Mac OS9
Windows Server 2008, x64 Mac OS8
Windows Server 2003, x64 Linux
Windows 2000 Windows CE 4.2 – 6.0
Notes:
1. The bit file load utility only runs on the Windows platforms.
2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this
function.
3. If you are utilizing the dual-mode drivers from FTDI (CDM2.x.x) and you want to use the Virtual
COM Port (VCP) drivers, then it may be necessary to disable the D2XX drivers first via Device
Manager. To do so, right click on the entry under USB Controllers that appears when the
DLP-HS-FPGA is connected, select Properties, select the Advanced tab, check the option for
“Load VCP” and click OK. Then unplug and replug the DLP-HS-FPGA, and a COM port should
appear in Device Manager under Ports (COM & LPT).
11.0 USING THE DLP-HS-FPGA
Select a power source via Header Pins 23 and 24, and connect the DLP-HS-FPGA to the PC to
initiate the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each
other. This will result in operational power being taken from the host PC. Once the drivers are loaded,
the DLP-HS-FPGA is ready for use.
Rev. 1.7 (May 2011) 10 © DLP Design, Inc.
Simply connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. Once the USB
drivers are loaded, the DLP-HS-FPGA is ready for use. All commands are issued as multi-byte
command packets consisting of at least two bytes.
You can either utilize the Test Application available from http://www.dlpdesign.com/test.shtml with
the DLP-HS-FPGA (as described in Section 12), or you can write your own program in your language
of choice.
If you are using the VCP drivers, begin by opening the COM port, and send multi-byte commands as
shown in Table 1 below. There is no need to set the baud rate because the DLP-HS-FPGA uses a
parallel interface between the USB IC and the FPGA. (The Ping Command can be used to locate the
correct COM port used for communicating with the DLP-HS-FPGA, or you can look in Device
Manager to see which port was assigned by Windows.) If you are using the D2XX drivers as with the
Test Application, no COM port selection is necessary.
TABLE 1
Command Packets
Command
Packet
Description
Byte Hex
Value
Return/Comments
Ping Issues Ping 0 0x00 Ping Command - 0x56 will be returned indicating that
the DLP-HS-FPGA is found on the selected port.
Read
Version/
Status
Accesses
the internal
version/
status
registers
0 0x10 Read Version/Status Registers Command
1 0xnn Register Address: 0xnn =
0x00 = Board ID (0x11 = Production PCB)
0x01 = FPGA Type ID : 0x3A = XC3S200A
0x4A = XC3S400A
0x02 = Design Version ID 1 (Design Month)
0x03 = Design Version ID 2 (Design Day)
0x04 = Design Version ID 3 (Design Year)
0x05 = Design Version ID 4 (Design Version)
0x06 = DDR2 Status: 0x00 = Not Initialized
0x01 = Initialized
Loopback Returns the
data byte
received
0 0x20 Loopback Command
1 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be
returned back.
Loopback
Compliment Returns the
compliment
of data byte
received
0 0x21 Loopback Compliment Command
1 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be
complimented and returned back.
Read Pin Reads the
state of one
of the user
I/O pins
0 0x30 Read Pin Command
1 0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is read and returns:
0x00 = User I/O pin 0xnn is low
0x01 = User I/O pin 0xnn is high
Rev. 1.7 (May 2011) 11 © DLP Design, Inc.
Clear Pin Forces the
selected
user I/O pin
low
0 0x40 Clear Pin Command
1 0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is cleared. The specified user I/O
number is returned.
Set Pin Forces the
selected
user I/O pin
high
0 0x41 Set Pin Command
1 0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is set. The specified user I/O number
is returned.
Initialize
Memory Initializes
DDR2
SDRAM
0 0x70 The Initialize Memory Command configures the DDR2
SDRAM for access by the FPGA. The memory cannot
be accessed without being initialized.
Important Note on DDR2 SDRAM Data Access:
DDR2 SDRAM data accesses using the reference design on the DLP-HS-FPGA module are always
performed 4 bytes at a time due to the fact that the device is configured for a burst length of four.
What this means is that column address Bits 0 and 1 only change the order of the read or write bytes;
they still refer to the same 4 bytes. Therefore, to increment the DDR2 SDRAM address for
consecutive memory locations, the column address must be incremented by 4.
Incrementing the column address by anything less than 4 simply changes the order in which the 4
bytes specified by column address 9:3 are written to the memory or returned to the user. For example,
a write to a column starting address of 0 will write to column locations 0, 1, 2 and 3. But if the user
then writes to column address 1, they will actually be writing to column locations 1, 2, 3 and 0, which
will overwrite the previous write operation.
More details on how the DDR2 SDRAM column bits 1 and 0 function can be found in Figure 4 and
Table 40 of the Micron™ MT47H32M8 datasheet. For details on how the bank, row and column bits
are sent via USB to the memory, refer to the commands below:
Memory
Read Reads 4
bytes from
the DDR
SDRAM
0 0x8n Reads 4 bytes from the DDR2 SDRAM starting with the
address specified. The command byte is OR’d with the
Most Significant Row Address Bit (24).
n = 0 the Most Sig Row Address Bit is low (0x80)
n = 1 the Most Sig Row Address Bit is high (0x81)
1 0xah Bits 23-16 Middle 8 bits of Row Address to be read from
2 0xam Bits 15-12 Lower 4 bits of Row Address to be read from
Bits 11-8 Upper 4 bits Column Address to be read from
3 0xal Bits 7-2: Lower 6 bits of Column Address to be read
from
NOTES: Refer to the text above regarding Column Bits
1 and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank
Address to be read from.
If the memory has not been initialized, the data returned
will be invalid, and the command returned will be 0xE7
indicating the error.
Rev. 1.7 (May 2011) 12 © DLP Design, Inc.
Memory
Write Writes 4
bytes to the
DDR
SDRAM
0 0x9n Writes 4 bytes to the DDR2 SDRAM starting with the
address specified. The command byte is OR’d with the
Most Significant Row Address bit (24).
n = 0 the Most Sig Row Address bit is low (0x90)
n = 1 the most Sig Row Address bit is high (0x91)
1 0xah Bits 23-16 Middle 8 bits of Row Address to be written to
2 0xam Bits 15-12 Lower 4 bits of Row Address to be written to
Bits 11-8 Upper 4 bits Column Address to be written to
3 0xal Bits 7-2: Lower 6 bits of column address to be written to
NOTE: Refer to the text above regarding Column Bits 1
and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank Address
to be written to
4 0xd0 Data Byte 0 written to Address Specified
5 0xd1 Data Byte 1 written to Address Specified + 1
6 0xd2 Data Byte 2 written to Address Specified + 2
7 0xd3 Data Byte 3 written to Address Specified + 3. Returns
the 4 bytes written followed by an echo back of the
command and address data sent.
NOTE: If the memory has not been initialized, the
command returned will be 0xE7 indicating the error.
The USER I/O Pin Read/Set/Clear Commands I/O number mapping to the physical I/O pins on the
DLP-HS-FPGA board are described in the following table:
TABLE 2
User I/O
I/O Number DLP-HS-
FPGA Pin
XC3S200A
XC3S400A
Pin
XC3S200A
XC3S400A
Bank
FPGA Pin Configurations Available
0x00 (0) J1 Pin 2 D13 0 Digital Input, Output, Differential Pair 0+
0x01 (1) J1 Pin 3 C13 0 Digital Input, Output, Differential Pair 0-
0x02 (2) J1 Pin 4 D11 0 Digital Input, Output, Differential Pair 1-
0x03 (3) J1 Pin 5 C12 0 Digital Input, Output, Differential Pair 1+
0x04 (4) J1 Pin 6 C10 0 Digital Input, Output, Differential Pair 2+,
Global Clock
0x05 (5) J1 Pin 7 D9 0 Digital Input, Output, Differential Pair 2-,
Global Clock
0x06 (6) J1 Pin 8 C8 0 Digital Input, Output, Differential Pair 3+,
Global Clock
0x07 (7) J1 Pin 9 D8 0 Digital Input, Output, Differential Pair 3-,
Global Clock
0x08 (8) J1 Pin 10 A14 0 Digital Input, Output, Differential Pair 4+
0x09 (9) J1 Pin 12 A13 0 Digital Input, Output, Differential Pair 4-
0x0A (10) J1 Pin 13 A6 0 Digital Input, Output, Differential Pair 5+
0x0B (11) J1 Pin 14 B6 0 Digital Input, Output, Differential Pair 5-
0x0C (12) J1 Pin 15 C11 0 Digital Input, Output, Differential Pair 6+
0x0D (13) J1 Pin 16 A11 0 Digital Input, Output, Differential Pair 6-
Rev. 1.7 (May 2011) 13 © DLP Design, Inc.
0x0E (14) J1 Pin 17 B8 0 Digital Input, Output, Differential Pair 7-,
Global Clock
0x0F (15) J1 Pin 18 A8 0 Digital Input, Output, Differential Pair 7+,
Global Clock
0x10 (16) J1 Pin 19 C5 0 Digital Input, Output, Differential Pair 8-
0x11 (17) J1 Pin 20 A5 0 Digital Input, Output, Differential Pair 8+
0x12 (18) J1 Pin 21 B3 0 Digital Input, Output, Differential Pair 9-
0x13 (19) J1 Pin 22 A3 0 Digital Input, Output, Differential Pair 9+
0x14 (20) J1 Pin 27 F3 3 Digital Input, Output, Differential Pair 10+
0x15 (21) J1 Pin 29 G4 3 Digital Input, Output, Differential Pair 10-
0x16 (22) J1 Pin 30 C2 3 Digital Input, Output, Differential Pair 11+
0x17 (23) J1 Pin 31 C1 3 Digital Input, Output, Differential Pair 11-
0x18 (24) J1 Pin 32 E1 3 Digital Input, Output, Differential Pair 12-
0x19 (25) J1 Pin 33 D1 3 Digital Input, Output, Differential Pair 12+
0x1A (26) J1 Pin 34 J6 3 Digital Input, Output, Differential Pair 13-
0x1B (27) J1 Pin 35 J4 3 Digital Input, Output, Differential Pair 13+
0x1C (28) J1 Pin 36 H6 3 Digital Input, Output, Differential Pair 14+
0x1D (29) J1 Pin 37 H5 3 Digital Input, Output, Differential Pair 14-
0x1E (30) J1 Pin 38 M4 3 Digital Input, Output, Differential Pair 15-
0x1F (31) J1 Pin 39 N3 3 Digital Input, Output, Differential Pair 15+
0x20 (32) J1 Pin 41 E3 3 Digital Input, Output, Differential Pair 16+
0x21 (33) J1 Pin 42 E2 3 Digital Input, Output, Differential Pair 16-
0x22 (34) J1 Pin 43 H3 3 Digital Input, Output, Differential Pair 17+
0x23 (35) J1 Pin 44 J3 3 Digital Input, Output, Differential Pair 17-
0x24 (36) J1 Pin 45 K1 3 Digital Input, Output, Differential Pair 18-,
Regional Clock
0x25 (37) J1 Pin 46 K3 3 Digital Input, Output, Differential Pair 18+,
Regional Clock
0x26 (38) J1 Pin 47 P1 3 Digital Input, Output, Differential Pair 19-
0x27 (39) J1 Pin 48 N2 3 Digital Input, Output, Differential Pair 19+
0x28 (40) J1 Pin 49 T9 2 Digital Input, Output, Global Clock
0x29 (41) J4 Pin 1 B15 0 Digital Input, Output
0x2A (42) J4 Pin 3 A12 0 Digital Input, Output
0x2B (43) J4 Pin 5 B10 0 Digital Input, Output, Differential Pair 20+
0x2C (44) J4 Pin 7 A10 0 Digital Input, Output, Differential Pair 20-
0x2D (45) J4 Pin 9 A9 0 Digital Input, Output, Global Clock
0x2E (46) J4 Pin 11 N1 3 Digital Input, Output
0x2F (47) J4 Pin 13 E7 0 Digital Input, Output
0x30 (48) J4 Pin 15 C4 0 Digital Input, Output
0x31 (49) J4 Pin 17 C7 0 Digital Input, Output
0x32 (50) J4 Pin 19 K4 3 Digital Input, Output
0x33 (51) J4 Pin 21 R1 3 Digital Input, Output
0x34 (52) J4 Pin 2 A7 0 Digital Input, Output
0x35 (53) J4 Pin 4 A4 0 Digital Input, Output, Differential Pair 21+
0x36 (54) J4 Pin 6 B4 0 Digital Input, Output, Differential Pair 21-
0x37 (55) J4 Pin 8 F1 3 Digital Input, Output, Differential Pair 22+
0x38 (56) J4 Pin 10 G1 3 Digital Input, Output, Differential Pair 22-
0x39 (57) J4 Pin 12 H1 3 Digital Input, Output, Regional Clock
0x3A (58) J4 Pin 14 J1 3 Digital Input, Output, Regional Clock
0x3B (59) J4 Pin 16 L1 3 Digital Input, Output
0x3C (60) J4 Pin 18 M1 3 Digital Input, Output
Rev. 1.7 (May 2011) 14 © DLP Design, Inc.
0x3D (61) J4 Pin 20 M3 3 Digital Input, Output, Differential Pair 23+
0x3E (62) J4 Pin 22 L4 3 Digital Input, Output, Differential Pair 23-
SUSPEND J4 Pin 23 R16 1 Force Suspend Mode (when enabled)
AWAKE J4 Pin 24 T11 2 Return from Suspend Mode Operation
+5V IN J1 Pin 23 - - +5V input to the DLP-HS-FPGA
+5V USB J1 Pin 24 - - +5V supplied by host PC USB port
+3.3V OUT J1 Pin 28,
J4 Pin 26 - -
+3.3V supplied by the onboard DLP-HS-
FPGA regulator after module enumerated
GND
J1 Pin 1,
J1 Pin 11,
J1 Pin 25,
J1 Pin 26,
J1 Pin 40,
J1 Pin 50,
J4 Pin 25
- -
Ground
Rev. 1.7 (May 2011) 15 © DLP Design, Inc.
12.0 USING THE DLP TEST APPLICATION (OPTIONAL)
Users can design their own application interface to send USB commands to the DLP-HS-FPGA
module or utilize the test application tool available from DLP Design. The DLP Test Application is
available in a free version for download from the DLP Design website at
www.dlpdesign.com/test.shtml. Using this tool, single- and multi-byte commands can be sent to the
DLP-HS-FPGA board.
Once installed the test application is used as follows:
The commands used to interface to the DLP-HS-FPGA are detailed in Section 10 of this datasheet.
Rev. 1.7 (May 2011) 16 © DLP Design, Inc.
13.0 MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY)
Rev. 1.7 (May 2011) 17 © DLP Design, Inc.
14.0 SCHEMATICS
Schematics for the DLP-HS-FPGA are included on the following three pages:
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Downloading
FPGA Code
For FPGA configuration
via SPI only.
PRELIMINARY
DLP-HS-FPGA
Page 1
v1.2
UPLOAD
500 mA
DC:+3.6 to +6.0V
13
2
Bottom side FPGA IO (top view)
Top side FPGA IO
DNS
EEDATA
PWREN#
EECS
P1V8
EESK
P5V0 USER_IO39_DP19
USER_IO36_DN18_RC
USER_IO31_DP15
USER_IO2_DN1
USER_IO33_DN16
USER_IO38_DN19
USER_IO40_GC
USER_IO3_DP1
USER_IO32_DP16
USER_IO34_DP17_RC
USER_IO5_DN2_GC USER_IO35_DN17_RC
USER_IO0_DP0
USER_IO18_DN9
USER_IO13_DN6
USER_IO17_DP8
USER_IO24_DN12
USER_IO23_DN11
USER_IO12_DP6
USER_IO20_DP10
USER_IO26_DN13
USER_IO21_DN10
USER_IO25_DP12
USER_IO37_DP18_RC
USER_IO22_DP11
USER_IO11_DN5
USER_IO16_DN8
USER_IO19_DP9
USER_IO15_DP7_GC
USER_IO14_DN7_GC
USER_IO27_DP13
USER_IO7_DN3_GC
USER_IO29_DN14
USER_IO6_DP3_GC
USER_IO8_DP4
USER_IO28_DP14
USER_IO9_DN4
USER_IO30_DN15
USER_IO4_DP2_GC
VCCSW
USER_IO1_DN0
FTDI_RXF
FTDI_D6
FTDI_D2
FTDI_D3
FTDI_TXE
FTDI_D7
FTDI_D0
FTDI_D1
FTDI_RD
FTDI_SI
FTDI_WR
FTDI_D5
FTDI_D4
SPI_MOSI
SPI_DIN
SPI_CSO_B
FPGA_RESET
SPI_CLK
VPLL
VPHY
VPLL
VPHY
PORTVCC
5VIN
FPGA_AWAKE
FPGA_SUSPEND
VCCSW
PORTVCC
5VIN
USER_IO10_DP5
USER_IO41 USER_IO52
USER_IO42
USER_IO43_DP20
USER_IO44_DN20
USER_IO45_GC
USER_IO46
USER_IO47
USER_IO48
USER_IO49
USER_IO50
USER_IO51
FPGA_SUSPEND
USER_IO53_DP21
USER_IO54_DN21
USER_IO55_DP22
USER_IO56_DN22
USER_IO57_RC
USER_IO58_RC
USER_IO59
USER_IO60
USER_IO61_DP23
USER_IO62_DN23
FPGA_AWAKE
VCCSW
SPI_PROG
3V3
5V0
3V3
3V3
3V3
3V3
3V3
3V33V3
5V0
3V3
5V0
CN1
CN-USB
1
2
3
4
5
C8
1.0uF/0603
C77
.1uF
CN2
DC BARREL JACK
2
3
1
D4
MBR130T1G
C2
.1uF
TP4 SPARE_ACBUS1
1
C1
.01
C47
.1uF
R24
2.2K
JP3
PROG Disable
1
2
C18
0.1uF
R31
1K
J1
CONN PCB 25x2
8
7
6
1
2
3
4
5
10
9
12
11
13
15
14
17
16
18
20
19
25
24
23
22
21
34
33
32
31
30
29
28
27
26
40
39
38
37
36
35
50
49
48
47
46
45
44
43
42
41
8
7
6
1
2
3
4
5
10
9
12
11
13
15
14
17
16
18
20
19
25
24
23
22
21
34
33
32
31
30
29
28
27
26
40
39
38
37
36
35
50
49
48
47
46
45
44
43
42
41
Q2
IRLML6402
R27
24.9K
Y1
12MHz
FB2
240-1018-1
1 2
C5
.1uF
C48
.1uF
R3
10K
C3910uF/10V
C17
0.1uF
R28
10K 5%
R4
2.2K
C3
.1uF
R19
0
U1
FT1232HQ
51
47
42
56
8
62
31
20
64
37
12
9
4
50
7
10
1
5
11
15
25
35
59
58
57
55
54
53
52
48
16
17
18
19
21
22
23
24
26
27
28
29
30
32
33
34
38
39
40
41
43
44
45
46
3
2
14
6
49
63
61
13
60
36
GND
GND
VCCIO
VCCIO
DP
EECLK
VCCIO
VCCIO
VCORE
VCORE
VCORE
VPLL
VPHY
VREGIN
DM
AGND
GND
GND
GND
GND
GND
GND
BCBUS7/PWRSAV#/PWRSAV#/GPIOH7
BCBUS6/-/-/GPIOH6
BCBUS5/-/-/GPIOH5
BCBUS4/RXLED#/SIWUB/GPIOH4
BCBUS3/TXLED#/WR#/GPIOH3
BCBUS2/RDSTB#/RD#/GPIOH2
BCBUS1/WRSTB#/TXE#/GPIOH1
BCBUS0/TXDEN/RXF#/GPIOH0
ADBUS0/TXD/D0/TCK SK
ADBUS1/RXD/D1/TDI DO
ADBUS2/RTS#/D2/TDO DI
ADBUS3/CTS#/D3/TMS CS
ADBUS4/DTR#/D4/GPIOL0
ADBUS5/DSR#/D5/GPIOL1
ADBUS6/DCD#/D6/GPIOL2
ADBUS7/RI#/D7/GPIOL3
ACBUS0/TXDEN/RXF#/GPIOH0
ACBUS1/WRSTB#/TXE#/GPIOH1
ACBUS2/RDSTB#/RD#/GPIOH2
ACBUS3/TXLED#/WR#/GPIOH3
ACBUS4/RXLED#/SIWUA/GPIOH4
ACBUS5/-/CLKOUT/GPIOH5
ACBUS6/-/OE#/GPIOH6
ACBUS7/-/-/GPIOH7
BDBUS0/TXD/DO/TCK SK
BDBUS1/RXD/D1/TDI DO
BDBUS2/RTS#/D2/TDO DI
BDBUS3/CTS#/D3/TMS CS
BDBUS4/DTR#/D4/GPIOL0
BDBUS5/DSR#/D5/GPIOL1
BDBUS6/DCD#/D6/GPIOL3
BDBUS7/RI#/D7/GPIOL4
OSCO
OSCI
RESET#
REF
VREGOUT
EECS
EEDATA
TEST
PWREN#
SUSPEND#
C33
.1uF
Q4
MMBT3904L
3
1
2
C34
10/10 Tant
FB3
240-1018-1
1 2
J4
CONN HDR 13x2
15
13
11
1
3
5
7
9
19
17
23
21
25
22
24
26
2
4
6
8
10
12
14
16
18
20
15
13
11
1
3
5
7
9
19
17
23
21
25
22
24
26
2
4
6
8
10
12
14
16
18
20
FB1
240-1018-1
1 2
C4
.1uF
D5
RED
C9
.1uF
C49
.1uF
R6
10K
R32 0
C10
4.7uF
C11
27pF
U3
93LC46
1
2
3
4
8
7
6
5
CS
SK
DIN
DOUT
VCC
NC
NC/ORG
GND
R16 27
TP5 SPARE_ACBUS6
1
C6
4.7uF
R17 27
R2
12K
C26
.1uF
R13
150
C85
.1uF
C19
10/10 Tant
R7 10K
C25
4.7uF
TP6 SPARE_ACBUS7
1
C46
.1uF
U2
NCP605-3.3V
41
5
2
6
3
VOUTVIN
SENSE
GND
VIN
EN
C12
27pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PRELIMINARY
Page 2
DLP-HS-FPGA
TDI
SPI
Flash
TMS
TDO
TCK
200mA Maximum
1.5A Maximum
1.2V REGULATOR
1.8V REGULATOR
2.5 mS ramp up
DDR II parallel
terminations
Use Ceramic caps
DNS
DNS
V1.2
DNS
DNS
DNS
DNS
DNS
DNS
DNS
DNS
SPI_PROG
JTAG_DIN
JTAG_TMS
JTAG_TCK
JTAG_DOUT
JTAG_TMS
JTAG_TCK
JTAG_DIN
JTAG_DOUT
LEDG_DONE
SPI_DIN
SPI_CLK
SPI_MOSI
SPI_CSO_B
VCCSW
VREF_0V9
VTT_0V9
DDR2_A10
DDR2_RFU_BA2 VTT_0V9
VTT_0V9
DDR2_A11
DDR2_A6
DDR2_RFU_A15
DDR2_A4
DDR2_BA1
DDR2_BA0
VTT_0V9
DDR2_A7
DDR2_A12
DDR2_A3
DDR2_WEn
DDR2_RFU_A14
DDR2_A9
DDR2_A1
DDR2_A5
DDR2_A2
DDR2_CKE
DDR2_RFU_A13
DDR2_A8
DDR2_ODT
DDR2_RASn
DDR2_CSn
DDR2_CASn
DDR2_A0
VTT_0V9
VTT_0V9
VTT_0V9
CLKIN
VCCSW
1V2
VCCSW
VCCSW
VCCSW
VCCSW
VCCSW
1V2
1V8
VCCSW
VCCSW
VCCSW
1V8
VCCSW
RN2
CAT25-500JALF 50 Ohm
1
2
3
4
56
7
8
9
10
R1
27
C14
0.01 uF
0603
C42
0.1uF
0603
C20
0.1uF
0603
R5
4.7K
C73
22 uF
C63
0.1uF
R9
4.7K
R14
0
Y2
FXO-HC735-66.666MHZ
1
2
3
4
EN
GND
OUT
VDD
C62
2.2 uF
0603
C32
0.01uF
C22
22 uF
TANT
C74
0.1uF
Q3
IRLML6401
R8
4.7K
C15
2.2 uF
0603
C69
2.2 uF
0603
C23
4.7uF
0603
C71
0.01uF
J2
Traditional JTAG
1
2
3
4
5
6
R21 4.7K
R18
50
D2
GREEN
U4
M25P20
6
7
8
3
1
4
5
2
C
HOLD
VCC
W
S
VSS
>Din
<Dout
C66
0.01uF
C76
0.1uF
RN3
CAT25-500JALF 50 Ohm
1
2
3
4
56
7
8
9
10
U8
ST1S03 DFN6
3
2 1
4
5
6
SW
GND FB
VIN_SW
VIN_A
INHIBIT
J3
Xilinx Parallel Cable Header
1
2
3
4
5
6
C68
0.01uF
R30
100 5%
C72
2.2 uF
C13
0.1uF
R11
4.7K
R12
220K 5%
C75
0.1uF
U5E
XC3S200A_FT256
B1
B2
T15
B16
A15
A2
TDI
TMS
DONE
TDO
TCK
PROG_B
RN1
CAT25-500JALF 50 Ohm
1
2
3
4
56
7
8
9
10
C70
0.1uF
U5F
XC3S200A_FT256
A1
T1
F2
K2
C3
P3
E5
M5
F6
R6
B7
K7
G8
J8
H9
K9
G10
R10
B11
L11
E12
M12
C14
P14
G15
L15
A16
T16
L12
E11
M6
F5
K10
J9
G9
K8
H8
G7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
U7
TPS79318DBVR / SOT23-5
1
2
3 4
5
IN
GND
EN BYPASS
OUT
R15
49.9K 1%
R25 330
R10
4.7K
C64
0.01uF
U6
LP2997 SOIC8
4
1
2
6
7
5 8
3
VREF
GND
SD#
AVIN
PVIN
VDDQ VTT
VSENSE
L1
3.3uH
JP1
PROG
1
2
C67
0.1uF
C65
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Suspend powered by Vccaux (3.3V)
Mode 001 = SPI Flash
Variant Select =
111 (Fast Read
0x0B)
v1.2
Page 3
DLP-HS-FPGA
PRELIMINARY
HEARTBEAT
DNS
DDR2_DQS
DDR2_DQSn
DDR2_CKn
DDR2_CK
DDR2_CK
DDR2_CKn
DDR2_DQS
DDR2_DQSn
FDBK
USER_IO8_DP4
USER_IO3_DP1
USER_IO2_DN1
USER_IO34_DP17_RC
USER_IO32_DP16
USER_IO21_DN10
USER_IO33_DN16
USER_IO20_DP10
USER_IO29_DN14
USER_IO9_DN4
USER_IO28_DP14
DDR2_CKE
DDR2_CASn
DDR2_RASn
DDR2_WEn
DDR2_CSn
DDR2_BA1
DDR2_BA0
DDR2_A12
DDR2_A11
DDR2_A10
DDR2_A9
DDR2_A8
DDR2_A7
DDR2_A6
DDR2_A5
DDR2_A4
DDR2_A3
DDR2_A2
DDR2_A1
DDR2_A0
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_ODT
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_ODT
DDR2_WEn
DDR2_CASn
DDR2_A8
DDR2_CSn
DDR2_A1
DDR2_A2
DDR2_A6
DDR2_CKE
DDR2_A5
DDR2_A0
DDR2_BA1
DDR2_A4
DDR2_A7
DDR2_A3
DDR2_RASn
DDR2_BA0
DDR2_A9
DDR2_RFU_BA2
DDR2_RFU_A13
DDR2_RFU_A14
DDR2_RFU_A15
DDR2_RFU_BA0
DDR2_RFU_A14
VREF_0V9
VREF_0V9
VREF_0V9
VREF_0V9
VREF_0V9
DDR2_RFU_A15
DDR2_RFU_A13
VREF_0V9
FPGA_SUSPEND
USER_IO35_DN17_RC
USER_IO36_DN18_RC
USER_IO37_DP18_RC
USER_IO27_DP13
USER_IO26_DN13
USER_IO61_DP23
USER_IO62_DN23
USER_IO39_DP19
USER_IO31_DP15
USER_IO30_DN15
USER_IO38_DN19
USER_IO5_DN2_GC
USER_IO4_DP2_GC
USER_IO6_DP3_GC
USER_IO0_DP0
USER_IO1_DN0
SPI_MOSI
DDR2_IDONE
FPGA_AWAKE
DDR2_ERROR
CLKIN
FPGA_RESET
DDR2_DVALID
LEDR_HEARTB
USER_IO24_DN12
USER_IO25_DP12
USER_IO23_DN11
USER_IO22_DP11
SPI_INITUSER_IO13_DN6
USER_IO10_DP5
USER_IO12_DP6
USER_IO11_DN5
USER_IO15_DP7_GC
USER_IO14_DN7_GC
USER_IO17_DP8
USER_IO16_DN8
SPI_CSO_B
USER_IO7_DN3_GC
USER_IO18_DN9
USER_IO19_DP9
USER_IO40USER_IO41
USER_IO42
USER_IO43_DP20
USER_IO44_DN20
USER_IO45_GC
USER_IO46
USER_IO47
USER_IO48
USER_IO50
USER_IO51
USER_IO52
USER_IO53_DP21
USER_IO54_DN21
USER_IO55_DP22
USER_IO56_DN22
USER_IO57_RC
USER_IO58_RC
USER_IO59
USER_IO60
DDR2_ERROR
DDR2_DVALID
DDR2_IDONE
USER_IO49
FTDI_D4
FDTI_D7
FDTI_D2
FTDI_D5
FDTI_WR
FTDI_TXE
FDTI_D3
FTDI_SI
FDTI_D6
FTDI_D0
FTDI_RXF
FTDI_RD
FDTI_D1
SPI_CLK
SPI_DIN
1V8
1V8
VCCSW
VCCSW
VCCSW VCCSW
VCCSW
VCCSW
VCCSW
TP1 DDR2_ERROR
1
C35
0.01uF
D3
GREEN
U5B
XC3S200A_FT256
R16
N13
N14
R15
P15
P16
N16
K11
K12
M13
M14
L13
K13
M15
M16
L14
L16
J10
J11
J12
J13
K15
K14
K16
J16
H10 J15
E15
H12
F11
F12
C15
C16
D14
E13
D15
D16
G11
G12
F13
E14
F14
G13
F15
E16
G14
H13
F16
G16
H16
H15
H14
H11
J14
N15
SUSPEND
IO_L01P_1/HDC
IO_L01N_1/LDC2
IO_L02P_1/LDC1
IO_L02N_1/LDC0
IO_L03P_1/A0
IO_L03N_1/A1
IP_L04P_1
IP_L04N_1/VREF_1
IO_L05P_1
IO_L05N_1/VREF_1
IO_L06P_1/A2
IO_L06N_1/A3
IO_L07P_1/A4
IO_L07N_1/A5
IO_L08P_1/A6
IO_L08N_1/A7
IP_L09P_1/VREF_1
IP_L09N_1
IO_L10P_1/A8
IO_L10N_1/A9
IO_L11P_1/RHCLK0
IO_L11N_1/RHCLK1
IO_L12P_1/RHCLK2
IO_L12N_1/TRDY1/RHCLK3
IP_L13P_1 VCCO_1
VCCO_1
VCCO_1
IP_L25N_1
IP_L25P_1/VREF_1
IO_L24N_1/A25
IO_L24P_1/A24
IO_L23N_1/A23
IO_L23P_1/A22
IO_L22N_1/A21
IO_L22P_1/A20
IP_L21N_1
IP_L21P_1/VREF_1
IO_L20N_1/A19
IO_L20P_1/A18
IO_L19N_1/A17
IO_L19P_1/A16
IO_L18N_1/A15
IO_L18P_1/A14
IO_L17N_1/A13
IO_L17P_1/A12
IO_L16N_1/A11
IO_L16P_1/A10
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L14N_1/RHCLK5
IP_L13N_1
IO_L14P_1/RHCLK4
VCCO_1
C54
0.01uF
C59
0.1uF
C52
0.1uF
C28
0.01uF
C31
0.1uF
C57
0.1uF
C37
0.01uF
R26
330
JP2
SUSPEND
1
2
VIA UNUSED_K5
1
VIAUNUSED_J11 1
R23
4.7K
U5D
XC3S200A_FT256
C2
C1
D4
D3
D1
E1
E4
F4
E3
E2
G6
G5
F3
G4
F1
G1
G3
H4
H6
H5
G2
H1
H3
J3
H7
J7 M2
H2
D2
L6
L5
M4
N3
P2
R1
P1
N2
K6
K5
N1
M1
L4
M3
L3
K4
J6
J4
L2
L1
K1
K3
J1
J2 J5
IO_L01P_3
IO_L01N_3
IO_L02P_3
IO_L02N_3
IO_L03P_3
IO_L03N_3
IP_L04P_3
IP_L04N_3/VREF_3
IO_L05P_3
IO_L05N_3
IP_L06P_3
IP_L06N_3/VREF_3
IO_L07P_3
IO_L07N_3
IO_L08P_3
IO_L08N_3/VREF_3
IO_L09P_3
IO_L09N_3
IO_L10P_3
IO_L10N_3
IO_L11P_3/LHCLK0
IO_L11N_3/LHCLK1
IO_L12P_3/LHCLK2
IO_L12N_3/IRDY2/LHCLK3
IP_L13P_3
IP_L13N_3 VCCO_3
VCCO_3
VCCO_3
IP_L25N_3/VREF_3
IP_L25P_3
IO_L24N_3
IO_L24P_3
IO_L23N_3
IO_L23P_3
IO_L22N_3
IO_L22P_3
IP_L21N_3
IP_L21P_3
IO_L20N_3
IO_L20P_3
IO_L19N_3
IO_L19P_3
IO_L18N_3
IO_L18P_3
IO_L17N_3
IO_L17P_3
IO_L16N_3
IO_L16P_3/VREF_3
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4 VCCO_3
C27
0.1uF
R22100
TP2 DDR2_DVALID
1
U5C
XC3S200A_FT256
N4
P4
N5
R2
T2
R3
T3
L7
N6
P5
M7
T4
R5
T5
T6
N7
P6
P7
N8
R7
T7
M8
P8
T8
N9
P9 R12
M9
R8
R4
R14
T14
M11
P13
N12
R13
T13
P12
T12
L10
N11
P11
R11
T11
P10
T10
L9
M10
N10
T9
R9
L8
IO_L01P_2/M1
IO_L01N_2/M0
IP_2/VREF_2
IO_L02P_2/M2
IO_L02N_2/CSO_B
IO_L03P_2/RDWR_B
IO_L03N_2/VS2
IP_2
IO_L04P_2/VS1
IO_L04N_2/VS0
IP_2/VREF_2
IO_L05P_2
IO_L05N_2
IO_L06P_2/D7
IO_L06N_2/D6
IO_L07P_2
IO_L07N_2
IO_L08P_2/D5
IO_L08N_2/D4
IO_L09P_2/GCLK12
IO_L09N_2/GCLK13
IP_2/VREF_2
IO_L10P_2/GCLK14
IO_L10N_2/GCLK15
IO_L11P_2/GCLK0
IO_L11N_2/GCLK1 VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L20N_2/CCLK
IO_L20P_2/D0/DIN/MISO
IP_2/VREF_2
IO_L19N_2
IO_L19P_2
IO_L18N_2/D1
IO_L18P_2/D2
IO_L17N_2/D3
IO_L17P_2/INIT_B
IP_2/VREF_2
IO_L16N_2
IO_L16P_2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L14N_2/MOSI/CSI_B
IO_L14P_2
IP_2/VREF_2
IO_L13N_2
IO_L13P_2
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IP_2
C40
0.01uF
C55
0.1uF
C41
0.01uF
C38
0.01uF
C61
2.2 uF
0603
C29
0.01uF
C30
0.1uF
C56
0.01uF
C24
0.1uF
R20100
TP3 DDR2_IDONE
1
C50
2.2 uF
0603
VIA
UNUSED_R3
1
C44
0.1uF
C60
0.01uF
C53
0.1uF
C43
0.1uF
C58
0.1uF
U1
MT47H32M8BP-37E
C8
C2
D7
D3
F3
G7
F7
G8
G2
G3
H2
H8
H3
H7
J2
F8
J8
J3
J7
K2
K8
K3
K7
F2
E8
B7
A3
E3
D1
D9
B1
B9
A1
E9
H9
L1
A9
C1
C3B8
D2
B2
A7
C9D8
C7
L2
K9
J1
E7
A8
E1
G1
L8
L3
L7
E2
F9
B3
A2
DQ0
DQ1
DQ2
DQ3
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
CK#
A4
A5
A6
A7
A8
A9
A11
CKE
CK
DQS
VSS
VSS
DQ4
DQ5
DQ6
DQ7
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQVSSQ
VSSQ
VSSQ
VSSQ
VDDQVSSQ
VDDQ
A12
VSS
VSS
VSSDL
DQS#
VDDL
RFU_BA2
RFU_A13
RFU_A14
RFU_A15
VREF
ODT
DM
RDSQ#/NU
C21
0.01uF
C51
2.2 uF
0603
C7
0.1uF
R29 4.7K
C36
0.1uF
VIAUNUSED_E10 1
C45
0.1uF
U5A
XC3S200A_FT256
D13
C13
D12
B15
B14
C12
D11
A14
A13
B12
A12
D10
E10
C11
A11
F10
B10
A10
C10
D9
E9
C9
A9
C8
D8 B13
B9
E8
B5
D5
C4
E6
B3
A3
B4
A4
D6
C5
A5
C6
D7
F7
B6
A6
E7
F8
C7
A7
B8
A8
F9
IO_L01P_0
IO_L01N_0
IP_0
IO_L02P_0/VREF_0
IO_L02N_0
IO_L03P_0
IO_L03N_0
IO_L04P_0
IO_L04N_0
IO_L05P_0
IO_L05N_0
IO_L06P_0
IO_L06N_0/VREF_0
IO_L07P_0
IO_L07N_0
IP_0
IO_L08P_0
IO_L08N_0
IO_L09P_0/GCLK4
IO_L09N_0/GCLK5
IP_0/VREF_0
IO_L10P_0/GCLK6
IO_L10N_0/GCLK7
IO_L11P_0/GCLK8
IO_L11N_0/GCLK9 VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L20N_0/PUDC_B
IO_L20P_0/VREF_0
IP_0
IO_L19N_0
IO_L19P_0
IO_L18N_0
IO_L18P_0
IP_0
IO_L17N_0
IO_L17P_0
IO_L16N_0
IO_L16P_0
IP_0
IO_L15N_0
IO_L15P_0
IO_L14N_0/VREF_0
IO_L14P_0
IO_L13N_0
IO_L13P_0
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IP_0
C16
0.1uF
Rev. 1.7 (May 2011) 18 © DLP Design, Inc.
15.0 DISCLAIMER
© DLP Design, Inc., 2000-2011
Neither the whole nor any part of the information contained herein nor the product described in this
manual may be adapted or reproduced in any material or electronic form without the prior written
consent of the copyright holder.
This product and its documentation are supplied on an as-is basis, and no warranty as to their
suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any
claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory
rights are not affected. This product or any variant of it is not intended for use in any medical
appliance, device or system in which the failure of the product might reasonably be expected to result
in personal injury.
This document provides preliminary information that may be subject to change without notice.
16.0 CONTACT INFORMATION
DLP Design, Inc.
1605 Roma Lane
Allen, TX 75013
Phone: 469-964-8027
Fax: 415-901-4859
Email Sales: sales@dlpdesign.com
Email Support: support@dlpdesign.com
Website URL: http://www.dlpdesign.com
Mouser Electronics
Authorized Distributor
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