19-0011; Rev. 0; 6/92 MA MAIN 8V CMOS Switched-Capacitor General Description The MAX665 charge-pump voltage inverter converts a +1.5V to +8V input to a corresponding -1.5V to -8V output. Using only two low-cost capacitors to produce 100mA, the MAX665 replaces switching regulators, elim- inating inductors and their associated cost, size, and EMI. Greater than 90% efficiency over most of its load- current range combined with a 200uA typical operating current provides ideal performance for both battery-pow- ered and board-level voltage conversion applications. The MAX665 can also double the output voltage of an input power supply or battery, providing +9.35V at 100mA from a +5V input. A Frequency Control (FC) pin selects either 10kHz or 45kHz operation to optimize capacitor size and quiescent current. The oscillator frequency can also be adjusted with an external capacitor or driven with an external clock. The MAX665 is a pin-compatible high-current upgrade of the ICL7660. For an 8-pin SO version with a 5.5V maximum input voltage, refer to the MAX660 data sheet. The MAX665 is available in both 8-pin DIP and 16-pin wide SO packages in commercial, extended, and military temperature ranges. Applications Laptop Computers Medical Instruments Interface Power Supplies Handheld Instrurnents Op-Amp Power Supplies GaAs Power-Amp Bias Supplies Pin Configurations TOP VIEW ad Fe [1] ra | vt caPs [2] AAAXLAA [7 | OSC GND [3] MAX665 a 6] Lv cap- [4] [5 | OUT DIP Wide SO on Iasi page Voltage Converter Features @ 0.65V Loss at 100mA Load @ 6.5Q Output Impedance @ Pin-Compatible High-Current ICL7660 Upgrade @ Inverts or Doubles Input Supply Voltage @ Selectable Oscillator Frequency: 10kHz/45kHz @ 88% Conversion Efficiency at 100mA (I, to GND) @ 200A Operating Current @ +1.5V to +8V Supply Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX665CPA 0C to +70C 8 Plastic DIP MAX665CWE 0C to +70C 16 Wide SO MAX665C/D 0C to +70C Dice* MAX665EPA -40C to +85C 8 Plastic DIP MAX665EWE -40C to +85C 16 Wide SO MAX665MJA -5C to +125C 8 CERDIP * Dice are tested at +25C only. _______sCT ypical Operating Circuits CAP+ Osc f + 3] AAAI |, 2 7 +ViN 1,5V TO 8V 1 8 1 FC Ve INVERTED "S0uF CSN MAX66S Negative ee ee ee 150uF + VOUTAGEINVERTER = Lt 1N5817 PF DOUBLED ' 3 POSITIVE qe 160F aT aps osch Et ce + 150uF maa |, . +VIN ET Tenn Maxegs LV 25V 10 8 4 5 CAP- OUT POSITIVE VOLTAGE DOUBLER PIN NUMBERS REFER TO DIP PACKAGE. SMA AI SV Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature.MAX665 8V CMOS Switched-Capacitor Voitage Converter ABSOLUTE MAXIMUM RATINGS Supply Voltage (V+ to GND, or GND to OUT) ......... +8.5V LV Input Voltage .............. (OUT - 0.3V) to (V+ + 0.3V) FC and OSC Input Voltages .......... The Least Negative of (OUT - 0.3V) or (V+ - BV) to (V+ + 0.3V) OUT and V+ Continuous Output Current ............. 120mA Output Short-Circuit Duration to GND (Note 1} ......... 1 sec Continuous Power Dissipation (Ta = +70C) Operating Temperature Ranges: MAX665C 8 ee OC to +70C MAXG65E ee tee -40C to +85C MAX6G65MJA 2.6. ee ees -55C to +125C Storage Temperature Range .............. -65C to +160C Lead Temperature (soldering, 10sec) .............. +300C 8-Pin Plastic DIP (derate 9.09mW/"C above +70C) . 727mW 16-Pin Wide SO (derate 9.52mW/"C above +70C) .. 762mW 8-Pin CERDIP (derate 8.cCOmW/"C above +70C) .... 640mW Note 1: OUT may be shorted to GND for 1 sec without damage, but shorting OUT to V+ may damage the device. Stresses beyond those listed under "Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 5V, C1, C2 = 150uF, test circuit of Figure 1, FC = open, TA = TMIN to Tmax, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Inverter, LV = open 3 8 Operating Supply Voltage Ri = 1k Inverter, LV = GND 1.5 8 Vv Doubler, LV = OUT 2.5 8 Supply Current No load FC = open oe os A u urren oO m pp FC = V+ 1 3 Ta s +85C, OUT more negative than -4V 100 Output Current - mA Ta > +85C, OUT more negative than -3.8V 100 . Tas +85C 6.5 10 Output Resistance (Note 3) IL = 100mA 7 Q Ta > +85C 12 ; FC = open 10 Oscillator Frequency kHz FC = V+ 45 OSC Inout C f FC = open +1.1 WA nput Curren P FC = V+ +5 Ri = 1kQ connected between V+ and OUT 96 98 Power Efficiency Ri = 500 connected between OUT and GND 92 96 % IL = 160mA to GND 88 Voltage Conversion Efficiency No load 99 99.96 % Note 2: In the test circuit, capacitors C1 and C2 are 150uF, 0.20 maximum ESR, aluminum electrolytics (Maxim part # MAXC001). Capacitors with higher ESR may reduce output voltage and efficiency. Note 3: Specified output resistance is a combination of internal switch resistance and capacitor ESR. See Capacitor Selection section. 2 MIAXISVI8V CMOS Switched-Capacitor Voltage Converter All curves are generated using the test circuit of Figure 1 with V+ = 5V, LV = GND, FC = open, and Ta = +25C, Typical Operating Characteristics unless otherwise noted. The charge-pump frequency is 1 one-half the oscillator frequency. Test results are also V4 oT AAXLAA valid for doubler mode with GND = +5V, LV = OUT, and C1 2] MAX665 OUT = OV, unless otherwise noted; however, the input TS0HF 4 3 voltage is restricted to +2.5V to +8V. SUPPLY CURRENT vs. SUPPLY VOLTAGE 900 800 700 = 6 3 DOUBLER = 500 ae = Fag LV=OUT o > a 300 wz 200 LV = OPEN 100 3 = 10 20 30 40 50 60 70 80 SUPPLY VOLTAGE (V) EFFICIENCY vs. LOAD CURRENT V+=5.5V Ve= 4, EFFICIENCY (%) V+ =2.5V Va=1.5V 0 20 40 60 80 LOAD CURRENT (mA) 100 8 Is }_________________ 7 6 Noo oO 5 (+5V) = on Vout C2 + 150uF PIN NUMBERS REFER TO DIP PACKAGE. ~ Figure 1. MAX665 Test Circuit SUPPLY CURRENT OUTPUT VOLTAGE AND EFFICIENCY vs. OSCILLATOR FREQUENCY vs. LOAD CURRENT 10,000 100 1000 92 3 = ue & = 3 gs 100 = a 3 = 762 z 5 = 10 5 a o 68 MAX665 1 : 60 0.01 04 1 10 100 0 2 40 6 8 10 OSCILLATOR FREQUENCY (kHz) LOAD CURRENT (mA) OUTPUT VOLTAGE DROP FROM OUTPUT VOLTAGE SUPPLY VOLTAGE vs. LOAD CURRENT vs. OSCILLATOR FREQUENCY 5.0 a N arin N ILoap = 10mA = 45--+A } S S V tows ima 4 5 2 1A g = .40 ILoap = 80mA 5 S / > > = 5 E 5 = -35 < | V+ =5.5V = 30 0 2 8640 60 =6aSs100 010204 1 2 4 10 20.40 100 LOAD CURRENT (mA) OSCILLATOR FREQUENCY (kHz) 3 MAAXAIsIMAX665 8V CMOS Switched-Capacitor Voltage Converter Typical Operating Characteristics (continued) EFFICIENCY vs. OUTPUT SOURCE RESISTANCE OUTPUT SOURCE RESISTANCE ILLATOR FREQUENCY vs. SUPPLY VOLTAGE 16 vs. TEMPERATURE 100 15 96 = = pi % an S14 Ve= 1 VDC 2 s LA 88 = = 12 A _ ~ an ae 84 @ 9 a | 3 ao to = 10 | 2 8 8 weavoe [4 So 76 = 6 5 ra 2 Ba = uo 72 Ee Lt Lee 68 = 3 = 6 al aaa 6 ILoap= 1mA 3 2 Se V+ = SVDC 0 4 Oorozos 1 2 4 10 20 40 100 05 1.0 1520 2530 3540 45 5.0 55 -60 -40-20 0 20 40 60 80 100 120140 OSCILLATOR FREQUENCY (kHz) SUPPLY VOLTAGE (V) TEMPERATURE (C) OSCILLATOR FREQUENCY OSCILLATOR FREQUENCY OSCILLA sp __ TE SUPPLY VOLTAGE oy _* SUPPLY VOLTAGE pao Ewen LV GROUNDED wv GaounpeD [1 10 tae eT an _ = - = 3 LL 2 LV OPEN 3 SL eT ET worn | 5 HT = 2 & 30 2 a = a SB 6 z 3 = # ce FC = OPEN, OSC = OPEN = 20 = S 4 iz S = 5 FC = V4, OSC = OPEN 5 z 5 = oO = 5 2 2B 10 5 & & 0 0 0 1.0 15 20 2530 35 4045 50 55 10 15 20 25 3035 40 45 5055 -60 40-200 20 40 60 80 100 120 140 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V} TEMPERATURE (C) OSCILLATOR FREQUENCY OSCILLATOR FREQUENCY vs. TEMPERATURE vs. EXTERNAL CAPACITANCE 100 z Z 10 = > 3S a BY # = FC = V+, OSC = = i 4 < 5 01 2 Oo & 8 0 0.01 -60 -40 -20 0 20 40 60 80 100 120 140 1 5 10 100 10000 TEMPERATURE (C) CAPACITANCE (pF) 4 SVLALAISVI8V CMOS Switched-Capacitor Voitage Converter Pin Description PIN FUNCTION NAME DIP WIDE SO INVERTER DOUBLER Frequency Control for internal oscillator. FC = open, 1 2 FC fosc = 10KHz yp: FC = V+, fosc = 45kHz typ; FC has no Same as inverter effect when OSC pin is driven externally. 2 4 CAP+ | Positive Charge-Pump Capacitor Terminal Same as inverter Power-Supply Positive Volt- 3 6 GND | Power-Supply Ground Input age Input 4 8 CAP- | Negative Charge-Pump Capacitor Terminal Same as inverter 5 9 OUT | Output, Negative Voltage Power-Supply Ground Input Low-Voltage Operation Input. Tie LV to GND when input voltage : 6 11 LV is less than 3V. Above 3V, LV may be connected to GND or le LV must be tied to OUT for all open; when overdriving OSC, LV must be connected to GND. Input voltages. Oscillator Control Input. OSC is connected to an internal 15pF . 7 13 osc | capacitor. An external capacitor can be added to slow the oscil- Same as inverter however, do lator. Care must be taken to minimize stray capacitance. An ex-| Goubler mode ge ternal oscillator may also be connected to overdrive OSC. 8 16 V+ Power-Supply Positive Voltage Input Positive Voltage Output _ 1 3 ie N.C. | No Connect - not internally connected No Connect Detailed Description The MAX665 capacitive charge-pump circuit either inverts or doubles the input voltage. Two external capacitors are needed in the voltage inverting mode, while two capacitors and one diode are needed for the voltage doubling mode (see Typical Operating Circuits). For highest performance, use low effective series resistance (ESR) capacitors. See Capacitor Selection section for more details. When using the inverting mode with a supply voltage less than 3V, LV must be connected to GND. This bypasses the internal regulator circuitry and provides best performance in low-voltage applications. When using the inverter mode with a supply voltage above 3V, LV may be connected to GND or left open. The part is typically operated with LV grounded, but since LV may be left open, the substitution of the MAX665 for the ICL7660 is simplified. LV must be grounded when overdriving OSC (see Changing Oscillator Frequency section). Connect LV to OUT (for any supply voltage) when using the doubler mode. Applications Information Negative Voltage Converter The most common application of the MAX665 is as a charge-pump voltage inverter. The operating circuit MMAXAI VI uses only two external capacitors, C1 and C2 (see Typical Operating Circuits). In most applications these are low- cost, low-ESR, 150uF electrolytic capacitors (refer to Capacitor Selection section). Even though its output is not actively regulated, the MAX665 is very insensitive to load current changes. A typical output source resistance of 6.5Q means that with an input of +5V the output voltage is -5V under light load, and decreases to only -4.35V with a 100mA load. Output source resistance vs. temperature and supply voltage are shown in the Typica/ Operating Character- istics graphs. Output ripple voltage is calculated by noting that the output current supplied is solely from capacitor C2 during one-half of the charge-pump cycle. This introduces a peak-to-peak ripple of: : louT 2(fPumMP) (C2) + lour (ESRca) VRIPPLE = For a nominal fpumMP of 5kHz (one-half the nominal 10kHz oscillator frequency) where C2 = 150uF with an ESR of 0.2Q, ripple is approximately 90mV with a 100mA load current. If C2 is raised to 390uF, the ripple drops to 45mvV. S9OXVNMAX665 8V CMOS Switched-Capacitor Voltage Converter Positive Voltage Doubler The MAX665 operates in the voltage-doubling mode as shown in the Typical Operating Circuit. The external Schottky (1N5817) diode is for start-up only. The no-load output is 2x VIN and is not reduced by the diode forward drop. Changing Oscillator Frequency Four modes control the MAX665's clock frequency, as listed below: FC osc Oscillator Frequency Open Open 10kHz FC = V+ Open 45kHz Open or : See Typical Operating FC = V+ External capacitor | Characteristics Open External clock External clock frequency When FC and OSC are unconnected (open), the oscilla- tor runs at 10kHz typically. When FC is connected to V+, the charge and discharge current at OSC changes from 1.1pA to 5yA, thus increasing the oscillator frequency 4.5 times. In the third mode, the oscillator frequency is low- ered by connecting a capacitor between OSC and GND. FC can still multiply the frequency by 4.5 times in this mode. In the inverter mode, OSC may also be overdriven by an external clock source that swings within 100mV of V+ and GND. Any standard CMOS logic output is suitable for driving OSC. When OSC is overdriven, FC has no effect. Also, LV must be grounded when overdriving OSC. Do not overdrive the OSC pin in the voltage doubler mode. Note: In all modes, the frequency of the signal appearing at CAP+ and CAP- is one-half that of the oscillator. Also, an undesirable effect of lowering the oscillator frequency is the charge pumps effective output resistance. Compen- sate for this by increasing the value of the charge-pump capacitors (see Capacitor Selection section and Typical Operating Characteristics). Insome applications, the 5kHz output ripple frequency may be iow enough to interfere with other circuitry. If desired, the oscillator frequency can then be increased by using the FC pin or an external oscillator as described above. The output ripple frequency is one-half the selected oscillator frequency. Increasing the clock frequency increases the MAX665's quiescent current, but also allows smaller ca- pacitance values to be used for C1 and C2. Capacitor Selection Three factors (in addition to load current) affect the MAX665 output voltage drop from its ideal value: 1) MAX665 output resistance, 2) Pump (C1) and reservoir (C2) capacitor ESRs, 3) C1 and C2 capacitance. The voltage drop caused by MAX665 output resistance is the load current times the output resistance. Similarly, the loss in C2 is the load current times C2s ESR. The loss in C1, however, is larger because it handles currents that are greater than the load current during charge- pump operation. The voltage drop due to C1 is therefore about four times C1's ESR times the load current. Conse- quently, a low (or high) ESR capacitor has much greater impact on performance for C1 than for C2. Generally, as the MAX665s pump frequency increases, the capacitance values required to maintain comparable ripple and output resistance diminish proportionately. Figure 2 shows the total circuit output resistance for various capac- itor values (the pump and reservoir capacitors values are equal) and oscillator frequencies. These curves assume 0.25 capacitor ESRs and a 5.25Q MAX665 output resis- tance, which is why the flat portion of the curve shows a 6.52 (RO MAX665 + 4(ESRc1) + ESRc2) effective output resistance. Note: Ro = 5.25Q is used, rather than the typical 6.5Q, because the typical specification includes the effect of the capacitors ESRs in the test circuit. To reduce output ripple caused by the charge pump, increase reservoir capacitor C2 and/or reduce its ESR. Also, the reservoir capacitor must have low ESR if filtering high-frequency noise at the output is important. ow ~ = Fz B pg B ee 22222 ESR = 0.2502 FOR BOTH C1 AND C2 MAX665 OUTPUT SOURCE RESISTANCE ASSUMED TO BE TOTAL OUTPUT SOURCE RESISTANCE (Q) 1 2 4 6810 100 1000 CAPACITANCE (aF) Figure 2. Total Output Source Resistance vs. Ci and C2 Capacitance (CT = C2) MMA KI