VND5T035AK-E Double channel high-side driver with analog current sense for 24 V automotive applications Datasheet - production data Features Max transient supply voltage VCC 58 V Operating voltage range VCC 8 to 36 V Typ on-state resistance (per ch.) RON 35 m Current limitation (typ) ILIM 42 A Off-state supply current IS 2 A General - Very low standby current - 3.0 V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - Compliant with European directive 2002/95/EC - Fault reset standby pin (FR_Stby) Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Off-state open load detection - Output short to VCC detection - Overload and short to ground latch off - Thermal shutdown latch-off - Very low current sense leakage Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shutdown - Electrostatic discharge protection September 2013 This is information on a product in full production. 3RZHU662 ("1($'5 Application All types of resistive, inductive and capacitive loads Description The VND5T035AK-E is a monolithic device made using STMicroelectronics(R) VIPower(R) technology, intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes. The device integrates an analog current sense which delivers a current proportional to the load current. Fault conditions such as overload, overtemperature or short to VCC are reported via the current sense pin. Output current limitation protects the device in overload conditions. The device latches off in case of overload or thermal shutdown. The device is reset by a low level pass on the fault reset standby pin. A permanent low level on the inputs and on the fault reset standby pins disables all outputs and sets the device in standby mode. Doc ID 018942 Rev 5 1/31 www.st.com 1 Contents VND5T035AK-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 21 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 22 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/31 Doc ID 018942 Rev 5 VND5T035AK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 24 V; Tj = 25 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Openload detection (VFR_Stby = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 018942 Rev 5 3/31 List of figures VND5T035AK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. 4/31 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram PowerSSO-24 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tstby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Openload off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output stuck to VCC detection delay time at FRSTBY activation. . . . . . . . . . . . . . . . . . . . 14 Delay response time between rising edge of ouput current and rising edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 23 PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 24 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 24 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 018942 Rev 5 VND5T035AK-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC Signal Clamp Control & Diagnostic 2 Undervoltage IN1 Control & Diagnostic 1 Power Clamp DRIVER IN2 CH1 VON Limitation Over Temperature Current Limitation OFF-state Open-load FR_Stby VSENSEH CS1 Current Sense CH2 CS2 OUT2 LOGIC OUT1 OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) GND GAPGCFT00643 Table 1. Pin function Name VCC OUT1,2 Function Battery connection Power outputs GND Ground connection IN1,2 Voltage controlled input pins with hysteresis, CMOS compatible. They Control output switch state CS1,2 Analog current sense pins, they deliver a current proportional to the load current FR_Stby In case of latch-off for overtemperature/overcurrent condition, a low pulse on the FR_Stby pin is needed to reset the channel. The device enters in standby mode if all inputs and the FR_Stby pin are low. Doc ID 018942 Rev 5 5/31 Block diagram and pin description Figure 2. VND5T035AK-E Configuration diagram PowerSSO-24 (top view) 9&& 1& &6 ,1 1& )5B6WE\ *1' 1& ,1 &6 1& 9&& 287 287 287 287 287 287 287 287 287 287 287 287 7$% 9&& *$3*&)7 Table 2. Suggested connections for unused and not connected pins Connection / pin CurrentSense N.C. Output Input FR_Stby Floating Not allowed X(1) X X X To ground Through 10 K resistor X Not allowed Through 10 K resistor Through 10 K 1. X: do not care. 6/31 Doc ID 018942 Rev 5 VND5T035AK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC IFR_Stby OUTn FR_Stby VFR_Stby IOUTn VOUTn ISENSEn IINn VINn VCC VFn CSn INn VSENSEn GND IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions reported in this section for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 58 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current 40 A DC input current -1 to 10 mA Fault reset standby DC input current -1 to 1.5 mA 200 mA VCC - 58 to +VCC V 250 mJ IIN IFR_Stby -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (L = 2.3 mH; VBAT = 32 V; Tjstart = 150 C; IOUT = IlimL (typ)) Doc ID 018942 Rev 5 7/31 Electrical specifications Table 3. Absolute maximum ratings (continued) Symbol Value Unit 40 H Maximum strain inductance in short circuit condition RL = 300 m, VBAT = 32 V, Tjstart = 150 C, lOUT = ILMHmax VESD Electrostatic discharge (Human Body Model: R = 1.5 K; C = 100 pF) - IN1,2 - CS1,2 - FR_Stby - OUT1,2 - VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 C Storage temperature -55 to 150 C Tstg Thermal data Table 4. 8/31 Parameter Lsmax Tj 2.2 VND5T035AK-E Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case (max) (with one channel ON) 2 C/W Rthj-amb Thermal resistance junction-ambient (max) See Figure 27 C/W Doc ID 018942 Rev 5 VND5T035AK-E 2.3 Electrical specifications Electrical characteristics 8 V < VCC < 36 V; -40 C < Tj < 150 C, unless otherwise specified. Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit 8 24 36 V 5 V VCC Operating supply voltage VUSD Undervoltage shutdown 3.5 VUSDhyst Undervoltage shutdown hysteresis 0.5 RON Vclamp IS IL(off) VF On-state resistance(1) IOUT = 3 A; Tj = 25C 35 m IOUT = 3 A; Tj = 150C Clamp voltage IS = 20 mA Supply current Off-state output current Output - VCC diode voltage V 70 58 64 70 V Off-state; VCC = 24 V; Tj = 25C; VIN = VOUT = VSENSE = 0 V 2(2) 5(2) A On-state; VCC = 24 V; VIN = 5 V; IOUT = 0 A 4.2 6 mA 0.01 3 VIN = VOUT = 0 V; VCC = 24 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 24 V; Tj = 125C 0 A 5 -IOUT = 3 A; Tj = 150C 0.7 V Max. Unit 1. For each channel 2. PowerMOS leakage included Table 6. Symbol Switching (VCC = 24 V; Tj = 25 C) Parameter Test conditions Min. Typ. td(on) Turn-on delay time RL = 8 46 s td(off) Turn-off delay time RL = 8 54 s dVOUT/dt(on) Turn-on voltage slope RL = 8 0.55 V/s dVOUT/dt(off) Turn-off voltage slope RL = 8 0.46 V/s WON Switching energy losses during twon RL = 8 1 mJ WOFF Switching energy losses during twoff RL = 8 0.65 mJ Doc ID 018942 Rev 5 9/31 Electrical specifications Table 7. Symbol VND5T035AK-E Logic inputs Parameter VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Fault_reset_standby low level voltage IFR_Stby_L Low level fault_reset_standby current VFR_Stby_H Fault_reset_standby high level voltage IFR_Stby_H High level fault_reset_standby current (hyst) VFR_Stby_CL VIN = 0.9 V Max. Unit 0.9 V 1 A 2.1 V 10 0.25 IIN = 1 mA 7 -0.7 A 2.1 V 10 0.25 tstby Standby delay See Figure 5 15 -0.7 2 24 s 120 1200 s Treset definition )5B67%< ,1 287387 &6 2YHUORDG &KDQQHO *$3*&)7 Doc ID 018942 Rev 5 V V 7BUHVHW 10/31 A V 11 IFR_Stby = -1 mA Overload latch-off reset time See Figure 4 V 1 VFR_Stby = 2.1 V IFR_Stby = 15 mA (10 ms) V V 0.9 VFR_Stby = 0.9 V A V 5.5 Fault_reset_standby hysteresis voltage Fault_reset_standby clamp voltage Typ. VIN = 2.1 V treset Figure 4. Min. IIN = -1 mA VFR_Stby_L VFR_Stby Test conditions VND5T035AK-E Electrical specifications Figure 5. Tstby definition )5B6WGE\ ,1387Q ,*1' WVWE\ WVWE\ *$3*&)7 Table 8. Protections and diagnostics Symbol Parameter Test conditions IlimH DC short circuit current IlimL Short circuit current during thermal cycling TTSD Shutdown temperature Reset temperature TRS Thermal reset of status VDEMAG VON Typ. Max. Unit 30 42 55 A 55 A 5 V < VCC < 36 V TR THYST VCC = 24V Min. VCC = 24 V; TR < Tj < TTSD 10.5 150 175 TRS + 1 TRS + 5 A 200 135 Thermal hysteresis (TTSD-TR) C C C 7 C Turn-off output voltage clamp IOUT = 3 A; VIN = 0; L = 6 mH VCC - 58 VCC - 64 VCC - 70 V Output voltage drop limitation IOUT = 150 mA; Tj = -40C...+150C 25 mV Doc ID 018942 Rev 5 11/31 Electrical specifications Table 9. Current sense (8 V < VCC < 36 V) Symbol K1 dK1/K1(1) K2 dK2/K2(1) K3 dK3/K3(1) ISENSE0 VND5T035AK-E Parameter Test conditions Typ. Max. 1952 2080 2960 4150 3840 IOUT = 1 A; VSENSE = 2 V; Tj = -40C...150C Tj = 25C...150C Current sense ratio drift IOUT = 1 A; VSENSE = 2 V; Tj = -40C to 150C IOUT/ISENSE IOUT = 3 A; VSENSE = 4 V; Tj = -40C...150C Tj = 25C...150C Current sense ratio drift IOUT = 3 A; VSENSE = 4 V; Tj = -40C to 150C IOUT/ISENSE IOUT = 12 A; VSENSE = 4 V; Tj = -40C...150C Tj = 25C...150C Current sense ratio drift IOUT = 12 A; VSENSE = 4 V; Tj = -40C to 150C -5 5 % IOUT = 0 A; VSENSE = 0 V; VIN = 0 V; Tj = -40C...150C 0 1 A IOUT = 0 A; VSENSE = 0 V; VIN = 5 V; Tj = -40C...150C 0 2 A Analog sense leakage current Max analog sense output IOUT = 12 A; RSENSE = 3.9 K voltage VSENSEH Analog sense output voltage in fault condition(2) Analog sense output current in fault condition (2) -15 2490 2585 15 2930 -10 2770 2755 +10 2900 % 3440 3265 % 3125 3045 5 V VCC = 24 V; RSENSE = 3.9 K 7.5 8.5 9.5 V VCC = 24 V; VSENSE = 5 V 4.9 9 12 mA 200 400 s 250 s 20 s Delay response time tDSENSE2H from rising edge of INPUT pins VSENSE < 4 V; 0.2 A < IOUT < 12 A; ISENSE = 90 % of ISENSE max; (see Figure 6) Delay response time between rising edge of tDSENSE2H output current and rising edge of current sense VSENSE < 4 V; ISENSE = 90 % of ISENSEMAX; IOUT = 90 % of IOUTMAX; IOUTMAX = 3 A (see Figure 10) Delay response time tDSENSE2L from falling edge of INPUT pins VSENSE < 4 V; 0.2 A < IOUT < 12 A; ISENSE = 10 % of ISENSE max; (see Figure 6) 5 1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation, overtemperature and open load in off-state condition. 12/31 Unit IOUT/ISENSE VSENSE ISENSEH Min. Doc ID 018942 Rev 5 VND5T035AK-E Electrical specifications Table 10. Openload detection (VFR_Stby = 5 V) Symbol Test conditions Min. Openload off-state voltage detection threshold VIN = 0 V; 8 V < VCC < 36 V tDSTKON Output short circuit to VCC detection delay at turn off IL(off2) td_vol VOL Parameter Max. Unit 2 4 V See Figure 7 180 1800 s Off-state output current at VOUT = 4V VIN = 0 V; VSENSE = 0 V; VOUT rising from 0 V to 4 V -120 0 A Delay response from output rising edge to VSENSE rising edge in openload VOUT = 4 V; VIN = 0 V; VSENSE = 90 % of VSENSEH; RSENSE = 3.9 K 20 s See Figure 9; Input1,2 = low 50 s Output short circuit to tDFRSTK_ON VCC detection delay at FRSTBY activation Figure 6. Typ. Current sense delay characteristics ,1387 /2$'&855(17 6(16(&855(17 W'6(16(+ W'6(16(/ *$3*&)7 Figure 7. Openload off-state delay timing 9287!92/ 9,1 96(16(+ 9&6 W'67.21 *$3*&)7 Note: Vfr_stby = high Doc ID 018942 Rev 5 13/31 Electrical specifications Figure 8. VND5T035AK-E Switching characteristics 9287 W:RQ W:RII G9287GW RII G9287GW RQ WU WI W ,1387 7G RQ 7G RII W *$3*&)7 Figure 9. Output stuck to VCC detection delay time at FRSTBY activation )567%< 9VHQVH+ 9&6 W')567.B21 ,QSXW /RZ *$3*&)7 14/31 Doc ID 018942 Rev 5 VND5T035AK-E Electrical specifications Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense 9,1 W'6(16(+ W ,287 ,2870$; ,2870$; W ,6(16( ,6(16(0$; ,6(16(0$; W *$3*&)7 Figure 11. Output voltage drop limitation 9&&9287 7M & 7M & 7M & 921 ,287 921521 7 $*9 Doc ID 018942 Rev 5 15/31 Electrical specifications VND5T035AK-E Figure 12. Device behavior in overload condition WBUHVHW WBUHVHW )$8/7B5(6(7 ,1Q 287387Q 9VHQVH+ &6Q RYHUORDG RYHUORDGUHVHW RYHUORDGGLDJUHVHW 29(5/2$' &+$11(/Q 287387QDQG&6QFRQWUROOHGE\,1Q )$8/7B5(6(7IURPWRQRDFWLRQRQ&6QSLQ RYHUORDGODWFKRII,QQKLJK&6QKLJK )$8/7B5(6(7ORZ$1'7HPSFKDQQHOQRYHUORDGBUHVHWRYHUORDGODWFKUHVHWDIWHUWBUHVHW WR)$8/7B5(6(7ORZ$1',1QKLJKWKHUPDOF\FOLQJ&6QKLJK )$8/7B5(6(7KLJKODWFKRIIUHVHWGLVDEOHG WRRYHUORDGHYHQWDQG)$8/7B5(6(7KLJKODWFKRIIQRWKHUPDOF\FOLQJ WRRYHUORDGGLDJQRVWLFGLVDEOHGHQDEOHGE\WKHLQSXW RYHUORDGODWFKRIIUHVHWE\)$8/7B5(6(7 29(5/2$' WKHUPDOVKXWGRZQ25SRZHUOLPLWDWLRQ *$3*&)7 Table 11. Truth table Fault reset standby Input Output Sense Standby L L L 0 Normal operation X X L H L H 0 Nominal Overload X X L H L H 0 > Nominal Overtemperature / short to ground X L H L H H L Cycling Latched 0 VSENSEH VSENSEH Undervoltage X X L 0 L L H H H H 0 Short to VBAT L H X VSENSEH < Nominal Open load off-state (with pull-up) L H X L L H H H H 0 VSENSEH 0 Negative output voltage clamp X L Negative 0 Conditions 16/31 Doc ID 018942 Rev 5 VND5T035AK-E Electrical specifications Table 12. ISO 7637-2: 2004(E) Electrical transient requirements (part 1) Test levels (1) Number of pulses or test times Burst cycle/pulse repetition time Delays and impedance Test pulse III IV 1 - 450 V - 600 V 5000 pulses 0.5 s 5s 1 ms, 50 2a + 37 V + 50 V 5000 pulses 0.2 s 5s 50 s, 2 3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 s, 50 3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 s, 50 4 - 12 V - 16 V 1 pulse 100 ms, 0.01 5b(1) + 123 V + 174 V 1 pulse 350 ms, 1 1. Valid in case of external load dump clamp: 58 V maximum referred to ground. Table 13. Electrical transient requirements (part 2)(1) ISO 7637-2: 2004(E) Test level results Test pulse III IV 1 C C 2a C C 3a C C 3b(2) E E 3b(3) C C 4 C C 5b (4) C C 1. In order to guarantee the ISO transient classes a minimum 10K protection resistors are needed on logic pins 2. Without capacitor between VCC and GND. 3. With 10 nF between VCC and GND. 4. External load dump clamp, 58 V maximum, referred to ground. Table 14. Electrical transient requirements (part 3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 018942 Rev 5 17/31 Electrical specifications 2.4 VND5T035AK-E Electrical characteristics curves Figure 13. Off-state output current Figure 14. High-level input current ,ORII>$@ ,LK>X$@ 9FF 9 9LQ 9RXW 9LQ 9 7F> &@ 7F> &@ *$3*&)7 Figure 15. Input clamp voltage *$3*&)7 Figure 16. High-level input voltage 9LFO>9@ 9LK>9@ ,LQ P$ 7F> &@ 7F> &@ *$3*&)7 Figure 17. Low-level input voltage *$3*&)7 Figure 18. Input hysteresis voltage 9LO>9@ 9LK\VW>9@ 7F> &@ 18/31 *$3*&)7 Doc ID 018942 Rev 5 7F> &@ *$3*&)7 VND5T035AK-E Electrical specifications Figure 19. On-state resistance vs Tcase Figure 20. On-state resistance vs VCC 5RQ>P2KP@ 5RQ>P2KP@ 7F & 7F & 7F & ,RXW $ 9FF 9 7F & 7F> &@ ,RXW $ 9FF>9@ *$3*&)7 Figure 21. ILIMH vs Tcase *$3*&)7 Figure 22. Turn-on voltage slope ,OLP+>$@ G9RXWGW 2Q>9XV@ 9FF 9 5/ 2KP 9FF 9 7F> &@ *$3*&)7 7F> &@ *$3*&)7 Figure 23. Turn-off voltage slope G9RXWGW 2II>9XV@ 9FF 9 5/ 2KP 7F> &@ *$3*&)7 Doc ID 018942 Rev 5 19/31 Application information 3 VND5T035AK-E Application information Figure 24. Application schematic 9 9&& 5SURW )5B6WE\ 'OG 0&8 5SURW ,1 5SURW &6 287 *1' 56(16( &H[W 9*1' '*1' *$3*&)7 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This solution can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND 600 mV / (IS(on)max). 2. RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0: during reverse battery situations) is: PD = (-VCC)2 / RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below). 20/31 Doc ID 018942 Rev 5 VND5T035AK-E 3.1.2 Application information Solution 2: diode (DGND) in the ground line A resistor (RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/2 table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient is present on the VCC line, the control pins are pulled negative. ST suggests that a resistor (Rprot) have to be inserted in line to prevent the microcontroller I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of the microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= -600 V and Ilatchup 20 mA; VOHC 4.5 V 30 k Rprot 180 k. Recommended Rprot value is 60 k. Doc ID 018942 Rev 5 21/31 Application information 3.4 VND5T035AK-E Maximum demagnetization energy (VCC = 24 V) Figure 25. Maximum turn-off current versus inductance $ % & , $ / P+ *$3*&)7 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse 9,1,/ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ W *$3*&)7 Note: 22/31 Values are generated with RL =0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 018942 Rev 5 VND5T035AK-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSSO-24 thermal data Figure 26. PowerSSO-24 PC board . ("1($'5 1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 m (front and back side), Copper areas: from minimum pad lay-out to 8 cm2). Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) 57+MBDPE &: 3&%&XKHDWVLQNDUHD FP *$3*&)7 Doc ID 018942 Rev 5 23/31 Package and PCB thermal data VND5T035AK-E Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON) =7+ &: $ & % 7LPH V *$3*&)7 A: Cu = Footprint B: Cu = 2 cm2 C: Cu = 8 cm2 Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24 ("1($'5 1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered 24/31 Doc ID 018942 Rev 5 VND5T035AK-E Package and PCB thermal data Equation 1: Pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T Table 15. Thermal parameters Area/island (cm2) Footprint 2 8 R1 (C/W) 0,5 -- -- R2 (C/W) 0.75 -- -- R3 (C/W) 1 -- -- R4 (C/W) 7.7 -- -- R5 (C/W) 9 9 8 R6 (C/W) 28 17 10 R7 (C/W) 0,5 -- -- R8 (C/W) 0.75 -- -- C1 (W.s/C) 0,005 -- -- C2 (W.s/C) 0,05 -- -- C3 (W.s/C) 0,1 -- -- C4 (W.s/C) 0,5 -- -- C5 (W.s/C) 1 4 9 C6 (W.s/C) 2.2 5 17 C7 (W.s/C) 0,005 -- -- C8 (W.s/C) 0,05 -- -- Doc ID 018942 Rev 5 25/31 Package and packing information VND5T035AK-E 5 Package and packing information 5.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-24 package information Figure 30. PowerSSO-24 package dimensions 26/31 Doc ID 018942 Rev 5 VND5T035AK-E Package and packing information Table 16. PowerSSO-24 mechanical data Millimeters Symbol Min. Typ. Max. A 2.15 2.47 A2 2.15 2.40 a1 0 0.075 b 0.33 0.51 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.8 e3 8.8 G 0.1 G1 0.06 H 10.1 10.5 h 0.4 k L 5 0.55 N 0.85 10 X 4.1 4.7 Y 6.5 7.1 Doc ID 018942 Rev 5 27/31 Package and packing information 5.3 VND5T035AK-E PowerSSO-24 packing information Figure 31. PowerSSO-24 tube shipment (no suffix) C Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A GAPGCFT00002 Figure 32. PowerSSO-24 tape and reel shipment (suffix "TR") 5HHOGLPHQVLRQV %DVH4W\ %XON4W\ $ PD[ % PLQ & ) * 1 PLQ 7 PD[ 7DSHGLPHQVLRQV $FFRUGLQJWR(OHFWURQLF,QGXVWULHV$VVRFLDWLRQ (,$ 6WDQGDUGUHY$)HE 7DSHZLGWK 7DSH+ROH6SDFLQJ &RPSRQHQW6SDFLQJ +ROH'LDPHWHU +ROH'LDPHWHU +ROH3RVLWLRQ &RPSDUWPHQW'HSWK +ROH6SDFLQJ : 3 3 ' ' PLQ ) . PD[ 3 $OOGLPHQVLRQVDUHLQPP (QG 6WDUW 7R S FRYHU WDSH 1RFRPSRQHQWV &RPSRQHQWV PPPLQ 1RFRPSRQHQWV PPPLQ (PSW\FRPSRQHQWVSRFNHWV VDOHGZLWKFRYHUWDSH 8VHUGLUHFWLRQRIIHHG ("1($'5 28/31 Doc ID 018942 Rev 5 VND5T035AK-E 6 Order codes Order codes Table 17. Device summary Order codes Package PowerSSO-24 Tube Tape and reel VND5T035AK-E VND5T035AKTR-E Doc ID 018942 Rev 5 29/31 Revision history 7 VND5T035AK-E Revision history Table 18. 30/31 Document revision history Date Revision Changes 21-Sep-2011 1 Initial release. 19-Oct-2011 2 Updated Table 2: Suggested connections for unused and not connected pins Added note on Table 13: Electrical transient requirements (part 2) 26-Oct-2011 3 Changed document status from preliminary data to definitive datasheet 13-Mar-2012 4 Updated Figure 13: Off-state output current Updated Section 3.4: Maximum demagnetization energy (VCC = 24 V) 18-Sep-2013 5 Updated Disclaimer Doc ID 018942 Rev 5 VND5T035AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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