This is information on a product in full production.
September 2013 Doc ID 018942 Rev 5 1/31
1
VND5T035AK-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Datasheet − production data
Features
■General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
■Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Off-state open load detection
– Output short to VCC detection
– Overload and short to ground latch off
– Thermal shutdown latch-off
– Very low current sense leakage
■Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shutdown
– Electrostatic discharge protection
Application
All types of resistive, inductive and capacitive
loads
Description
The VND5T035AK-E is a monolithic device made
using STMicroelectronics® VIPower® technology,
intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes.
The device integrates an analog current sense
which delivers a current proportional to the load
current.
Fault conditions such as overload,
overtemperature or short to VCC are reported via
the current sense pin.
Output current limitation protects the device in
overload conditions. The device latches off in
case of overload or thermal shutdown.
The device is reset by a low level pass on the fault
reset standby pin.
A permanent low level on the inputs and on the
fault reset standby pins disables all outputs and
sets the device in standby mode.
Max transient supply voltage VCC 58 V
Operating voltage range VCC 8 to 36 V
Typ on-state resistance (per ch.) RON 35 mΩ
Current limitation (typ) ILIM 42 A
Off-state supply current IS2 µA
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Contents VND5T035AK-E
2/31 Doc ID 018942 Rev 5
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 21
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 22
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VND5T035AK-E List of tables
Doc ID 018942 Rev 5 3/31
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 24 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Openload detection (VFR_Stby = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures VND5T035AK-E
4/31 Doc ID 018942 Rev 5
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram PowerSSO-24 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Tstby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Openload off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Output stuck to VCC detection delay time at FRSTBY activation. . . . . . . . . . . . . . . . . . . . 14
Figure 10. Delay response time between rising edge of ouput current and rising edge of current
sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 23
Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 24
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 24
Figure 30. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 31. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VND5T035AK-E Block diagram and pin description
Doc ID 018942 Rev 5 5/31
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
VCC Battery connection
OUT1,2 Power outputs
GND Ground connection
IN1,2
Voltage controlled input pins with hysteresis, CMOS compatible. They Control output
switch state
CS1,2 Analog current sense pins, they deliver a current proportional to the load current
FR_Stby
In case of latch-off for overtemperature/overcurrent condition, a low pulse on the
FR_Stby pin is needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.
Control & Diagnostic 2
VCC
CH1
LOGIC
DRIVER
Current
Limitation
Power
Clamp
Over
Temperature
Undervoltage
CH2
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
IN1
IN2
CS1
CS2
FR_Stby
GND
OUT2
OUT1
Signal Clamp
GAPGCFT00643
Current
Sense
VSENSEH
Control & Diagnostic 1
OFF-state
Open-load
VON
Limitation
Block diagram and pin description VND5T035AK-E
6/31 Doc ID 018942 Rev 5
Figure 2. Configuration diagram PowerSSO-24 (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin CurrentSense N.C. Output Input FR_Stby
Floating Not allowed X(1)
1. X: do not care.
XX X
To ground Through 10 KΩ
resistor X Not allowed Through 10 KΩ
resistor Through 10 KΩ
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VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 7/31
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in the Ta bl e 3 may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to the conditions reported in this section for extended periods may affect
device reliability.
I
S
I
GND
V
CC
V
CC
OUTn
I
OUTn
CSn
I
SENSEn
INn
I
INn
GND
FR_Stby
V
FR_Stby
V
INn
V
SENSEn
V
OUTn
V
Fn
I
FR_Stby
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 58 V
-VCC Reverse DC supply voltage 0.3 V
-IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current 40 A
IIN DC input current -1 to 10 mA
IFR_Stby Fault reset standby DC input current -1 to 1.5 mA
-ICSENSE DC reverse CS pin current 200 mA
VCSENSE Current sense maximum voltage VCC -58 to
+VCC
V
EMAX
Maximum switching energy
(L = 2.3 mH; VBAT =32V; T
jstart = 150 °C; IOUT =I
limL (typ))250 mJ
Electrical specifications VND5T035AK-E
8/31 Doc ID 018942 Rev 5
2.2 Thermal data
Lsmax
Maximum strain inductance in short circuit condition
RL=300mΩ, VBAT =32V, T
jstart = 150 °C, lOUT =I
LMHmax
40 µH
VESD
Electrostatic discharge
(Human Body Model: R = 1.5 KΩ; C = 100 pF)
–IN
1,2
–CS
1,2
–FR_Stby
–OUT
1,2
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case (max) (with one channel ON) 2 °C/W
Rthj-amb Thermal resistance junction-ambient (max) See Figure 27 °C/W
VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 9/31
2.3 Electrical characteristics
8V<V
CC <36V; -40°C<T
j< 150 °C, unless otherwise specified.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC
Operating supply
voltage 82436 V
VUSD Undervoltage shutdown 3.5 5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.5 V
RON On-state resistance(1)
1. For each channel
IOUT = 3 A; Tj= 25°C 35 mΩ
IOUT = 3 A; Tj= 150°C 70
Vclamp Clamp voltage IS= 20 mA 58 64 70 V
ISSupply current
Off-state; VCC =24V; T
j= 25°C;
VIN =V
OUT =V
SENSE =0V 2(2)
2. PowerMOS leakage included
5(2) µA
On-state; VCC =24V; V
IN =5V;
IOUT =0A 4.2 6 mA
IL(off) Off-state output current
VIN =V
OUT =0V; V
CC =24V;
Tj=25°C 00.01 3
µA
VIN =V
OUT =0V; V
CC =24V;
Tj=125°C 05
VF
Output - VCC diode
voltage -IOUT = 3 A; Tj= 150°C 0.7 V
Table 6. Switching (VCC =24V; T
j=25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL= 8 Ω46 µs
td(off) Turn-off delay time RL= 8 Ω54 µs
dVOUT/dt(on) Turn-on voltage slope RL= 8 Ω0.55 V/µs
dVOUT/dt(off) Turn-off voltage slope RL= 8 Ω0.46 V/µs
WON
Switching energy losses
during twon
RL= 8 Ω1mJ
WOFF
Switching energy losses
during twoff
RL= 8 Ω0.65 mJ
Electrical specifications VND5T035AK-E
10/31 Doc ID 018942 Rev 5
Figure 4. Treset definition
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN = 0.9 V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN = 1 mA 5.5 7 V
IIN = -1 mA -0.7 V
VFR_Stby_L
Fault_reset_standby low
level voltage 0.9 V
IFR_Stby_L
Low level
fault_reset_standby current VFR_Stby = 0.9 V 1 µA
VFR_Stby_H
Fault_reset_standby high
level voltage 2.1 V
IFR_Stby_H
High level
fault_reset_standby current VFR_Stby = 2.1 V 10 µA
VFR_Stby
(hyst)
Fault_reset_standby
hysteresis voltage 0.25 V
VFR_Stby_CL
Fault_reset_standby clamp
voltage
IFR_Stby = 15 mA (10 ms) 11 15 V
IFR_Stby = -1 mA -0.7 V
treset Overload latch-off reset time See Figure 4 224µs
tstby Standby delay See Figure 5 120 1200 µs
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VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 11/31
Figure 5. Tstby definition
Table 8. Protections and diagnostics
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC = 24V 30 42 55 A
5V<V
CC <36V 55 A
IlimL
Short circuit current
during thermal cycling VCC = 24 V; TR<T
j<T
TSD 10.5 A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature TRS + 1 TRS + 5 °C
TRS Thermal reset of status 135 °C
THYST
Thermal hysteresis
(TTSD-TR)7°C
VDEMAG
Turn-off output voltage
clamp
IOUT = 3 A; VIN = 0;
L=6mH VCC - 58 VCC - 64 VCC - 70 V
VON
Output voltage drop
limitation
IOUT = 150 mA;
Tj= -40°C...+150°C 25 mV
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Electrical specifications VND5T035AK-E
12/31 Doc ID 018942 Rev 5
Table 9. Current sense (8 V < VCC <36V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K1IOUT/ISENSE
IOUT = 1 A; VSENSE = 2 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
1952
2080 2960 4150
3840
dK1/K1(1)
1. Parameter guaranteed by design; it is not tested.
Current sense ratio drift IOUT = 1 A; VSENSE = 2 V;
Tj= -40°C to 150°C -15 15 %
K2IOUT/ISENSE
IOUT = 3 A; VSENSE = 4 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2490
2585 2930 3440
3265
dK2/K2(1) Current sense ratio drift IOUT = 3 A; VSENSE = 4 V;
Tj= -40°C to 150°C -10 +10 %
K3IOUT/ISENSE
IOUT = 12 A; VSENSE = 4 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2770
2755 2900 3125
3045
dK3/K3(1) Current sense ratio drift IOUT = 12 A; VSENSE = 4 V;
Tj= -40°C to 150°C -5 5 %
ISENSE0
Analog sense leakage
current
IOUT = 0 A; VSENSE = 0 V;
VIN = 0 V; Tj= -40°C...150°C 01µA
IOUT = 0 A; VSENSE = 0 V;
VIN = 5 V; Tj= -40°C...150°C 02µA
VSENSE
Max analog sense output
voltage IOUT = 12 A; RSENSE =3.9KΩ5V
VSENSEH
Analog sense output
voltage in fault
condition(2)
2. Fault condition includes: power limitation, overtemperature and open load in off-state condition.
VCC =24V; R
SENSE = 3.9 KΩ7.5 8.5 9.5 V
ISENSEH
Analog sense output
current in fault condition
(2)
VCC = 24 V; VSENSE = 5 V 4.9 9 12 mA
tDSENSE2H
Delay response time
from rising edge of
INPUT pins
VSENSE <4V;
0.2 A < IOUT <12A;
ISENSE =90% of I
SENSE max;
(see Figure 6)
200 400 µs
ΔtDSEN
SE
2H
Delay response time
between rising edge of
output current and rising
edge of current sense
VSENSE <4V;
ISENSE = 90 % of ISENSEMAX;
IOUT =90% of I
OUTMAX;
IOUTMAX = 3 A (see Figure 10)
250 µs
tDSENSE2L
Delay response time
from falling edge of
INPUT pins
VSENSE <4V;
0.2 A < IOUT <12A;
ISENSE =10% of I
SENSE max;
(see Figure 6)
520µs
VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 13/31
Figure 6. Current sense delay characteristics
Figure 7. Openload off-state delay timing
Note: Vfr_stby = high
Table 10. Openload detection (VFR_Stby =5V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VOL
Openload off-state
voltage detection
threshold
VIN =0V; 8V<V
CC <36V 2 4 V
tDSTKON
Output short circuit to
VCC detection delay at
turn off
See Figure 7 180 1800 µs
IL(off2)
Off-state output current
at VOUT = 4V
VIN =0V; V
SENSE =0V;
VOUT rising from 0 V to 4 V -120 0 µA
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
openload
VOUT =4V; V
IN =0V;
VSENSE = 90 % of VSENSEH;
RSENSE =3.9K
20 µs
tDFRSTK_ON
Output short circuit to
VCC detection delay at
FRSTBY activation
See Figure 9; Input1,2 = low 50 µs
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Electrical specifications VND5T035AK-E
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Figure 8. Switching characteristics
Figure 9. Output stuck to VCC detection delay time at FRSTBY activation
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VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 15/31
Figure 10. Delay response time between rising edge of ouput current and rising
edge of current sense
Figure 11. Output voltage drop limitation
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Figure 12. Device behavior in overload condition
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Table 11. Truth table
Conditions Fault reset
standby Input Output Sense
Standby L L L 0
Normal operation X
X
L
H
L
H
0
Nominal
Overload X
X
L
H
L
H
0
> Nominal
Overtemperature /
short to ground
X
L
H
L
H
H
L
Cycling
Latched
0
VSENSEH
VSENSEH
Undervoltage X X L 0
Short to VBAT
L
H
X
L
L
H
H
H
H
0
VSENSEH
< Nominal
Open load off-state
(with pull-up)
L
H
X
L
L
H
H
H
H
0
VSENSEH
0
Negative output
voltage clamp X L Negative 0
VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 17/31
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
Test levels (1) Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III IV
1 - 450 V - 600 V 5000
pulses 0.5 s 5 s 1 ms, 50 Ω
2a + 37 V + 50 V 5000
pulses 0.2 s 5 s 50 µs, 2 Ω
3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 - 12 V - 16 V 1 pulse 100 ms, 0.01 Ω
5b(1)
1. Valid in case of external load dump clamp: 58 V maximum referred to ground.
+ 123 V + 174 V 1 pulse 350 ms, 1 Ω
Table 13. Electrical transient requirements (part 2)(1)
1. In order to guarantee the ISO transient classes a minimum 10KΩ protection resistors are needed on logic
pins
ISO 7637-2:
2004(E)
Test pulse
Test level results
III IV
1C C
2a C C
3a C C
3b(2)
2. Without capacitor between VCC and GND.
EE
3b(3)
3. With 10 nF between VCC and GND.
CC
4C C
5b (4)
4. External load dump clamp, 58 V maximum, referred to ground.
CC
Table 14. Electrical transient requirements (part 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Electrical specifications VND5T035AK-E
18/31 Doc ID 018942 Rev 5
2.4 Electrical characteristics curves
Figure 13. Off-state output current Figure 14. High-level input current
Figure 15. Input clamp voltage Figure 16. High-level input voltage
Figure 17. Low-level input voltage Figure 18. Input hysteresis voltage
VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 19/31
Figure 19. On-state resistance vs Tcase Figure 20. On-state resistance vs VCC
Figure 21. ILIMH vs Tcase Figure 22. Turn-on voltage slope
Figure 23. Turn-off voltage slope
Application information VND5T035AK-E
20/31 Doc ID 018942 Rev 5
3 Application information
Figure 24. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (RGND only)
This solution can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600 mV / (IS(on)max).
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD= (-VCC)2/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in case of several high
side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
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VND5T035AK-E Application information
Doc ID 018942 Rev 5 21/31
3.1.2 Solution 2: diode (DGND) in the ground line
A resistor (RGND =4.7kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient is present on the VCC line, the
control pins are pulled negative. ST suggests that a resistor (Rprot) have to be inserted in
line to prevent the microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of the
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the
latch-up limit of microcontroller I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= -600 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V
30 kΩ ≤ Rprot ≤ 180 kΩ.
Recommended Rprot value is 60 kΩ.