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FEATURES APPLICATIONS
D (SOIC) OR PW (TSSOP) PACKAGE
(TOP VIEW)
CATHODE
3OUT
3IN−
3IN+
1OUT
1IN−
1IN+
VCC+
2OUT
2IN−
2IN+
VREF
VCC–
4IN+
4IN−
4OUT
116
7
6
5
4
3
2
89
10
11
12
13
14
15
+
–+–
+
–+–
COMP COMP
AMP AMP
DESCRIPTION/ORDERING INFORMATION
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
•Switch-Mode Power Supplies•OPERATIONAL AMPLIFIERS
•Battery Chargers– Low Supply Current …200 µA/A
•Voltage and Current Sensing– Medium Speed …2.1 MHz
•Power-Good, Overvoltage, Undervoltage,– Low-Level Output Voltage Close to
Overcurrent DetectionV
CC–
…0.1 V Typ (R
L
= 10 k Ω)
•Window Comparators– Input Common-Mode Voltage Range
•Alarms, Detectors, and SensorsIncludes Ground•COMPARATORS
– Low Supply Current …200 µA/A(V
CC
= 5 V)– Input Common-Mode Voltage RangeIncludes Ground– Low Output Saturation Voltage …Typically 250 mV (I
sink
= 4 mA)•VOLTAGE REFERENCE
– Adjustable Output Voltage …V
REF
to 36 V– Sink Current Capability …1 mA to 100 mA– 0.4% (A Grade) and 1% (Standard Grade)Precision
– Latch-Up Immunity
The TSM102 and TMS102A combine the building blocks of a dual operational amplifier, a dual comparator, anda precision voltage reference, all of which often are used to implement a wide variety of power-managementfunctions, including overcurrent detection, undervoltage/overvoltage detection, power-good detection, windowcomparators, error amplifiers, etc. Additional applications include alarm and detector/sensor applications.
The TSM102A offers a tight V
REF
tolerance of 0.4% at 25 °C. The TSM102 and TSM102A are characterized foroperation from –40 °C to 85 °C.
ORDERING INFORMATION
MAX V
REFT
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKINGTOLERANCE (25 °C)
Tube of 75 TSM102AIDSOIC – D TSM102AIReel of 2500 TSM102AIDRA grade:
0.4% precision
Tube of 90 TSM102AIPWTSSOP – PW SN102AIReel of 2000 TSM102AIPWR–40 °C to 85 °C
Tube of 75 TSM102IDSOIC – D TSM102IReel of 2500 TSM102IDRStandard grade:1% precision
Tube of 90 TSM102IPWTSSOP – PW SN102IReel of 2000 TSM102IPWR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
Total Device Electrical Characteristics
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
over free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage 36 VV
ID
Input differential voltage 36 VV
I
Input voltage range –0.3 36 VI
KA
Voltage reference cathode current 100 mAD package 73θ
JA
Package thermal impedance
(2) (3)
°C/WPW package 108T
J
Maximum junction temperature 150 °CT
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Maximum power dissipation is a function of T
J
(max), θ
JA
, and T
A
. The maximum allowable power dissipation at any allowable ambienttemperature is P
D
= (T
J
(max) – T
A
)/ θ
JA
. Selecting the maximum of 150 °C can affect reliability.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC+
– V
CC–
Supply voltage 3 30 VV
ID
Comparator differential input voltage V
CC+
– V
CC–
VV
KA
Cathode-to-anode voltage V
REF
36 VI
K
Reference cathode current 1 100 mAT
A
Operating free-air temperature –40 85 °C
PARAMETER TEST CONDITIONS T
A
MIN TYP MAX UNIT
25 °C 0.8 1.5Total supply current,I
CC
V
CC+
= 5 V, V
CC–
= 0 V, No load mAexcluding reference cathode current
Full range 2
2
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Operational Amplifier Electrical Characteristics
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
V
CC+
= 5 V, V
CC–
= GND, R1 connected to V
CC
/2 (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
MIN TYP MAX UNIT
25 °C 1 4.5V
IO
Input offset voltage mVFull range 6.5αV
IO
Input offset voltage drift 25 °C 10 µV/ °C25 °C 5 20I
IO
Input offset current nAFull range 4025 °C 20 100I
IB
Input bias current nAFull range 20025 °C 50 100V
CC+
= 30 V, R1 = 10 k Ω,A
VD
Large-signal voltage gain V/mVV
O
= 5 V to 25 V
Full range 25k
SVR
Supply-voltage rejection ratio V
CC+
= 5 V to 30 V 25 °C 80 100 dB25 °C V
CC–
V
CC+
– 1.8V
ICM
Input common-mode voltage VFull range V
CC–
V
CC+
– 2.2V
CC+
= 30 V,CMRR Common-mode rejection ratio 25 °C 70 90 dBV
ICM
= 0 V to V
CC+
– 1.8 V
Source 3 6I
SC
Short-circuit current V
ID
=±1 V, V
O
= 2.5 V 25 °C mASink 3 625 °C 27 28V
OH
High-level output voltage V
CC+
= 30 V, R
L
= 10 k ΩVFull range 2625 °C 130 170V
OL
Low-level output voltage R
L
= 10 k ΩmVFull range 200V
CC
=±15 V, C
L
= 100 pF,SR Slew rate 25 °C 1.3 2 V/ µsV
I
=±10 V, R
L
= 10 k ΩGBW Gain bandwidth product R
L
= 10 k Ω, C
L
= 100 pF, f = 100 kHz 25 °C 1.4 2.1 MHzΦm Phase margin R
L
= 10 k Ω, C
L
= 100 pF 25 °C 45 °THD Total harmonic distortion 25 °C 0.01 %V
n
Equivalent input noise voltage f = 1 kHz 25 °C 19 nV/ √Hz
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Comparator Electrical Characteristics
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
V
CC+
= 5 V, V
CC–
= GND (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
MIN TYP MAX UNIT
25 °C 5V
IO
Input offset voltage mVFull range 9Comparator differentialV
ID
Full range V
CC+
Vinput voltage
25 °C 50I
IO
Input offset current nAFull range 15025 °C 250I
IB
Input bias current nAFull range 40025 °C 0.1 nAI
OH
High-level output current V
ID
= 1 V, V
CC
= V
O
= 30 V
Full range 1 µA25 °C 250 400V
OL
Low-level output voltage V
ID
= –1 V, I
sink
= 4 mA mVFull range 700V
CC+
= 15 V, R1 = 15 k Ω,A
VD
Large-signal voltage gain 25 °C 200 V/mVV
O
= 1 V to 11 VI
sink
Output sink current V
O
= 1.5 V, V
ID
= –1 V 25 °C 6 16 mA25 °C 0 V
CC+
– 1.5Input common-modeV
ICM
Vvoltage range
Full range 0 V
CC+
– 2t
RESP
Response time
(1)
R1 = 5.1 k Ωto V
CC+
, V
REF
= 1.4 V 25 °C 1.3 µsR1 = 5.1 k Ωto V
CC+
, V
REF
= 1.4 V,t
RESP,large
Large-signal response time 25 °C 300 nsV
I
= TTL
(1) The response-time specification is for 100-mV input step with 5-mV overdrive. For larger overdrive signals, 300 ns can be obtained.
4
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VREF(MAX)
VREF(MIN)
T1 T2 Temperature
Temperature
25°C
MAX
2.5 V
MIN
–n ppm/°C
+n ppm/°C
Voltage-Reference Electrical Characteristics
D
D
V
T
REF
D
D
V
V
REF
KA
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
PARAMETER TEST CONDITIONS T
A
MIN TYP MAX UNIT
TSM102 25 °C 2.475 2.5 2.525V
KA
= V
REF
, I
K
= 10 mA,V
REF
Reference voltage
(1)
VSee Figure 1TSM102A 25 °C 2.49 2.5 2.51Reference input voltage deviation V
KA
= V
REF
, I
K
= 10 mA,∆V
REF
Full range 7 30 mVover temperature range
(1)
See Figure 1
Average temperature coefficient of
V
KA
= V
REF
, I
K
= 10 mA Full range ±22 ±100 ppm/ °Creference input voltage
(2)
Ratio of change in reference voltage V
KA
= 3 V to 36 V, I
K
= 10 mA,
25 °C –1.1 –2 mV/Vto change in cathode voltage See Figure 2
25 °C 1.5 2.5I
K
= 10 mA, R1 = 10 k Ω, R2 = ∞,I
REF
Reference input current µASee Figure 2
Full range 3Reference input current deviation I
K
= 10 mA, R1 = 10 k Ω, R2 = ∞,∆I
REF
Full range 0.5 1 µAover temperature range See Figure 2Minimum cathode currentI
min
V
KA
= V
REF
, See Figure 1 25 °C 0.5 1 mAfor regulationI
K,OFF
Off-state cathode current See Figure 3 25 °C 180 500 nA
(1) ∆V
REF
is defined as the difference between the maximum and minimum values obtained over the full temperature range.∆V
REF
= V
REF(MAX)
– V
REF(MIN)(2) The temperature coefficient is defined as the slopes (positive and negative) of the voltage vs temperature limits within which thereference voltage is specified.
5Submit Documentation Feedback
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PARAMETER MEASUREMENT INFORMATION
VREF
IK
VKA
Input
VREF
IK
VKA
Input
IREF
R1
R2
V = V (1 + (R1/R2)) + (I × R1)
KA REF REF
IOFF
VKA
Input
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
Figure 1. Test Circuit for V
KA
= V
REF
Figure 2. Test Circuit for V
KA
> V
REF
Figure 3. Test Circuit for I
OFF
6
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TYPICAL CHARACTERISTICS
0.0001
0.001
0.01
0.1
1
100100010000100000
f–Frequency–Hz
THD–TotalHarmonicDistortion–%
100 1k 10k 100k
0
50
100
150
200
250
300
350
400
10100100010000100000
f–Frequency–Hz
VoltageNoise–nV/rtHz
nV/ÖHz
10 100 1k 10k 100k
-30
-20
-10
0
10
20
30
40
50
60
1.E+031.E+041.E+051.E+061.E+07
f–Frequency–Hz
Gain–dB
-180
-140
-100
-60
-20
20
60
100
140
180
Phase–deg
1k 10k 100k 1M 10M
Gain
Phase
0
5
10
15
20
25
30
35
110100100010000
Capacitance–pF
Current–mA
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
AMPLIFIER TOTAL HARMONIC DISTORTION AMPLIFIER NOISE VOLTAGEvs vsFREQUENCY FREQUENCY
Figure 4. Figure 5.
GAIN AND PHASE V
REF
STABILITYvs vsFREQUENCY CAPACITANCE
Figure 6. Figure 7.
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Temperature –°C
V–V
REF
–40 –25 –10 520 35 50 65 80 95 110 125
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
I = 100 mA
O
IO= 10 mA
IO= 1 mA
TSM102 , , TSM102ADUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
TYPICAL CHARACTERISTICS (continued)
V
REF
vsTEMPERATURE
Figure 8.
8
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PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TSM102AID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TSM102AI
TSM102AIDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TSM102AI
TSM102AIPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SN102AI
TSM102AIPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SN102AI
TSM102ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TSM102I
TSM102IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TSM102I
TSM102IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SN102I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TSM102AIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TSM102AIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TSM102IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TSM102IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSM102AIDR SOIC D 16 2500 367.0 367.0 38.0
TSM102AIPWR TSSOP PW 16 2000 367.0 367.0 35.0
TSM102IDR SOIC D 16 2500 367.0 367.0 38.0
TSM102IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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