Revised May 2005 74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs General Description Features The ACTQ16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ACTQ16244 utilizes Fairchild's Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance. Utilizes Fairchild's FACT Quiet Series technology Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed pin-to-pin output skew Separate control logic for each byte and nibble 16-bit version of the ACTQ244 Outputs source/sink 24 mA Additional specs for multiple output switching Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number 74ACTQ16244SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Description 74ACTQ16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol Pin Description Pin Names Description OEn Output Enable Input (Active LOW) I0-I15 Inputs O0-O15 Outputs FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation DS010925 www.fairchildsemi.com 74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs May 1991 74ACTQ16244 Connection Diagram Functional Description The ACTQ16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Truth Tables Inputs OE1 Outputs I0-I3 L L L L H H H X Z Inputs Outputs OE2 I4-I7 O4-O7 L L L L H H H X Z Inputs Logic Diagram Outputs OE3 I8-I11 O8-O11 L L L L H H H X Z Inputs OE4 2 Outputs I12-I15 O12-O15 L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com O0-O3 Supply Voltage (VCC) Recommended Operating Conditions 0.5V to 7.0V DC Input Diode Current (IIK) VI VI 0.5V VCC 0.5V Supply Voltage (VCC) 20 mA 20 mA DC Output Diode Current (IOK) 0.5V VCC 0.5V per Output Pin Storage Temperature 0V to VCC 40qC to 85qC Minimum Input Edge Rate ('V/'t) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC VCC or Ground Current Junction Temperature 0V to VCC Output Voltage (VO) Operating Temperature (TA) 20 mA 20 mA VO 0.5V to VCC 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) r50 mA VO 4.5V to 5.5V Input Voltage (VI) r50 mA 140qC 65qC to 150qC DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ Parameter VCC TA 25qC TA 40qC to 85qC (V) Typ Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Units Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 V V VOUT 0.1V or VCC 0.1V VOUT 0.1V or VCC 0.1V V IOUT 50 PA VIN VIL or VIH V IOH 24 mA IOH 24 mA (Note 2) Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 r 0.5 r 5.0 PA 5.5 r 0.1 r 1.0 PA 1.5 8.0 80.0 Maximum 3-STATE Conditions Guaranteed Limits 50 PA V IOUT VIN VIL or VIH V IOH 24 mA IOH Leakage Current VI 24 mA (Note 2) VIL, VIH VO VCC, GND IIN Maximum Input Leakage Current ICCT Maximum ICC/Input 5.5 ICC Max Quiescent Supply Current 5.5 IOLD Minimum Dynamic 5.5 IOHD Output Current (Note 3) VOLP Quiet Output Maximum Dynamic VOL 5.0 0.5 0.8 V Figure 1, Figure 2 (Note 5)(Note 6) VOLV Quiet Output Minimum Dynamic VOL 5.0 0.5 1.0 V Figure 1, Figure 2 (Note 5)(Note 6) 0.6 VI VCC, GND mA VI VCC 2.1V PA VIN 75 mA VOLD 1.65V Max 75 mA VOHD 3.85V Min VCC or GND (Note 6) VOHP Maximum Overshoot 5.0 VOH 1.0 VOH 1.5 V (Note 4)(Note 6) VOHV Minimum VCC Droop 5.0 VOH 1.0 VOH 1.8 V (Note 4)(Note 6) VIHD Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7) VILD Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7) Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH. Note 7: Max number of data inputs (n) switching. (n 1) input switching 0V to 3V input under test switching 3V to threshold (VILD) 3 www.fairchildsemi.com 74ACTQ16244 Absolute Maximum Ratings(Note 1) 74ACTQ16244 AC Electrical Characteristics Symbol Parameter VCC TA 25qC (V) CL 50 pF (Note 8) tPLH Propagation tPHL Delay An, Bn to Bn, An 5.0 tPZH Output Enable 5.0 tPZL Time tPHZ Output Disable tPLZ Time 5.0 Min Typ 3.0 2.5 40qC to 85qC TA CL 50 pF Max Min 5.2 7.3 3.0 7.8 4.8 6.8 2.5 7.3 Units Max 2.5 5.0 7.4 2.5 7.9 2.7 4.6 7.5 2.7 8.0 2.3 5.0 7.9 2.3 8.2 2.0 4.6 7.4 2.0 7.9 ns ns ns Note 8: Voltage Range 5.0 is 5.0V r 0.5V. Extended AC Electrical Characteristics TA 40qC to 85qC CL Symbol Parameter tPLH Propagation Delay tPHL Data to Output tPZH Output Enable tPZL Time tPHZ Output Disable tPLZ Time tOSHL Pin to Pin Skew (Note 10) HL Data to Output tOSLH Pin to Pin Skew (Note 10) LH Data to Output tOST Pin to Pin Skew (Note 10) LH/HL Data to Output 50 pF TA VCC 16 Outputs Switching (V) (Note 11) 40qC to 85qC CL 250 pF (Note 8) Min Max Min Max 5.0 4.0 11.6 5.6 14.3 3.4 9.6 4.8 13.1 5.0 5.0 Units (Note 12) Typ 3.5 10.1 3.4 10.0 3.6 8.9 3.1 8.1 5.0 1.2 5.0 2.5 5.0 4.3 (Note 13) (Note 14) ns ns ns ns ns ns Note 9: Voltage Range 5.0 is 5.0V r 0.5V. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 14: The Output Disable Time is dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC 5.0V CPD Power Dissipation Capacitance 30 pF VCC 5.0V www.fairchildsemi.com 4 Conditions VOLP/VOLV and VOHP/VOHV: The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. * Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f tf 3 ns, skew 150 ps. 1 MHz, tr 3 ns, FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ16244 FACT Noise Characteristics 74ACTQ16244 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 6 74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com