© 2005 Fairchild Semiconductor Corporation DS010925 www.fairchildsemi.com
May 1991
Revised May 2005
74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
74ACTQ16244
16-Bit Buffer /L ine Driver wi th 3-STATE Outputs
General Descript ion
The ACTQ16244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and addre ss driver, clock driver, or bus oriented tran s-
mitter/receiver . The device is nibble controlled. Each nibble
has separate 3- S TATE con tro l inpu ts which can be sh ort ed
together for full 16-bit operation.
The ACTQ16244 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic th reshold perform ance. FACT Quie t Series
¥
fea-
tures GTO
¥
output control for superior performance.
Features
■Utilizes Fairchild’s FACT Quiet Series technology
■Guaranteed simultaneous switching noise level and
dynamic thresh ol d per for man ce
■Guaranteed pin-to-pin output skew
■Separate control logic for each byte and nibble
■16-bit version of the ACTQ244
■Outputs source/sink 24 mA
■Additional specs for multiple output switching
■Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device a l s o av ailable in Tape and R eel. Specify by appending suffix lette r “X” to the ordering code.
Logic Symbol
Pin Description
FACT
¥
, FACT Quiet Series
¥
, and GTO
¥
are trad emarks of Fa irc hild Semic onduct or C orporat ion.
Order Number Package Number Package Description
74ACTQ16244SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACTQ16244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OEnOutput Enable Input (Active LOW)
I0–I15 Inputs
O0–O15 Outputs
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74ACTQ16244
Connection Diagram
Logic Diagram
Functional Description
The ACTQ16244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is nibble
(4 bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The 3-
STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW , the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Inputs Outputs
OE1I0–I3O0–O3
LL L
LH H
HX Z
Inputs Outputs
OE2I4–I7O4–O7
LL L
LH H
HX Z
Inputs Outputs
OE3I8–I11 O8–O11
LL L
LH H
HX Z
Inputs Outputs
OE4I12–I15 O12–O15
LL L
LH H
HX Z
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74ACTQ16244
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absol ut e max imum r ating s are those v alues beyond which damage
to the dev ice may occur. The databook specifi cations should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook spec if ic at ions.
DC Electrical Characteristics
Note 2: All outputs load ed; thresholds a ssociated w it h output un der test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of out puts that can s w it c h s im ultaneous ly is n. (n
1) outp uts ar e s w itche d LOW and one ou t put held LOW.
Note 6: Maximum number of out puts that can s w it c h s im ultaneous ly is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7: Max number of data inputs (n) switching. (n
1) input sw it c hing 0V to 3V input u nder test switching 3V t o t hreshold (VILD)
Supply Voltage (VCC)
0.5V to
7.0V
DC Input Diode Current (IIK)
VI
0.5V
20 mA
VI
VCC
0.5V
20 mA
DC Output Diode Current (IOK)
VO
0.5V
20 mA
VO
VCC
0.5V
20 mA
DC O utput Voltage (VO)
0.5V to VCC
0.5V
DC Output Source/Sink Current (IO)
r
50 mA
DC VCC or Ground Current
per Output Pin
r
50 mA
Junction Temperature
140
q
C
Storage Temperature
65
q
C to
150
q
C
Supply Voltage (VCC) 4.5V to 5.5V
Input Voltage (VI)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA)
40
q
C to
85
q
C
Minimum Input Edge Rate (
'
V/
'
t) 125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Symbol Parameter VCC TA
25
q
CT
A
40
q
C to
85
q
CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH 4.5 1.5 2.0 2.0 VVOUT
0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC
0.1V
VIL Maximum LOW 4.5 1.5 0.8 0.8 VVOUT
0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC
0.1V
VOH Minimum HIGH 4.5 4.49 4.4 4.4 VI
OUT
50
P
A
Output Voltage 5.5 5.49 5.4 5.4 VIN
VIL or VIH
4.5 3.86 3.76 V IOH
24 mA
5.5 4.86 4.76 IOH
24 mA (Note 2)
VOL Maximum LOW 4.5 0.001 0.1 0.1 VI
OUT
50
P
A
Output Voltage 5.5 0.001 0.1 0.1 VIN
VIL or VIH
4.5 0.36 0.44 V IOH
24 mA
5.5 0.36 0.44 IOH
24 mA (Note 2)
IOZ Maximum 3-STATE 5.5
r
0.5
r
5.0
P
AV
I
VIL, VIH
Leakage Current VO
VCC, GND
IIN Maximum Input Leakage Current 5.5
r
0.1
r
1.0
P
AV
I
VCC, GND
ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI
VCC
2.1V
ICC Max Quiescent Supply Current 5.5 8.0 80.0
P
AV
IN
VCC or GND (Note 6)
IOLD Minimum Dynamic 5.5 75 mA VOLD
1.65V Max
IOHD Output Current (Note 3)
75 mA VOHD
3.85V Min
VOLP Quiet Output Maximum Dynamic VOL 5.0 0.5 0.8 V Figure 1, Figure 2
(Note 5)(Note 6)
VOLV Quiet Output Minimum Dynamic VOL 5.0
0.5
1.0 V Figure 1, Figure 2
(Note 5)(Note 6)
VOHP Maximum Overshoot 5.0 VOH
1.0 VOH
1.5 V (Note 4)(Note 6)
VOHV Minimum VCC Droop 5.0 VOH
1.0 VOH
1.8 V (Note 4)(Note 6)
VIHD Minimum HIGH Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7)
VILD Maximum LOW Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)
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74ACTQ16244
AC Electrical Characteristics
Note 8: Voltage Range 5.0 is 5. 0V
r
0.5V.
Extended AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5. 0V
r
0.5V.
Note 10: Skew is d efined a s the a bsolute v alue of the differe nce bet ween the actu al propaga tion dela ys for an y two s eparate o utputs of t he same device .
The specif ica tion appli es t o an y ou tput s sw itchin g HI GH -to-L OW (tOSHL), LOW-to-H IG H (tOSLH), or an y com bin ation sw itc hing LO W-to-H IGH an d/or HIGH -
to-LO W (t OST).
Note 11: This specif ic ation is gu arante ed but not tes t ed. The limits apply to pr opagation delays for all paths des c ribed sw it ch ing in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 12: This spec ification is guar anteed but n ot tested. The lim its repr esent propagati on delays with 250 pF load capacitors in p lace of the 50 pF load
capacit ors in the s tan dard AC load. This sp ec if ic ation perta ins t o s ingle output switching only.
Note 13: 3-STATE delays ar e load dominated and have been excl uded from th e datasheet .
Note 14: The Outp ut D is able Time is dominated by t he RC netw ork (500
:
, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
VCC TA
25
q
CT
A
40
q
C to
85
q
C
Symbol Parameter (V) CL
50 pF CL
50 pF Units
(Note 8) Min Typ Max Min Max
tPLH Propagation 3.0 5.2 7.3 3.0 7.8 ns
tPHL Delay An, Bn to Bn, An5.0 2.5 4.8 6.8 2.5 7.3
tPZH Output Enable 5.0 2.5 5.0 7.4 2.5 7.9 ns
tPZL Time 2.7 4.6 7.5 2.7 8.0
tPHZ Output Disable 5.0 2.3 5.0 7.9 2.3 8.2 ns
tPLZ Time 2.0 4.6 7.4 2.0 7.9
TA
40
q
C to
85
q
C
CL
50 pF TA
40
q
C to
85
q
C
Symbol Parameter VCC 16 Outputs Switching CL
250 pF Units
(V) (Note 11) (Note 12)
(Note 8) Min Typ Max Min Max
tPLH Propagation Delay 5.0 4.0 11.6 5.6 14.3 ns
tPHL Data to Output 3.4 9.6 4.8 13.1
tPZH Output Enable 5.0 3.5 10.1 (Note 13) ns
tPZL Time 3.4 10.0
tPHZ Output Disable 5.0 3.6 8.9 (Note 14) ns
tPLZ Time 3.1 8.1
tOSHL Pin to Pin Skew 5.0 1.2 ns
(Note 10) HL Data to Output
tOSLH Pin to Pin Skew 5.0 2.5 ns
(Note 10) LH Data to Output
tOST Pin to Pin Skew 5.0 4.3 ns
(Note 10) LH/HL Data to Output
Symbol Parameter Typ Units Conditions
CIN Input Pin Capacita nce 4.5 pF VCC
5.0V
CPD Power Dissipation Capacitance 30 p F VCC
5.0V
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74ACTQ16244
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy an d rep eatab i lity of the tests. The follo wi ng
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
:
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Term i na te a ll inpu ts and o utputs to ensu re p ro per loa d-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS ge nerato r to togg le all but on e outpu t at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
VOHV and VOLP are mea s ured with re s pect to ground reference.
Input pulses have the following characteristics: f
1MHz, t
r
3ns,
tf
3 ns, skew
150 ps.
FIGURE 1. Quiet Output Noise Voltage W aveforms
5. Set the HFS gen erator input le vels at 0V LOW and 3V
HIGH for ACT device s and 0V LOW and 5 V HIGH f or
AC devices. V erify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
•Determine the quiet output pin that demonstrates the
greatest no ise levels. The worst case pin w ill usually be
the furthe st from th e g rou nd pi n . Mo nito r the out put vol t-
ages us ing a 50
:
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
•Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
•Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
•Monitor one of the switching outputs using a 50
:
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
•First incr ease the in put LOW voltage level, V IL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input L OW voltage level at which
oscillation occurs is defined as VILD.
•Next decrease the input HIGH voltage level, VIH, until
the output b egins to o scillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
•Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ16244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Packag e Num b er MS48A
7 www.fairchildsemi.com
74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide
Package Number MTD48
Fairchild does not assum e any responsibility for use of any circuitry described, n o circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the l abe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t
device or system, or to affect its safety or effectiveness.
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