MICRF003YMTR - Micrel - Datasheet.Directory

Micrel Inc. • 1849 Fortune Drive San Jose, Ca 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

MICRF003 / 033

QwikRadiotm 900 MHz UHF Receiver

Preliminary Information

General Description

The MICRF003 is a single chip OOK (ON-OFF Keyed) Receiver IC for

remote wireless applications, employing Micrel’s latest QwikRadiotm

technology. This device is a true “antenna-in, data-out” monolithic device. All

RF and IF tuning is accomplished automatically within the IC, which

eliminates manual tuning, and reduces production costs. Receiver functions

are completely integrated. The result is a highly reliable yet extremely low

cost solution for high volume wireless applications. Because the MICRF003

is a true single-chip radio receiver, it is extremely easy to apply, minimizing

design and production costs, and improving time to market.

The MICRF003 provides two fundamental modes of operation, FIXED and

SWP. In FIXED mode, the device functions like a conventional

Superheterodyne receiver, with an (internal) local oscillator fixed at a single

frequency based on an external reference crystal or clock. As with any

conventional superheterodyne receiver, the transmit frequency must be

accurately controlled, generally with a crystal or SAW (Surface Acoustic

Wave) resonator.

In SWP mode, the MICRF003 sweeps the (internal) local oscillator at rates

greater than the baseband data rate. This effectively “broadens” the RF

bandwidth of the receiver to a value equivalent to conventional super-

regenerative receivers. Thus the MICRF003 can operate with less

expensive LC transmitters without additional components or tuning, even

though the receiver topology is still superheterodyne. In this mode the

reference crystal can be replaced with a less expensive ± 0.5% ceramic

resonator.

The MICRF003 provides two additional key features: (1) a Shutdown Mode,

which may be used for duty-cycle operation, and (2) a “Wakeup” function,

which provides a logical indication of an incoming RF signal. These features

make the MICRF003 ideal for low and ultra-low power applications, such as

RKE and RFID.

All post-detection (demodulator) data filtering is provided on the MICRF003,

so no external filters need to be designed. Any one of four filter bandwidths

may be selected externally by the user. Nominal filter bandwidths range in

binary steps, from 0.75kHz to 6kHz (SWP mode) or 2.8kHz to 22.4kHz

(FIXED mode). The user only needs to program the appropriate filter

selection based on data rate and code modulation format.

Features

• Complete 900 MHz Band receiver on a monolithic IC

• UHF Frequency range 800 to 1000 MHz

• Typical range over 170 meters with monopole antenna

• Data rates to 5kbps (SWP), 20kbps (FIXED)

• Automatic tuning, no manual adjustment

• No Filters or Inductors required

• Low Operating Supply Current--4mA @ 868MHz

• Shutdown Mode for Duty-Cycle Operation in excess of

100:1

• Wakeup Function to Enable External Decoders and

Microprocessors

• Very low RF re-radiation at the antenna

• CMOS logic interface to standard decoder and

microprocessor ICs

• Extremely low external part count

Applications

• Automotive Remote Keyless Entry

• Security Systems

• Low Rate Data Modems

• Remote Meter Data Collection

Typical Operating Circuit

915 MHz, 2400 bps OOK

ISM Band RECEIVER

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Ordering Information

Part Number Temperature Range Package

MICRF003BM -40°C to +105°C 16-Pin SOIC

MICRF033BM -40°C to +105°C 8-Pin SOIC

The standard 16-pin package provides the user with complete control of MICRF002 mode and filter selection. An 8-pin

standard part is also available for very low cost applications. The 8-pin version comes pre-programmed in SWP mode, with

Demodulator Filter bandwidth set to 5000Hz, and SHUT pin externally available. Other 8-pin configurations are available.

Contact the factory for details.

Pin Configuration (SOIC)

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Pin Description (Pin numbers for the 8-pin version are identified in parentheses)

Pin Number Pin Name Pin Function

1 SEL0 This pin, in conjunction with SEL1, programs the desired Demodulator Filter Bandwidth. This pin is internally

pulled-up to VDDRF. See Table 1.

2/3

VSSRF This pin is the ground return for the RF section of the IC. The bypass capacitor connected from VDDRF to

VSSRF should have the shortest possible lead length. For best performance, connect VSSRF to VSSBB at the

power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

(1)

VSSRF This pin is the ground return for the IC. The bypass capacitor connected from VDDRF to VSSRF should have

the shortest possible lead length.

(2) ANT This is the receive RF input, internally ac-coupled. Connect this pin to the receive antenna. Input impedance is

high (FET gate) with approximately 2pF of shunt (parasitic) capacitance. For applications located in high

ambient noise environments, a fixed value band-pass network may be connected between the ANT pin and

VSSRF to provide additional receive selectivity and input overload protection. (See “Application Note TBD”.)

VDDRF This pin is the positive supply input for the RF section of the IC. VDDBB and VDDRF should be connected

directly at the IC pins. Connect a low ESL, low ESR decoupling capacitor from this pin to VSSRF, as short as

possible.

6 VDDBB This pin is the positive supply input for the baseband section of the IC. VDDBB and VDDRF should be

connected directly at the IC pins.

(3) VDDRF This pin is the positive supply input for the IC. Connect a low ESL, low ESR decoupling capacitor from this pin

to VSSRF, as short as possible.

(4)

CTH This capacitor extracts the (DC) average value from the demodulated waveform, which becomes the reference

for the internal data slicing comparator. Treat this as a low-pass RC filter with source impedance of nominally

90kohms ( for REFOSC frequency Ft = 6.75MHz, see “Application Note TBD”). A standard ± 20% X7R

ceramic capacitor is generally sufficient.

8 N/C Unused Pin

9 VSSBB This is the ground return for the baseband section of the IC. The bypass and output capacitors connected to

VSSBB should have the shortest possible lead lengths. For best performance, connect VSSRF to VSSBB at

the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).

(5) DO The output data signal. CMOS level compatible.

(6)

SHUT A logic input for Shutdown Mode control. Pull this pin low to place the IC into operation. This pin in internally

pulled-up to VDDRF.

12 WAKEB An output signal, active low when the IC detects an incoming RF signal, determined by monitoring for data

preamble. CMOS level compatible.

(7) CAGC Integrating capacitor for on-chip AGC (Automatic Gain Control). The Decay/Attack time-constant (TC) ratio is

nominally set as 10:1. Use of 0.47uF or greater is strongly recommended for best range performance. Use

low-leakage type capacitors for duty-cycle operation (Dip Tantalum, Ceramic, Polyester). (See “Application Note

TBD.)

14 SEL1 This pin, in conjunction with SEL0, programs the desired Demodulator Filter Bandwidth. This pin in internally

pulled-up to VDDRF. See Table 1.

(8) REFOSC This is the timing reference for on-chip tuning and alignment. Connect either a ceramic resonator or crystal

(mode dependent) between this pin and VSSBB, or drive the input with an AC coupled 0.5Vpp input clock. Use

ceramic resonators without integral capacitors. Note that if operating in FIXED mode, a crystal must be used;

however in SWP mode, one may use either a crystal or ceramic resonator. See “Application Note TBD” for

details on frequency selection and accuracy.

16 SWEN This logic pin controls the operating mode of the MICRF003. When SWEN = HIGH, the MICRF003 is in SWP

mode. When SWEN = LOW, the device operates as a conventional single-conversion superheterodyne

receiver. (See “Application Note TBD” for details.) This pin is internally pulled-up to VDDRF.

SEL0 SEL1 Demodulator Bandwidth (Hz)

SWP Mode FIXED Mode

1 1 6000 22400

0 1 3000 11200

1 0 1500 5600

0 0 750 2800

Table 1

Nominal Demodulator (Baseband) Filter Bandwidth

vs. SEL0, SEL1 and Mode

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ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDDRF, VDDBB)..................................+7V

Voltage on any I/O Pin.........................VSS-0.3 to VDD+0.3

Junction Temperature...............................................+150°C

Storage Temperature Range......................-65°C to + 150°C

Lead Temperature (soldering, 10 seconds)..............+ 260°C

Operating Ratings

Supply Voltage (VDDRF, VDDBB)....................4.75V to

5.5V

Ambient Operating Temperature (TA)..........-40°C to

+105°C

Package Thermal Resistance θja (8 Pin SOIC).....120°C/W

Package Thermal Resistance θja (16 Pin SOIC).....120°C/W

Electrical Characteristics

Unless otherwise stated, these specifications apply for Ta = -40°C to 105°C, 4.75<VDD<5.5V. All voltages are with respect

to Ground; Positive currents flow into device pins. CAGC = 4.7µF, CTH = .047µF, VDDRF = VDDBB = VDD. REFOSC

frequency = 6.75MHz.

Parameter Test Conditions MIN TYP MAX UNITS

Power Supply

Operating Current 4 mA

Operating Current 10:1 Duty Cycle 400 µA

Standby Current SHUT = VDD 1 µA

RF/IF Section

Receiver Sensitivity Note 1, 3 -95 dBm

IF Center Frequency Note 4 2.37 MHz

IF 3dB Bandwidth Note 3, 4 1.18 MHz

Receive Data Rate FIXED Mode, Manchester Encoded Data 20 kbps

Receive Data Rate SWP Mode, Manchester Encoded Data 5 kbps

RF Input Range 800 1000 MHz

Receive Modulation Duty-Cycle 20 80 %

Maximum Receiver Input Rs = 50Ω -20 dBm

Spurious Reverse Isolation ANT pin, Rs = 50Ω Note 2 30 µVrms

AGC Attack / Decay ratio T(Attack) / T(Decay) 0.1

AGC Leakage Current Ta = 85°C ±200 nA

Local Oscillator Stabilization Time To 1% of Final Value 2.5 msec

Demod Section

CTH Source Impedance Note 5 90k Ω

CTH Source Impedance Variation -15 +15 %

CTH Leakage Current Ta = 85°C ±200 nA

Demod Filter Bandwidth SEL0 = SEL1 = SWEN = VDD, Note 4, 6 5730 Hz

Demod Filter Bandwidth SEL0 = SEL1 = VDD, SWEN = VSS,

Note 4, 6 21500 Hz

Digital/Control Section

REFOSC Input Impedance 200k Ω

Input Pullup Current SEL0, SEL1, SWEN, SHUT=VSS 8 µA

Input High Voltage SEL0, SEL1, SWEN 0.8VDD V

Input Low Voltage SEL0, SEL1, SWEN 0.2VDD V

Output Current DO, WAKEUP pins, Push-Pull 35 µA

Output High Voltage DO, WAKEUP pins, Iout = -1µA 0.9VDD V

Output Low Voltage DO. WAKEUP pins, Iout = +1µA 0.1VDD V

Output Tr, Tf DO, WAKEUP pins, Cload=15pF 5 µsec

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Note 1: Sensitivity is defined as the average signal level measured at the input necessary to achieve 10e-2 Bit Error Rate (BER). The input

signal is defined as a return-to-zero (RZ) waveform with 50% average duty cycle (e.g., Manchester Encoded Data) at a data rate of

600bps. The RF input is assumed to be matched into 50Ω.

Note 2: Spurious reverse isolation represents the spurious components which appear on the RF input (ANT) pin measured into 50Ω with an

input RF matching network.

Note 3: Sensitivity, a commonly specified Receiver parameter, provides an indication of the Receiver’s input referred noise, generally input

thermal noise. However, it is possible for a more sensitive receiver to exhibit range performance no better than that of a less

sensitive receiver, if the “ether” noise is appreciably higher than the thermal noise. “Ether” noise refers to other interfering “noise”

sources, such as FM radio stations, pagers, etc.

A better indicator of achievable receiver range performance is usually given by its Selectivity, often stated as Intermediate Frequency

(IF) or Radio Frequency (RF) bandwidth, depending on receiver topology. Selectivity is a measure of the rejection by the receiver of

“ether” noise. More selective receivers will almost invariably provide better range. Only when the receiver selectivity is so high that

most of the noise on the receiver input is actually thermal will the receiver demonstrate sensitivity-limited performance.

Note 4: Parameter scales linearly with REFOSC frequency Ft. For any REFOSC frequency other than 6.75MHz, compute new parameter

value as the ratio [(REFOSC FREQ (in MHz)) / 6.75] * [Parameter Value @ 6.75MHz]. Example: For REFOSC Freq. Ft =

7.12MHz, [Parameter Value @ 7.12MHz] = (7.12 / 6.75) * [Parameter Value @ 6.75MHz].

Note 5: Parameter scales inversely with REFOSC frequency Ft. For any REFOSC frequency other than 6.75MHz, compute new parameter

value as the ratio [6.75 / (REFOSC FREQ (in MHz))] * [Parameter Value @ 6.75MHz]. Example: For REFOSC Freq. Ft =

7.12MHz, [Parameter Value @ 7.12MHz] = (6.75 / 7.12) * [Parameter Value @ 6.75MHz].

Note 6: Demod filter bandwidths are related in a binary manner, so any of the other (lower) nominal filter values may be derived simply by

dividing this parameter value by 2, 4, or 8 as desired.

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Typical Performance Characteristics

3.00

3.50

4.00

4.50

5.00

5.50

6.00

800 825 850 875 900 925 950 975 1000

Frequency (MHz)

2.50

3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

7.00

-40 -20 020 40 60 80 100 120

Temperature (C)

MICRF003 IDD vs Temperature

(Frequency=868MHz, VDD=5.0V, SWP Mode)

IDD(mA)

MICRF003 IDD vs Frequency

(Temperature=25°°C, VDD=5.0V, SWP Mode)

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MICRF003 Block Diagram

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Functional Description

Please refer to “MICRF003 Block Diagram”. Identified in

the block diagram are the four principal functional blocks of

the IC, namely (1) UHF Downconverter, (2) OOK

Demodulator, (3) Reference and Control, and (4) Wakeup.

Also shown in the figure are two capacitors (CTH, CAGC)

and one timing component (CR), usually a ceramic

resonator. With the exception of a supply decoupling

capacitor, these are all the external components needed

with the MICRF003 to construct a complete UHF receiver.

Four control inputs are shown in the block diagram, SEL0,

SEL1, SWEN, and SHUT. Through these logic inputs the

user can control the operating mode and selectable features

of the IC. These inputs are CMOS compatible, and are

pulled-up on the IC.

Input SWEN selects the operating mode of the IC (FIXED

mode or SWP mode). When low, the IC is in FIXED mode,

and functions as a conventional superheterodyne receiver.

When SWEN is high, the IC is in SWP mode. In this mode,

while the topology is still superheterodyne, the local

oscillator (LO) is deterministically swept over a range of

frequencies at rates greater than the data rate. When

coupled with a peak-detecting demodulator, this technique

effectively increases the RF bandwidth of the MICRF003, so

the device can operate in applications where significant

Transmitter/Receiver frequency misalignment may exist.

[Note: The swept LO technique does not affect the IF

bandwidth, so noise performance is not impacted relative to

FIXED mode. In other words, the IF bandwidth is the same

(1.18MHz) whether the device is in FIXED or SWP mode.]

Due to limitations imposed by the LO sweeping process, the

upper limit on data rate in SWP mode is approximately

5kbps. Data rates beyond 20kbps are possible in FIXED

mode however.

Examples of SWP mode operation include applications

which utilize low-cost LC-based transmitters, whose

transmit frequency may vary up to ± 0.5% over initial

tolerance, aging, and temperature. In this (patent-pending)

mode, the LO frequency is varied in a prescribed fashion

which results in downconversion of all signals in a band

approximately 1.5% around the transmit frequency. So the

Transmitter may drift up to ± 0.5% without the need to

retune the Receiver, and without impacting system

performance. Such performance is not achieved with

currently available crystal-based superheterodyne receivers,

which can operate only with SAW or crystal based

transmitters.

[Note: In SWP mode only, a range penalty will occur in

installations where there exists a competing signal of

sufficient strength in this small frequency band of 1.5%

around the transmit frequency. This results from the fact

that sweeping the LO indiscriminantly “sweeps” all signals

within the sweep range down into the IF band. This same

penalty also exists with super-regenerative type receivers,

as their RF bandwidth is also generally 1.5%. So any

application for a super-regenerative receiver is also an

application for the MICRF003 in SWP mode.]

For applications where the transmit frequency is accurately

set for other reasons (e.g., applications where a SAW

transmitter is used for its mechanical stability), the user

may choose to configure the MICRF003 as a standard

superheterodyne receiver (FIXED mode), mitigating the

aforementioned problem of a competing close-in signal.

This can be accomplished by tying SWEN to ground. Doing

so forces the on-chip LO frequency to a fixed value. In

FIXED mode, the ceramic resonator would be replaced with

a crystal. Generally, however, the MICRF003 can be

operated in SWP mode, using a ceramic resonator , with

either LC or CRYSTAL/SAW based transmitters, without

any significant range difference.

The inputs SEL0 and SEL1 control the Demodulator filter

bandwidth in four binary steps (750Hz-6000Hz in SWP,

2800Hz-22400Hz in FIXED mode), and the user must select

the bandwidth appropriate to his needs.

Rolloff response of the IF Filter is 5

th order, while the

demodulator data filter exhibits a 2

nd order response.

Multiplication factor between the REFOSC frequency Ft and

the internal Local Oscillator (LO) is 129X for FIXED mode,

and 128.5X for SWP mode (i.e., for Ft = 6.75MHz in FIXED

mode, LO frequency = 6.75MHz * 129 = 870.75MHz).

Slicing Level and the CTH Capacitor

Extraction of the DC value of the demodulated signal for

purposes of logic-level data slicing is accomplished by

external capacitor CTH and the on-chip switched-cap

“resistor” RSC, indicated in the block diagram. The

effective resistance of RSC is 90kohms. The value of

capacitor CTH is easily calculated, once the slicing level

time-constant is chosen. Slicing Level time constant values

vary somewhat with decoder type, data pattern, and data

rate, but typical values range 5-50msec. Optimization of

the CTH value is required to maximize range, as discussed

in “Application Note TBD”.

During quiet periods (i.e., no signal transmissions) the Data

Output (DO pin) transitions randomly based on noise. This

may present problems for some decoders. The most

common solution is to introduce a small offset (“Squelch”)

on the CTH pin so that noise does not trigger the internal

comparator. Usually 20-30mV is sufficient, and may be

introduced by connecting a several-Megohm resistor from

the CTH pin to either VSS or VDD, depending on the

desired offset polarity. Since the MICRF003 is an AGC’d

receiver, noise at the internal comparator input is always

the same, set by the AGC. So the squelch offset

requirement does not change as the local “ether” noise

changes from installation to installation. Note that

introducing squelch will reduce range modestly, so only

introduce an amount sufficient to “quiet” the output.

AGC Function and the CAGC Capacitor

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The signal path has automatic gain control (AGC) to

increase input dynamic range. An external capacitor,

CAGC, must be connected to the CAGC pin of the device.

The ratio of decay-to-attack time-constant is fixed at 10:1

(i.e., the attack time constant is 1/10th the decay time

constant), and this ratio cannot be changed by the user.

However, the attack time constant is selectable by the user

through the value of capacitor CAGC.

[By adding resistance from the CAGC pin to VDDBB or

VSSBB in parallel with the CAGC capacitor, the ratio of

decay-to-attack time-constant may be varied, although the

value of such adjustments must be studied on a per-

application basis. Generally the design value of 10:1 is

adequate for the vast majority of applications.] See

“Application Note TBD”.

To maximize system range, it is important to keep the AGC

control voltage ripple low, preferably under 10mVpp once

the control voltage has attained its quiescent value. For this

reason capacitor values ≥ 0.47uF are recommended.

The AGC control voltage is carefully managed on-chip to

allow duty-cycle operation of the MICRF003 in excess of

100:1. When the device is placed into SHUT mode (i.e.,

SHUT pin pulled high), the AGC capacitor is “floated”, to

retain the voltage. When operation is resumed, only the

voltage droop on the capacitor associated with leakage

must be replenished. Thus a relatively low-leakage

capacitor is recommended for duty cycle operation. The

actual tolerable leakage will be application dependent.

Clearly, leakage performance is less critical when the

device off-time is low (milliseconds), and more critical when

the off-time is high (seconds).

To further enhance Duty-cycle operation of the IC, the AGC

push and pull currents are increased for a fixed time

immediately after the device is taken out of Shutdown mode

(i.e., turned-on). This compensates for AGC capacitor

voltage “droop” while the IC is in Shutdown, reduces the

time to reacquire the correct AGC voltage, and thus extends

maximum achievable duty ratios. Push/Pull currents are

increased by 45X their nominal values. The fixed time

period is based on the REFOSC frequency Ft, 9.7msec for

Ft = 6.75MHz, and varies inversely as Ft varies, by the

scale factor Ft / 6.75, where Ft is in MHz.

Reference Oscillator (REFOSC) and External Timing

Element

All timing and tuning operations on the MICRF003 are

derived from the REFOSC function. This function is a

single-pin Colpitts-type oscillator. The user may handle this

pin in one of three possible ways:

(1) connect a ceramic resonator, or

(2) connect a crystal, or

(3) drive this pin with an external timing signal.

The third approach is attractive for further lowering system

cost if an accurate reference signal exists elsewhere in the

system (e.g., a reference clock from a crystal or ceramic

resonator-based microprocessor). An externally applied

signal should be AC-coupled, and resistively-divided down

(or otherwise limited) to approximately 0.5Vpp. The specific

reference frequency required is related to the system

transmit frequency, and to the operating mode of the device

as set by the SWEN control pin. See “Application Note

TBD” for a discussion of frequency selection and accuracy

requirements.

Wakeup Function

The Wakeup function is made available for the purposes of

further reducing power consumption of the overall wireless

system. WAKEB is an output logic signal, which goes

active when the IC detects a constant RF Carrier “header” in

the demodulated output signal. Sense of the signal is

active-low. This output may be used to “wakeup” other

external circuits, like a data decoder or microprocessor,

only at times when there is a reasonable expectation of an

incoming RF signal. The Wakeup function is unavailable

when the IC is in SHUT mode.

The Wakeup function is composed of a resettable counter,

based on an internal 27.5kHz clock (based on a 7.04Mhz

reference frequency). To utilize this function, a burst of RF

Carrier in excess of 5msec must be placed at the start of

each data code word, or a single 5msec RF carrier tone at

the start of the data pattern (clearly the former is preferred

to improve communication reliability). When this constant

carrier tone is detected, without interruption, for 128 clock

cycles of 27.5kHz, WAKEB will transition low, and stay low

until data begins. This particular approach is utilized over

others (1) since constant tones in excess of 5msec are very

rare, leading to few false-positive indications, and (2) this

technique does not require the introduction of a signal path

offset, which impacts achievable range.

[Note: For designers who wish to use the Wakeup function

while “squelching” the output, a positive squelching offset

voltage must be used. This simply requires the squelch

resistor be taken to a voltage more positive than the

quiescent voltage on pin CTH, so that the data output is low

in absence of a transmission.]

Shutdown Function

The Shutdown function is controlled by the logic state of

SHUT. When SHUT is high, the device goes into low-power

standby mode, consuming less than 1µA. This pin is pulled

high internally, and so must be pulled low to engage the

device.

MICRF003 Frequency and Capacitor Selection

Selection of the REFOSC frequency Ft, Slicing Level (CTH)

capacitor, and AGC capacitor are briefly summarized in this

section. Please see Application Note TBD for complete

details.

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1. Selecting REFOSC Frequency Ft (FIXED Mode)

As with any superheterodyne receiver, the difference

between the (internal) Local Oscillator (LO) frequency Flo

and the incoming Transmit frequency Ftx must ideally equal

the IF Center frequency. Equation (1) may be used to

compute the appropriate Flo for a given Ftx:

Flo = Ftx ± 2.496 * (Ftx / 915) (1)

where Ftx and Flo are in MHz. Note that two values of Flo

exist for any given Ftx, distinguished as “high-side mixing”

and “low-side mixing”, and there is generally no preference

of one over the other.

After choosing one of the two acceptable values of Flo, use

equation (2) to compute the REFOSC frequency Ft:

Ft = Flo / 129. (2)

Here Ft is in MHz. Connect a crystal of frequency Ft to the

REFOSC pin of the MICRF003. 4 decimal-place accuracy

on the frequency is generally adequate. The following table

identifies Ft for some common Transmit frequencies when

the MICRF003 is operated in FIXED mode.

Transmit Freq. Ftx (MHz) REFOSC Freq. Ft (MHz)

868

915

6.7470

7.1124

2. Selecting REFOSC Frequency Ft (SWP Mode)

Selection of REFOSC frequency Ft in SWP mode is much

simpler than in FIXED mode, due to the LO sweeping

process. Further, accuracy requirements of the frequency

reference component are significantly relaxed.

In SWP mode, Ft is given by equation (3):

Ft = Ftx / 128.5. (3)

Connect a ceramic resonator of frequency Ft to the

REFOSC pin of the MICRF003. 2-decimal place accuracy

is generally adequate. (A crystal may also be used if

desired, but may be necessary to reduce the Rx frequency

ambiguity if the Tx frequency ambiguity is excessive. See

Application Note TBD for further details.)

3. Selecting Capacitor CTH

First step in the process is selection of a Data Slicing Level

timeconstant. This selection is strongly dependent on

system issues, like system decode response time and data

code structure (e.g., existance of data preamble, etc.). This

issue is too broad to discuss here, and the interested reader

should consult the Application Note TBD.

Source impedance of the CTH pin is given by equation (4),

where Ft is in MHz:

Rs = 90kΩ * (6.75 / Ft). (4)

Assuming that a Slicing Level Timeconstant TC has been

established, capacitor CTH may be computed using

equation (5):

CTH = TC / Rs. (5)

4. Selecting CAGC Capacitor in Continuous Mode

Selection of CAGC in continuous mode is dictated by

minimizing the ripple on the AGC control voltage, by using a

sufficiently large capacitor. It is Micrel’s experience that

CAGC should be in the vicinity of 0.47µF to 4.7µF. Large

capacitor values should be carefully considered, as this

determines the time required for the AGC control voltage to

settle from a completely discharged condition. AGC settling

time from a completely discharged (0-volt) state is given

approximately by equation (6):

∆T = (1.333 * CAGC) – 0.44 (6)

where CAGC is in microfarads, and ∆T is in seconds.

5. Selecting CAGC Capacitor in Duty-Cycle Mode

Generally, droop of the AGC control voltage during

shutdown should be replenished as quickly as possible after

the IC is “turned-on”. Recall from the section “AGC

Function and the CAGC Capacitor” that for about 10msec

after the IC is turned-on, the AGC push-pull currents are

increased to 45X their normal values. So consideration

should be given to selecting a value for CAGC and a

shutdown time period such that the droop can be

replenished within this 10msec period.

Polarity of the droop is unknown, meaning the AGC voltage

could droop up or down. Worst-case from a recovery

standpoint is downward droop, since the AGC pullup current

is 1/10th magnitude of the pulldown current. The downward

droop is replenished according the the well-known equation

(7):

I / CAGC = ∆V / ∆T (7)

where I = AGC Pullup current for initial 10msec (67.5µA),

CAGC is the AGC capacitor value, ∆T = Droop recovery

time (<10msec), and ∆V is the droop voltage.

For example, if user desires ∆T = 10msec, and chooses a

4.7µF CAGC, then the allowable droop is about 144mV.

Using the same equation with 200nA worst case pin

leakage and assuming 1uA of capacitor leakage in the

same direction, the maximum allowable ∆T (Shutdown

time) is about 0.56 seconds, for droop recovery in 10msec.

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October 1999 MICRF003

MICRF003 Micrel

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF003

is shown in Figures 1 through 6. Specific information

regarding each of these circuits is discussed in the following

sub-paragraphs. Not shown are ESD protection diodes

which are applied to all input and output pins.

1. ANT Pin

The ANT pin is internally AC-coupled via a 3pF capacitor, to

an RF N-channel MOSFET, as shown in Figure 1.

Impedance on this pin to VSS is quite high at low

frequencies, and decreases as frequency increases. In the

UHF frequency range, the device input can be modeled as

6.3kΩ in parallel with 2pF (pin capacitance) shunt to

VSSRF.

2. CTH Pin

Figure 2 illustrates the CTH pin interface circuit. CTH pin is

driven from a P-channel MOSFET source-follower biased

with approximately 10µA of bias current. Transmission

gates TG1 and TG2 isolate the 6.9pF capacitor. Internal

control signals PHI1/PHI2 are related in a manner such that

the impedance across the transmission gates looks like a

“resistance” of 90kohms. The DC potential on the CTH pin

is approximately 1.6V.

3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The

AGC control voltage is developed as an integrated current

into a capacitor CAGC. The attack (pulldown) current is

nominally 15µA, while the decay (pullup) current is a 1/10th

scaling of this, nominally 1.5µA, so the attack/decay

timeconstant ratio is fixed at 10:1. Signal gain of the RF/IF

strip inside the IC diminishes as the voltage on CAGC

decreases. Further discussion on setting the attack time

constant is found in “Application Note TBD. Modification of

the attack/decay ratio is possible by adding resistance from

CAGC pin either to VDDBB or VSSBB, as desired. Both the

Push and Pull current sources are disabled during SHUT,

which holds the voltage across CAGC, and improves

recovery time in duty-cycled applications. To further

improve duty cycle recovery, both Push and Pull currents

are increased by 45X for approximately 10msec after

release of SHUT. This allows rapid recovery of any voltage

droop on CAGC while in SHUT.

4. DO and WAKEB Output Pins

The output stage for the signals DO and WAKEB is shown

in Figure 4. The output is a 35µA push-35µA pull, switched

current stage. Such an output stage is capable of driving

CMOS-type loads. An external buffer-driver is

recommended for driving high capacitance loads.

5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is quite high (200kΩ). This is a Colpitts

oscillator, with internal 30pF capacitors. This input is

intended to work with standard ceramic resonators,

connected from this pin to VSSBB, although a crystal may

be used instead, where greater frequency accuracy is

required. The resonators should not contain integral

capacitors, since these capacitors are contained inside the

IC. Externally applied signals should be AC-coupled,

amplitude limited to approximately 0.5Vpp. The nominal

DC bias voltage on this pin is 1.4V.

6. Control Inputs (SEL0, SEL1, SWEN, SHUT)

Control input circuitry is shown in Figures 6a and 6b. The

standard input is a logic inverter constructed with minimum

geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a

large channel length device which functions essentially as a

“weak” pullup to VDDBB. Typical pullup current is 5µA,

leading to an impedance to the VDDBB supply of typically

1MΩ.

Figure 1 ANT Pin

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Figure 2 CTH Pin

Figure 5 REFOSC Pin

Figure 4 DO and WAKEB Pins

Figure 6b SHUT

Figure 3 CAGC Pin

Figure 6a SEL0, SEL1, SWEN

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Typical Application

Figure 7 below illustrates a typical application for the MICRF003 UHF Receiver IC. Operation in this example is at 915MHz,

and may be customized by selection of the appropriate reference frequency (CR1), and adjustment of the antenna length.

The value of C4 would also change, if the optional input filter is used. Changes from the 1kbps data rate may require a

change in the value of R1. The Bill of Materials is shown in the accompanying chart.

Bill of Materials

Item Part Number Manufacturer Description

U1 MICRF003 Micrel UHF Receiver

U2 HT-12D Holtek Logic decoder

CR1 CSA7.12MG Murata 7.12MHz Cer. Res.

D1 SSF-LX100LID Lumex RED LED

R1 Bourns 68k, 1/4W ,5%

R2 Bourns 1k,1/4W, 5%

C1 Panasonic 4.7µF, Dip Tant. Cap

C3 Panasonic 0.47µF, Dip Tant. Cap

C2 Panasonic 2.2µF, Dip Tant. Cap

C4 Panasonic 3.0 pF, COG Cer. Cap

Vendor Telephone Fax

Bourns (909) 781-5500 (909) 781-5273

Holtek (408) 894-9046 (408) 894-0838

Lumex (800) 278-5666 (847) 359-8904

Murata (800) 241-6574 (770) 436-3030

Panasonic (201) 348-7000 (201) 348-8164

Figure 7

915MHz, 1kbps OOK Receiver/Decoder

SWP Mode, Continuous Operation

6-Bit Address Decode/2 OP Codes

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MICRF003 Micrel

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October1999 MICRF003

MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights

of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.

This is preliminary

information and a final specification has not been completed. Before making any final design determination, consult with Micrel for final specifications.