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FEATURES DESCRIPTION
PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
0.1 µF
PG
VO
10 µF
+
TPS768xx
Co
GND
EN
IN
IN
PG
FB/NC
OUT
OUT
1
2
3
4
8
7
6
5
D PACKAGE
(Top View)
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
GND/HSINK
GND/HSINK
NC
NC
PG
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(Top View)
NC = No Internal Connection
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
FAST TRANSIENT RESPONSE, 1-A LOW-DROPOUT VOLTAGE REGULATORS
•Input Voltage Range: 2.7 V to 10 V
This device is designed to have a fast transientresponse and be stable with 10 µF capacitors. This•Low-Dropout Voltage: 230 mV typical at 1 A
combination provides high performance at a(TPS76850)
reasonable cost.•2% Tolerance Over Specified Conditions for
Since the PMOS device behaves as a low-valueFixed-Output Versions
resistor, the dropout voltage is very low (typically•Open Drain Power Good (See TPS767xx for
230 mV at an output current of 1 A for the TPS76850)Power-On Reset With 200-ms Delay Option)
and is directly proportional to the output current.•Ultralow 85 µA Typical Quiescent Current
Additionally, because the PMOS pass element is avoltage-driven device, the quiescent current is very•Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,
low and independent of output loading (typically3.0-V, 3.3-V, 5.0-V Fixed Output and
85 µA over the full range of output current, 0 mA toAdjustable (1.2 V to 5.5 V) Versions
1 A). These two key specifications yield a significant•Fast Transient Response
improvement in operating life for battery-powered•Thermal Shutdown Protection
systems. This LDO family also features a shutdownmode; applying a TTL high signal to EN (enable)•SOIC-8 (D) and TSSOP-20 (PWP) Package
shuts down the regulator, reducing the quiescentcurrent to less than 1 µA at T
J
= 25 °C.
Power good (PG) is an active high output, which canbe used to implement a power-on reset or alow-battery indicator.
Figure 1. Typical Application Configuration(For Fixed Output Options)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE—FREE-AIR TEMPERATURES
RECOMMENDED OPERATING CONDITIONS
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS768 xxQyyyz XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).YYY is package designator.Zis package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Custom output voltages are available; minimum order quantities may apply. Contact factory for details and availability.
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range, V
I
(2)
–0.3 V to 13.5 V
Voltage range at EN –0.3 V to V
I
+ 0.3 V
Maximum PG voltage 16.5 V
Peak output current Internally limited
Continuous total power dissipation See Dissipation Rating Table
Output voltage, V
O
(OUT, FB) 7 V
Operating junction temperature range, T
J
–40 °C to +125 °C
Storage temperature range, T
stg
–65 °C to +150 °C
ESD rating, HBM 2 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network terminal ground.
AIR FLOW T
A
< +25 °C DERATING FACTOR T
A
= +70 °C T
A
= +85 °CPACKAGE (CFM) POWER RATING ABOVE T
A
= +25 °C POWER RATING POWER RATING
0 568.18 mW 5.6818 mW/ °C 312.5 mW 227.27 mWD
250 904.15 mW 9.0415 mW/ °C 497.28 mW 361.66 mW
0 3.1 W 30.7 mW/ °C 1.7 W 1.2 WPWP
(1)
250 4.1 W 41.2 mW/ °C 2.3 W 1.6 W
(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer, 5-in ×5-in PCB, 1 oz. copper, 4-in ×4-incoverage (4 in
2
).
MIN MAX UNIT
Input voltage, V
I
(1)
2.7 10 V
Output voltage range, V
O
1.2 5.5 V
Output current, I
O
(2)
0 1.0 A
Operating junction temperature, T
J
(2)
–40 +125 °C
(1) Minimum V
IN
= V
OUT
+ V
DO
or 2.7 V, whichever is greater.(2) Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that thedevice operate under conditions beyond those specified in this table for extended periods of time.
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(2) If V
O
≤1.8 V then V
Imax
= 10 V, V
Imin
= 2.7 V:
LineReg. (mV) (%V) VOVImax2.7V
100 1000
If V
O
≥2.5 V then V
Imax
= 10 V, V
Imin
= V
O
+ 1 V:
LineReg. (mV) (%V) VOVImaxVO1V
100 1000
ELECTRICAL CHARACTERISTICS
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
over recommended operating free-air temperature range, V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = 0 V, C
O
= 10 µF (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
–40 °C≤T
J
≤+125 °C, V
O
+ 1 V ≤V
IN
≤10V
(1)
,V
OUT
Accuracy (0.98)V
O
V
O
(1.02)V
O
V10 µA≤I
O
≤1A
10 µA < I
O
< 1 A, T
J
= +25 °C 85Quiescent current (GND current) EN = 0V
(1)
µAI
O
= 1 A, T
J
= –40 °C to +125 °C 125
Output voltage line regulation ( ∆V
O
/V
O
)
(1) (2)
V
O
+ 1 V < V
I
≤10 V, T
J
= +25 °C 0.01 %/V
Load regulation 3 mV
BW = 200 Hz to 100 kHz, C
O
= 10 µF,Output noise voltage (TPS76818) 55 µVrmsI
C
= 1 A, T
J
= +25 °C
Output current limit V
O
= 0 V 1.2 1.7 2 A
Thermal shutdown junction temperature 150 °C
V
EN
= V
I
, T
J
= +25 °C, 2.7 V < V
I
< 10 V 1 µAStandby current
V
EN
= V
I
, T
J
= –40 °C to +125 °C,
10 µA2.7 V < V
I
< 10 V
FB pin current, I
FB
TPS76801 V
FB
= 1.5 V 2 nA
High-level enable input voltage 1.7 V
Low-level enable input voltage 0.9 V
Power-supply ripple rejection
(1)
f = 1 kHz, C
O
= 10 µF, T
J
= +25 °C 60 dB
Minimum input voltage for valid PG I
O(PG)
= 300 µA 1.1 V
Trip threshold voltage V
O
decreasing 92 98 %V
OPower
Good Hysteresis voltage Measured at V
O
0.5 %V
O(PG)
Output low voltage V
I
= 2.7 V, I
O(PG)
= 1 mA 0.15 0.4 V
Leakage current V
(PG)
= 5 V 1 µA
V
EN
= 0 V 1 0 1Enable pin current (I
EN
)µAV
EN
= V
I
1 1
I
O
= 1 A, T
J
= +25 °C 500TPS76828
I
O
= 1 A, T
J
= –40 °C to +125 °C 825
I
O
= 1 A, T
J
= +25 °C 450TPS76830
I
O
= 1 A, T
J
= –40 °C to +125 °C 675Dropout voltage
(3)
mVI
O
= 1 A, T
J
= +25 °C 350TPS76833
I
O
= 1 A, T
J
= –40 °C to +125 °C 575
I
O
= 1 A, T
J
= +25 °C 230TPS76850
I
O
= 1 A, T
J
= –40 °C to +125 °C 380
(1) Minimum IN operating voltage is 2.7 V or V
O(typ)
+ 1 V, whichever is greater. Maximum IN voltage 10 V.
(3) IN voltage equals V
O
(typ) – 100 mV; TPS76801 output voltage set to 3.3 V nominal with external resistor divider. TPS76815, TPS76818,TPS76825, and TPS76827 dropout voltage limited by input voltage range limitations (that is, TPS76830 input voltage must drop to 2.9 Vfor the purpose of this test).
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_
+
Vref = 1.1834 V
OUT
FB/NC
EN
GND
PG
_
+
IN
External to the device
R1
R2
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
_
+
IN
PG
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
FUNCTIONAL BLOCK DIAGRAM—Adjustable Version
FUNCTIONAL BLOCK DIAGRAM—Fixed-Voltage Version
Terminal Functions
SOIC-8 (D) TSSOP-20 (PWP)NAME PIN NO. PIN NO. DESCRIPTION
GND 1 3 Regulator groundGND/HSINK — 1, 2, 9-12, 19, 20 Regulator ground and heatsinkNC — 4, 8, 17, 18 No connectEN 2 5 Enable inputIN 3, 4 6, 7 Input voltageOUT 5, 6 13, 14 Regulated output voltageFB/NC 7 15 Feedback input voltage for adjustable device (no connect for fixed options)PG 8 16 PG output
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TYPICAL CHARACTERISTICS
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TPS76833 TPS76815OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 2. Figure 3.
TPS76825 TPS76833OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 4. Figure 5.
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TA − Free-Air Temperature − °C
− Output Voltage − V
VO
1.515
1.500
1.485 −40 0
1.510
1.505
1.495
−20 100−60 120
1.490
20 40 60 80
VI = 2.7 V
IO = 1 A
IO = 1 mA
140
TA − Free-Air Temperature − °C
− Output Voltage − V
VO
−40 0−20 100−60 12020 40 60 80
2.515
2.500
2.480
2.510
2.505
2.495
2.490
2.485
VI = 3.5 V
IO = 1 A
IO = 1 mA
TA − Free-Air Temperature − °C
Ground Current − Aµ
−40 0−20 100−60 12020 40 60 80 140
VI = 2.7 V
IO = 1 A
100
95
90
85
80
75
IO = 1 mA
IO = 500 mA
TA − Free-Air Temperature − °C
Ground Current − Aµ
92
84
72
90
88
82
80
78
76
74
86
−40 0−20 100−60 12020 40 60 80 140
VI = 4.3 V
IO = 500 mA
IO = 1 A
IO = 1 mA
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
TPS76815 TPS76825OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 6. Figure 7.
TPS76833 TPS76815GROUND CURRENT GROUND CURRENTvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 8. Figure 9.
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f − Frequency − Hz
102103104105
10−5
10−6
10−8
10−7
IO = 7 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
VHzOutput Spectral Noise Density − µ
3
2.7
21.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) − V
4
33.25 3.5
TA = 25°C
VI
VO − Output Voltage − V
IO = 1 A
TA = 125°C
TA = −40°C
f − Frequency − kHz
− Output Impedance −ZoΩ
101102105106
0
10−1
10−2 104
103
IO = 1 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
TPS76833 TPS76833POWER-SUPPLY RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 10. Figure 11.
TPS76833INPUT VOLTAGE (MIN) OUTPUT IMPEDANCEvs vsOUTPUT VOLTAGE FREQUENCY
Figure 12. Figure 13.
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TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
102
101
100
10−1
10−2 −20 140
IO = 1 A
IO = 10 mA
IO = 0
Co = 10 µF
t − Time − µs
VO− Change in VI− Input Voltage − V
∆
Output Voltage − mV
5.3
604020 80 100 140120 160 180 200
Co = 10 µF
TA = 25°C
0
4.3
10
0
−10
t − Time − µs
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
1
0.5
0
0 300200100 400 500 700600 800 900 1000
0
50
100
−50
−100
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
TPS76833
DROPOUT VOLTAGE TPS76815vs LINE TRANSIENT RESPONSEFREE-AIR TEMPERATURE
Figure 14. Figure 15.
TPS76815 TPS76833LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 16. Figure 17.
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t − Time − ms
3
2
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
VO− Output Voltage − V
0
1
4
Enable Pulse − V
Co = 10 µF
IO = 1 A
TA = 25°C
t − Time − µs
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
1
0.5
300200100 400 500 700600 800 900 10000
Co = 10 µF
TA = 25°C
0
0
50
100
−50
−100
IN
EN
OUT
+
GND Co
ESR
RL
VI
To Load
VI − Input Voltage − V
600
300
03 4
500
400
200
3.52.5
− Dropout Voltage − mV
100
4.5 5
VDO
900
800
700
TA = 125°C
TA = −40°C
TA = 25°C
IO = 1 A
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
TPS76833TPS76833 OUTPUT VOLTAGELOAD TRANSIENT RESPONSE vsTIME (AT START-UP)
Figure 18. Figure 19.
TPS76801 TEST CIRCUIT FOR TYPICAL REGIONS OF STABILITYDROPOUT VOLTAGE (Figure 22 through Figure 25 )vs (Fixed Output Options)INPUT VOLTAGE
Figure 20. Figure 21.
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IO − Output Current − mA
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
IO − Output Current − mA
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°CRegion of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
1
IO − Output Current − mA
0.01
Region of Instability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
IO − Output Current − mA
1
Region of Instability
Region of Stability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
0.01
Region of Instability
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, anyseries resistance added externally, and PWB trace resistance to C
O
.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 22. Figure 23.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 24. Figure 25.
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APPLICATION INFORMATION
DEVICE OPERATION
MINIMUM LOAD REQUIREMENTS
FB - PIN CONNECTION (ADJUSTABLE VERSION ONLY)
EXTERNAL CAPACITOR REQUIREMENTS
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
The TPS768xxQ family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V,3.3 V, and 5.0 V), and offers an adjustable device, the TPS76801 (adjustable from 1.2 V to 5.5 V).
The TPS768xxQ features very low quiescent current, which remains virtually constant even with varying loads.Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to theload current through the regulator (I
B
= I
C
/β). The TPS768xxQ uses a PMOS transistor to pass current; becausethe gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the PNP-pass element is its tendency to saturate when the device goes intodropout. The resulting drop in βforces an increase in I
B
to maintain the load. During power up, this translates tolarge start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, itmeans rapid battery discharge when the voltage decays below the minimum required for regulation. TheTPS768xxQ quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS768xxQ family also features a shutdown mode that places the output in the high-impedance state(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdownfeature is not used, EN should be tied to ground.
The TPS768xxQ family is stable even at zero load; no minimum load is required for operation.
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The outputvoltage is sensed through a resistor divider network to close the loop as shown in Figure 27 . Normally, thisconnection should be as short as possible; however, the connection can be made near a critical circuit toimprove performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier andnoise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup isessential.
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improvesload transient response and noise rejection if the TPS768xxQ is located more than a few inches from the powersupply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) loadtransients with fast rise times are anticipated.
Like all low dropout regulators, the TPS768xxQ requires an output capacitor connected between OUT and GNDto stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR(equivalent series resistance) must be between 60 m Ωand 1.5 Ω. Capacitor values 10 µF or larger areacceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayerceramic capacitors are all suitable, provided they meet the requirements described above.
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PG
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
C1
0.1 µF
PG
VO
10 µF
+
TPS768xx
Co
250 kΩ
VOVref 1R1
R2
where:
Vref = 1.1834 V typ (the internal reference voltage)
(1)
R1 VO
Vref 1R2
(2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
4.75 V
UNIT
33.2
53.6
61.9
90.8
30.1
30.1
30.1
30.1
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIPG
OUT
FB / NC
R1
R2
GND
EN
IN
≤ 0.9 V
≥ 1.7 V
TPS76801
PG
0.1 µF250 kΩ
POWER-GOOD INDICATOR
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
APPLICATION INFORMATION (continued)
Figure 26. Typical Application Circuit (Fixed Versions)
The output voltage of the TPS76801 adjustable regulator is programmed using an external resistor divider asshown in Figure 27 . The output voltage is calculated using:
Resistors R1 and R2 should be chosen for approximately 50- µA divider current. Lower value resistors can beused but offer no inherent advantage and waste more power. Higher values should be avoided as leakagecurrents at FB increase the output voltage error. The recommended design procedure is to chooseR2 = 30.1 k Ωto set the divider current at 50 µA and then calculate R1 using:
Figure 27. TPS76801 Adjustable LDO Regulator Programming
The TPS768xxQ features a power-good (PG) output that can be used to monitor the status of the regulator. Theinternal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominalregulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullupresistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as alow-battery indicator. PG does not assert itself when the regulated output voltage falls out of the specified 2%tolerance, but instead reports an output voltage low, relative to its nominal regulated value.
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REGULATOR PROTECTION
POWER DISSIPATION AND JUNCTION TEMPERATURE
PDmax
TJmaxTA
RJA
(3)
PDVIVOIO
(4)
TPS768xxQ
SLVS211L – JUNE 1999 – REVISED JANUARY 2006
APPLICATION INFORMATION (continued)
The TPS768xxQ PMOS-pass transistor has a built-in back diode that conducts reverse currents when the inputvoltage drops below the output voltage (for example, during power-down). Current is conducted from the outputto the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may beappropriate.
The TPS768xxQ also features internal current limiting and thermal protection. During normal operation, theTPS768xxQ limits output current to approximately 1.7 A. When current limiting engages, the output voltagescales back linearly until the overcurrent condition ends. While current limiting is designed to prevent grossdevice failure, care should be taken not to exceed the power dissipation ratings of the package. If thetemperature of the device exceeds +150 °C (typ), thermal-protection circuitry shuts it down. Once the device hascooled below +130 °C (typ), regulator operation resumes.
Specified regulator operation is assured to a junction temperature of +125 °C; the maximum junction temperatureshould be restricted to +125 °C under normal operating conditions. This restriction limits the power dissipation theregulator can handle in any given application. To ensure the junction temperature is within acceptable limits,calculate the maximum allowable dissipation, P
D
max, and the actual dissipation, P
D
, which must be less than orequal to P
D
max.
The maximum-power-dissipation limit is determined using the following equation:
Where:
•T
J
max is the maximum allowable junction temperature.•R
θJA
is the thermal resistance junction-to-ambient for the package; that is, 172 °C/W for the 8-pin SOIC (D)and 32.6 °C/W for the 20-pin TSSOP (PWP) with no airflow.•T
A
is the ambient temperature.
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger thethermal protection circuit.
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PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS76801QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76801QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76801QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76801QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76801QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76801QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76801QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76801QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76815QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76815QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76815QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76815QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76815QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76815QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76815QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76815QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76818QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS76818QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76818QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76818QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76818QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76818QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76818QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76818QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76825QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76825QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76825QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76825QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76825QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76825QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76825QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76825QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76827QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76827QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76827QPWP ACTIVE HTSSOP PWP 20 TBD Call TI Call TI
TPS76827QPWPG4 ACTIVE HTSSOP PWP 20 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS76828QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76828QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76830QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76830QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76830QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76830QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76833QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76833QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76833QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76833QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76833QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76833QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76833QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76833QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76850QD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76850QDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76850QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS76850QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS76850QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76850QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76850QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS76850QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS76801, TPS76815, TPS76818, TPS76825, TPS76827, TPS76828, TPS76830, TPS76833, TPS76850 :
•Automotive: TPS76801-Q1, TPS76815-Q1, TPS76818-Q1, TPS76825-Q1, TPS76827-Q1, TPS76828-Q1, TPS76830-Q1, TPS76833-Q1, TPS76850-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 5
•Enhanced Product: TPS76801-EP, TPS76815-EP, TPS76818-EP, TPS76825-EP, TPS76833-EP, TPS76850-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS76801QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76801QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76801QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS76815QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76815QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS76818QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76818QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS76825QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76825QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS76833QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76833QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS76850QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS76850QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS76801QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76801QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76801QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS76815QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76815QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS76818QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76818QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS76825QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76825QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS76833QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76833QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS76850QDR SOIC D 8 2500 367.0 367.0 35.0
TPS76850QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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