Rev.2.00 Jan 31, 2006 page 1 of 9
HD74HC259
8-bit Addressable Latch REJ03D0603–0200
(Previous ADE-205-480)
Rev.2.00
Jan 31, 2006
Description
The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable
input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the
address of the latch into which the data is to be entered is held on the A, B and C inputs. When enable is taken low the
data flows through to the addressed outpu t. The data is stored when enable transitions from low to high. All
unaddressed latches will remain unaffected. With enable in the high state the device is deselected, and all latches
remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of
entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing.
If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all latches except
the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3-
to-8 line decoder.
Features
High Speed Operation: tpd (Data to Output) = 16 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74HC259P DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74HC259FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
HD74HC259RPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
HD74HC259
Rev.2.00 Jan 31, 2006 page 2 of 9
Function Table
Inputs
Clear G
Output of Addressed
Latch Each Other Output Function
H L D Qio Addressable latch
H H Qio Qio Memory
L L D L 8-line demultiplexer
L H L L Clear
Select Inputs
C B A
Latch Addressed
L L L 0
L L H 1
L H L 2
L H H 3
H L L 4
H L H 5
H H L 6
H H H 7
Notes: 1. D: the level at the data input
2. Qio: the level of Qi (i = 0, 1, ···7, as appropriate) before the indicated steady-state input conditions were
established.
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
A
B
C
Q0
Q1
Q2
Q3
GND
VCC
Clear
Enable
Q7
Q6
Q5
Q4
16
15
14
13
12
11
10
9
B
C
Q0
Q1
Q2
Q3
CLR
G
D
Q7
Q6
Q5
A
Q4
Data
input
Outputs
Outputs
Latch
select
HD74HC259
Rev.2.00 Jan 31, 2006 page 3 of 9
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range VCC –0.5 to 7.0 V
Input / Output voltage VIN, VOUT –0.5 to VCC +0.5 V
Input / Output diode current IIK, IOK ±20 mA
Output current IO ±25 mA
VCC, GND current ICC or IGND ±50 mA
Power dissipation PT 500 mW
Storage temperature Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item Symbol Ratings Unit Conditions
Supply voltage VCC 2 to 6 V
Input / Output voltage VIN, VOUT 0 to VCC V
Operating temperature Ta –40 to 85 °C
0 to 1000 VCC = 2.0 V
0 to 500 VCC = 4.5 V
Input rise / fall time*1 t
r, tf
0 to 400
ns
VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input s witches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C Ta = –40 to+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
2.0 1.5 1.5
4.5 3.15 3.15
VIH
6.0 4.2 4.2
V
2.0 — 0.5 0.5
4.5 — 1.35 1.35
Input voltage
VIL
6.0 — 1.8 1.8
V
2.0 1.9 2.0 1.9
4.5 4.4 4.5 4.4
6.0 5.9 6.0 5.9
IOH = –20 µA
4.5 4.18 4.13 IOH = –4 mA
VOH
6.0 5.68 5.63
V Vin = VIH or VIL
IOH = –5.2 mA
2.0 — 0.0 0.1 0.1
4.5 — 0.0 0.1 0.1
6.0 — 0.0 0.1 0.1
IOL = 20 µA
4.5 — 0.26 0.33 IOL = 4 mA
Output voltage
VOL
6.0 — 0.26 0.33
V Vin = VIH or VIL
IOL = 5.2 mA
Input current Iin 6.0 ±0.1 — ±1.0 µA Vin = VCC or GND
Quiescent supply
current ICC 6.0 4.0 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC259
Rev.2.00 Jan 31, 2006 page 4 of 9
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C Ta = –40 to +85°CItem Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
2.0 — 185 230
4.5 — 16 37 46
6.0 — 31 39
ns Data to output
2.0 — 215 270
4.5 — 20 43 54
6.0 — 37 46
ns Latch select to output
2.0 — 200 250
4.5 — 17 40 50
tPHL
tPLH
6.0 — 34 43
ns Enable to output
2.0 — 155 195
4.5 — 15 31 39
Propagation delay
time
tPHL
6.0 — 26 33
ns Clear to output
2.0 80 100
4.5 16 6 20
Pulse width tw
6.0 14 17
ns Clear, Enable
2.0 100 125
4.5 20 5 25
Setup time tsu
6.0 17 21
ns Latch select or data to enable
2.0 5 5
4.5 5 –1 5
Hold time th
6.0 5 5
ns Latch select or data to enable
2.0 — 75 95
4.5 — 5 15 19
Output rise/fall
time tTLH
tTHL 6.0 — 13 16
ns
Input capacitance Cin 5 10 10 pF
Test Circuit
V
CC
C =
50 pF
G
Z
out
= 50
Input
V
CC
L
Output
Q
0 to
Q
7
D
B
A
Clear
C
Note : 1. C
L
includes probe and jig capacitance.
See Function Table
Pulse Generator
HD74HC259
Rev.2.00 Jan 31, 2006 page 5 of 9
Waveforms
Enable G
Addressed
Output Q
Clear
V
CC
50%
50%
V
OL
V
OH
0 V
V
CC
0 V
1. Input pulse : PRR 1 MHz, Zo = 50 Ω, t
r
6 ns, t
f
6 ns
2.
D = V
CC
, Unaddressed Q = L
Notes :
t
r
Waveform – 1
t
f
50%
t
THL
90%
10%
t
PHL
t
w (Clear)
90%
10%
90%
10%
t
r
t
f
90%
10%
90%
10%
Output Q
Data
50%
50%
V
OL
V
OH
0 V
V
CC
1. Input pulse : PRR 1 MHz, Zo = 50 , t
r
6 ns, t
f
6 ns
2. Other input : G = GND, Clear = Vcc, A to C = Address
Notes :
t
PLH
90%
10% 10%
t
r
90%
Waveform – 2
50%
t
f
t
TLH
t
THL
90%
10% 10%
90%
t
PHL
50%
HD74HC259
Rev.2.00 Jan 31, 2006 page 6 of 9
VOH
VOL
0 V
VCC
50 %
Data
0 V
VCC
Address
(A to C)
10 %
90 %
tr
10 %
tf
Waveform – 3
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
2. Other input : G = GND, Clear = VCC, A to C = Address
10 %
90 %
tTLH
10 %
tTHL
VOH
Addressed
Output Q
tPHL
50 %
50 %
50 % 50 %
tPLH
VOL
Addressed
Output Q
90 %
90 %
Data
Qn
V
CC
50%
50%
V
OL
V
OH
0 V
1. Input pulse : PRR 1 MHz, Zo = 50 , t
r
6 ns, t
f
6 ns
2. Other input : Clear = V
CC
, A to C = Address
Notes :
G
0 V
V
CC
90%
50%
10%
90%
10%
50%
t
PLH
t
PHL
t
TLH
t
THL
t
f
t
r
Waveform – 4
50%50%50%
50% 50%
t
su(H)
t
su(L)
t
h(H)
t
h(L)
t
w(G)
90%
10%
90%
10%
HD74HC259
Rev.2.00 Jan 31, 2006 page 7 of 9
0 V
V
CC
Data
Waveform – 5
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
2. Other input : Clear = VCC
3. Address inputs except appropriate inputs are set to address to appropriate Q outputs.
0 V
V
CC
G
Address
Input
50 %
50 %
tsu
50 % 50 % 50 % 50 %
thtsu
VOH
VOL
Qn
t
h
0 V
V
CC
HD74HC259
Rev.2.00 Jan 31, 2006 page 8 of 9
Package Dimensions
7.62
DP-16FV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
1.05g
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0016AE-BP-DIP16-6.3x19.2-2.54
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
0.80
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-16DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.24g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP16-5.5x10.06-1.27 PRSP0016DH-B
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74HC259
Rev.2.00 Jan 31, 2006 page 9 of 9
0.635
0.15
1.27
5.80 6.20
0.400.34
p
A
1
10.30
FP-16DNV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8
°
0
°
0.25
1.08
9.90
0.15g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
e
L
A
P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
xM
p
*3
*2
*1
F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .5.0