FINAL
Publicati on# 14971 Rev: GAmendment/0
Issue Date: May 1998
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPRO M
DISTINCTIVE CHARACTERISTICS
■Fast access time
— Available in speed options as fast as 90 ns
■Low power consumptio n
— <10 µA typical CMOS standby current
■JEDEC-approved pinout
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
— Easy upgrade from 28-pin JEDEC EPROMs
■Single +5 V power supply
■±10% power supply tolerance standard
■100% Flashrite™ programming
— Typical programming time of 1 minute
■Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■High noise immunity
■Compact 32-pin DIP, PDIP, PLCC packages
GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable pro-
grammable read-only memory. It is organized as 512K
bytes, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The devic e is availab le in win dowed
ceramic DIP packages and plastic one-time program-
mable (OTP) packages.
Data can be typically accessed in less than 90 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating b us contention in a multiple b us micro-
proc esso r sys te m.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 50 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses) re-
sulting in typical programming time of 1 minute.
BLOCK DIAGRAM
14971G-1
A0–A18
Address
Inputs
CE#/PGM#
OE#
VCC
VSS
VPP
Data Outputs
DQ0–DQ7
Output
Buffers
Y
Gating
4,194,304-Bit
Cell Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
2 Am27C040
FINAL
PRODUCT SELECTOR GUIDE
CONNECTION DIAGRAMS
Top View
DIP PLCC
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
A0–A18 = Address Inputs
CE# (E#)/PGM# (P#)= Chip Enable/Program Enable Input
DQ0–DQ7 = Data Inputs/Outputs
OE# (G#) = Output Enable Input
VCC =V
CC Supply Voltage
VPP = Program Voltage Input
VSS = GroundLogic Symbol
LOGIC SYMBOL
Family Part Number Am27C040
Speed Options (VCC = 5.0 V ± 10%) -90 -120 -150 -200
Max Access Time (ns) 90 120 150 200
CE# (E#) Access (ns) 90 120 150 200
OE# (G#) Access (ns) 40 50 65 75
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE# (G#)
A10
CE# (E#)/PGM# (P#)
DQ7
VCC
A18
DQ6
A17
A14
A13
DQ5
DQ4
DQ3
VPP
14971G-2
5
6
7
8
9
10
11
12
13 17 18 19 20161514
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
131 3023432
A14
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)/PGM# (P#)
DQ7
A12
A15
A16
VPP
VCC
A18
A17
14971G-3
19
8
DQ0–DQ7
A0–A18
OE# (G#)
14971E-4
CE# (E#)/PGM#(P#)
Am27C040 3
FINAL
ORDERING INFORMATION
UV EPROM Products
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS UV EPROM
AM27C040 -90 D C
OPTION AL PROCES SI NG
Blank = Standard Processing
B = Burn-In
TEMPER ATURE RANGE
C = Commercial (0°C to +70°C)
I=Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYP E
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and
Va lid Com bin ati ons
Valid Combinations
AM27C040-90
DC, DCB, DI, DIB, DE, DEB
AM27C040-120
AM27C040-150
AM27C040-200
4 Am27C040
FINAL
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUM BE R/ DES CR IP TIO N
Am27C040
4 Megabit (512K x 8-Bit) CMOS OTP EPROM
AM27C040 -90 J C
OPTIONAL PROCESSING
Blank = Standard Pro ces sin g
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I=Industrial (–40°C to +85°C)
E = Extended (–55°C to 125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
Valid Combinations
AM27C040-90
PC, PI, JC, JI
AM27C040-120
AM27C040-150
AM27C040-200
Am27C040 5
FINAL
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 15 W seconds/cm2 is required
to completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm2 f or 15 to 20
minutes. The device should be directly under and about
one inch from the source and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources hav ing wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of it s bits in the “ONE”, or HIGH stat e. “ZE ROs” are
loaded into the device through the programming pro-
cedure.
The programming mode is entered when 12.75 V ±
0.25 V is applied to the VPP pin, CE#/PGM# is at VIL
and OE# is at VIH .
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data output pins.
The flowchar t in the EPROM Products Data Book, Pro-
gramming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces pro-
gramming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reli-
ably program the data. After each pul se is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each ad-
dress of the device . This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at VCC = VPP = 5.25 V.
Please refer to the EPROM Products Data Book, Sec-
tion 5 for the programming flow chart and characteris-
tics.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with VPP = 12.75 V ± 0.25 V will program
that particular dev ice . A high -lev el CE#/PG M# in put in-
hibits the other devices from being programmed.
Program Verify
A v erificat ion should be performed on the prog r ammed
bits to determine that the y were correct ly programmed.
The verify should be performed with OE# at VIL, CE#/
PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gra mming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the de vice outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the de vice outputs, Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the powe r to the dev ice and is t yp-
ically used to select the device. OE# enables the de vice
to output data, independent of device selection. Ad-
dresses must be stable for at least tACC–tOE. Refer to
the Switching Waveforms section for the timing dia-
gram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at VCC ± 0.3 V. Maximum VCC current is
reduced to 100 µA. The device ent ers t he TTL-standb y
mode when CE#/PGM# is at VIH. Maximum VCC cur-
rent is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-imped-
ance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
■Low memory power dissipation, and
■Assurance that output bus contention will not occur
CE#/PGM# should be decoded and used as the pri-
mary device-selecting function, while OE# be made a
6 Am27C040
FINAL
common connection to all de vices in the arr a y and con-
nected to the READ line from the system control bus.
This assures that all deselec ted memory de vices are in
their lo w-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and f alling edges of Chip Enab le . The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of t he device . At a minim um, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPR OM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between V CC and VSS for each eight de vi ces. The loca-
tion of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
Note:
1. V
H
= 12.0 V
±
0.5 V.
2. X = Either VIH or VIL
3. A1 – A8 = A10 – A18 = VIL
4. See DC Programming Characteristics in the EPROM Products Data Book for VPP voltage during programming
Mode CE#/PGM# OE# A0 A9 VPP Outputs
Read VIL VIL XXXD
OUT
Output Disable VIL VIH X X X HIGH Z
Standby (TTL) VIH X X X X HIGH Z
Standby (CMOS) VCC + 0.3 V X X X X HIGH Z
Program VIL VIH XXV
PP DIN
Program Verify VIL VIL XXV
PP DOUT
Program Inhibit VIH XXXV
PP HIGH Z
Auto Select
(Note 3)
Manufacturer Code VIL VIL VIL VHX 01h
Device Code VIL VIL VIH VHX 9Bh
Am27C040 7
FINAL
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products . . . . . . . . . . . . . . . . –65°C to +125°C
All Oth er Products. . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Voltage with Respect to VSS
All pins except A9, VPP
,
VCC (Note 1) . . . . . . . . . . . . . . –0.6 V to VCC +0.5 V
A9 and VPP (Note 2) . . . . . . . . . . . .–0.6 V to +13.5 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . .–0.6 V to +7.0 V
1. During v oltage transitions, inputs may overshoot VSS to –
2.0 V for periods of up to 20 ns. Maximum DC voltage on
input and I/O pins may overshoot to V CC + 2.0 V for
periods up to 20ns.
2. During voltage transi tion s, A9 and VPP may overshoot
VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must
not exceed +13.5 V at any time.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions abov e those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to ab solu te m axi mum ratin g co ndi tion s for
extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) De vices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
Supply Read Voltages
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
8 Am27C040
FINAL
DC CHARACTERISTICS over operating ranges unless otherwise specified
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maxi-
mum DC Voltage on output pins is Vcc +0.5 V, which may overshoot to VCC +2.0 V for periods less than 20 ns.
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to VCC C/I Devices 1.0 µA
E Devices 5.0
ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA
ICC1 VCC Active Current (Note 3) CE# = VIL, f = 10 MHz,
IOUT = 0 MA
C/I Devices 40 mA
E Devices 60
ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA
ICC3 VCC CMOS Standby
Current CE# = VCC ± 0.3 V 100 µA
IPP1 VPP Current During Read CE# = OE# = VIL, VPP
= VCC 100 µA
1610
25
15
5
10
20
2345 78 9
Frequency in MHz
Supply Current
in mA
Figure 1. Typical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°C
14971E-1
–75 50 150
25
15
5
10
20
–50 –25 0 25 75 100 125
Temperature in °C
Supply Current
in mA
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
14971E-1
Am27C040 9
FINAL
TEST CONDITIONS
Table 1. Test Specifications
SWITCHING TEST WAVEFORM
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
14971G-5
Figure 1. Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition All Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 100 pF
Input Rise and Fall Times ≤ 20 ns
Input Pulse Levels 0.45–2.4 V
Input timing measurement reference
levels 0.8, 2.0 V
Output timing measurement
reference levels 0.8, 2.0 V
2.4 V
0.45 V Input Output
Te st Points
2.0 V 2.0 V
0.8 V0.8 V
14971G-6
3 V
0 V Input Output
1.5 V 1.5 V
Te st Points
Note: For CL = 100 pF.Note: For CL = 30 pF.
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
10 Am27C040
FINAL
AC CHARACTERISTICS
Caution: Do not remove the device from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP
, and removed simultaneously or after VPP
.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 1 and Table 1 for test specifications.
SWITCHING WAVEFORMS
PACKAGE CAPACITANCE
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25
°
C, f = 1 MHz.
Parameter Symbols
Description Test Setup
Am27C040
UnitJEDEC Std. -90 -120 -150 -200
tAVQV tACC Address to Output Delay CE# = OE#
= VIL Max 90 120 150 200 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 120 150 200 ns
tGLQV tOE Output Enable to Output Delay CE# = VIL Max40506575ns
t
EHQZ
tGHQZ
tDF
(Note 2) Chip Enable High or Output Enable High,
Whichever Occurs First, to Output High Z Max30303040ns
t
AXQX tOH Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First Min0000ns
Parameter
Symbol Parameter
Description Test
Conditions
CDV032 PD 032 PL 032
UnitTyp Max Typ Max Typ Max
CIN Input Capacitance VIN = 0 V 10121012 8 10pF
C
OUT Output Capacitance VOUT = 0 V 12151215 9 12pF
Addresses
CE#/PGM#
OE#
Output
Address es Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF
(Note 2)
tOH
Note:
1. OE# ma y be delay ed up to tACC - tOE after the f alling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
14971E-1
Am27C040 11
FINAL
PH YS ICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.670
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160 .016
.022
SEATING PLANE
.015
.060
16-038-S_AG
PD 032
EC75
5-28-97 lv
32 17
16 .630
.700
0°
10°
.600
.625
.009
.015
.050 REF.
.026
.032 TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF. .490
.530
12 Am27C040
FINAL
PH YS ICAL DIMENSIONS *
CDV032—32-Pin Ceramic DIP, UV Lens (measured in inches)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
REVISION SUMMARY FOR AM27C040
Revision E/1
Product Selector Guide:
Added -90 (90 ns, ±10% VCC) and deleted -100 speed options.
Ordering Information, UV EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations:
Added -90 and deleted -100 speed options in valid combinations.
Ordering Information, OTP EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations:
Added -90 and deleted -100 speed options in valid combinations.
Programming the Am27C040:
The fourth paragraph should read, “Please refer to Section 5 for programming…”.
TOP VIEW
SIDE VIEW END VIEW
INDEX AND
TERMINAL NO. 1
I.D. AREA
.565
.605
1.635
1.680
.005 MIN .045
.065 .014
.026 .100 BSC
.015
.060
.160
.220
.125
.200
BASE PLANE
SEATING PLANE
.300 BSC .600
BSC .008
.018
94°
105°
.700
MAX
16-000038H-3
CDV032
DF11
3-30-95 ae
DATUM D
CENTER PLANE
DATUM D
CENTER PLANE
1
UV Lens
Am27C040 13
FINAL
Operating Ranges:
Changed Supply Read V o ltages listings to match those
in the Product Selector Guide.
AC Characteristics:
Added -90 and deleted - 100 speed options in tab le, re-
arranged notes, moved text from table title to Note 4,
renamed table.
Revision F
Deleted -255 speed option.
Changed all active low signal designations from over-
bars or trailing “#”s.
Revision G
Global
Made form atting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Distinctive Characteristics:
Low P o wer Consumption:
Changed “100 µA maxim um”
to “<10 µA typical”.
TSOP package deleted.
General Description:
In the third paragraph, changed “100 µW in standby
mode” to 50 µW in standby mode”.
Connection Diagrams:
Deleted TSOP Pinout figure.
Pin Designations:
Changed “Chip Enable I nput” to “Chip Enab le/Prog ram
Enable Input”.
Ordering Information:
UV EPROM Products:
Changed -75 speed option to
-90.
OTP EPROM Products:
Changed -75 speed option to
-90.
Temperature Range:
Added “E = Extended (–55°C to
125°C)”.
Package Type:
Deleted “E = 32-pin Thin Small Outline
Package (TSO P) Standard Pinout (TS 032)”.
Valid Combinations:
Deleted EC and EI options.
Functional Description:
Replaced device specific text with generic text.
Test Conditions:
New section with Test Setup Figure and Test Specifica-
tions Table.
Switching Test Waveform:
Modified figure.
Operating Ranges:
Supply Read Voltages:
Replaced with generic data.
DC Characteristics:
Modified Figures 1 and 2.
Switching Waveform:
Corrected “DF” to “t
DF
” in Note 2.
Package Capacitance:
Deleted TSOP data.
Physi cal Dimensions:
New section, added f igures f or the 32-Pin Ceramic DIP,
32-Pin Plastic DIP, and 32-Pin Plastic Leaded Chip
Carrier.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights rese rved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
