kyz_ SGS;THOMSON ST6x86 P90+, P120+, P133+, P150+, P166+ 3.52 Volt ST6x86 CPU Sixth-Generation Superscalar Superpipelined Architecture - Dual 7-stage integer pipelines - High performance on-chip FPU with 64-bit interface - Operating at P90+ speeds and above - 16-KByte write-back cache X86 Instruction Set Compatible - Runs Windows 95, Windows NT, DOS, UNIX, Novell, OS/2, Solaris, and others PRELIMINARY DATA Optimum Performance for Windows 95 - Intelligent instruction dispatch - Out-of-order execution - Register renaming - Data forwarding - Branch prediction - Speculative execution 64-Bit Data Bus - P54C socket compatible for quick time to market The ST6x86" microprocessor is a superscalar, superpipelined CPU that provides sixth-generation performance for x86 software. Since the ST6x86 CPU is fully compatible with the x86 instruction set, it is capable of executing a wide range of exist- ing operating systems and applications, including Windows 95, DOS, Unix, Windows NT, Novell, OS/2, and Solaris. The ST6x86 CPU achieves top performance levels through the use of two opti- mized superpipelined integer units and an on-chip floating point unit. The superpipelined architecture reduces timing constraints and allows the ST6x86 CPU to achieve P90+ performance levels and above. In addition, the ST6x86 CPUs integer and floating point units are optimized for maximum instruction throughput by using advanced architec- tural techniques, including register renaming, out-of-order execution, data forwarding, branch prediction, and speculative execution. These design innovations eliminate many data depen- dencies and resource conflicts that provide opti- mum performance for Windows 95 software. BLOCK DIAGRAM Instruction Address IF Sequence ID1 Instruction Data q 128 a2 Control ID2 D2 Lines Ac1 AG a nce Ac2 <> 2 Bus BET# BEG EX EX 256-Byte Instruction 3 . Interface WB WE 32 Line Gachs Unit One xP Pi Data ipe ipe Floating Poin eg OPCode | m . Queue Integer Unit 2 16- KByte Unified Cache ata > D63-D0 a2 32 Cache Unit 6 64 Floating Point X Linear Y Linear Pracaseor Address Addrese < A A lq ox Floating Polnt Unit v v 64 42 X Physical Physical Addrass Address <-> Contral Mamory Management Unit 32 Bus Interface 1AFaasoz August 1996 1/53 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.ST6x86 1.0 ARCHITECTURE OVERVIEW The SGS-THOMSON ST6x86 CPU is a leader in the sixth generation of high performance, x86-compatible microprocessors. Increased per- formance is accomplished by the use of supersca- lar and superpipelined design techniques. The ST6x86 CPU is superscalar in that it contains two separate pipelines that allow multiple instruc- tions to be processed at the same time. The use of advanced processing technology and_ the increased number of pipeline stages (superpipelin- ing) allow the ST6x86 CPU to achieve clocks rates of 80, 100, 110, 120, 183 MHz and above. Through the use of unique architectural features, the ST6x86 processor eliminates many data dependencies and resource conflicts, resulting in optimal performance for both 16-bit and 32-bit x86 software. The ST6x86 CPU contains two caches: a 16-KByte dual-ported unified cache and a 256-byte instruction line cache. Since the unified cache can store instructions and data in any ratio, the unified cache offers a higher hit rate than sepa- rate data and instruction caches of equal size. An increase in overall cache-to-integer unit bandwidth is achieved by supplementing the unified cache with a small, high-speed, fully associative instruc- tion line cache. The inclusion of the instruction line cache avoids excessive conflicts between code and data accesses in the unified cache. The on-chip FPU allows floating point instructions to execute in parallel with integer instructions and features a 64-bit data interface. The FPU incorpo- rates a four-deep instruction queue and a four-deep store queue to facilitate parallel execu- tion. The ST6x86 CPU operates from a 3.3 volt power supply resulting in reasonable power consumption at all frequencies. In addition, the ST6x86 CPU incorporates a low power suspend mode, stop clock capability, and system management mode (SMM) for power sensitive applications. k SGS-THOMSON TF UR aeLECT EMS 1.1. Major Functional Blocks The ST6x86 processor consists of five major func- tional blocks, as shown in the overall block dia- gram on the first page of this manual: - Integer Unit - Cache Unit - Memory Management Unit - Floating Point Unit - Bus Interface Unit Instructions are executed in the X and Y pipelines within the Integer Unit and also in the Floating Point Unit (FPU). The Cache Unit stores the most recently used data and instructions to allow fast access to the information by the Integer Unit and FPU. Physical addresses are calculated by the Memory Management Unit and passed to the Cache Unit and the Bus Interface Unit (BIU). The BIU provides the interface between the external system board and the processor's internal execution units. 2/53ST6x86 1.2 Integer Unit The Integer Unit (Figure 1.1) provides parallel ger pipelines. Each of the two pipelines, X and Y, instruction execution using two seven-stage inte- can process several instructions simultaneously. Figure1.1. Integer Unit a Instruction Fetch Instruction Decode 1 In-Order Instruction Instruction Processing Decode 2 Decode 2 Address Address Calculation 1 Calculation 1 Address Address t Calculation 2 Calculation 2 zx | | Execution Execution Out-of-Order | | Completion Write-Back Write-Back Zz X Pipeline Y Pipeline 1727301 3/53 as SGS-THOMSON + LICROELESTRONIESST6x86 The Integer Unit consists of the following pipeline stages: - Instruction Fetch (IF) - Instruction Decode 1 (ID1) - Instruction Decode 2 (ID2) - Address Calculation 1 (AC1) - Address Calculation 2 (AC2) - Execute (EX) - Write-Back (WB) The instruction decode and address calculation functions are both divided into superpipelined stages. 1.2.1 Pipeline Stages The Instruction Fetch (IF) stage, shared by both the X and Y pipelines, fetches 16 bytes of code from the cache unit in a single clock cycle. Within this section, the code stream is checked for any branch instructions that could affect normal pro- gram sequencing. If an unconditional or conditional branch is detected, branch prediction logic within the IF stage generates a predicted target address for the instruction. The IF stage then begins fetching instructions at the predicted address. The superpipelined Instruction Decode function contains the ID1 and ID2 stages. |ID1, shared by both pipelines, evaluates the code stream pro- vided by the IF stage and determines the number of bytes in each instruction. Up to two instructions per clock are delivered to the ID2 stages, one in each pipeline. The ID2 stages decode instructions and send the decoded instructions to either the X or Y pipeline for execution. The particular pipeline is chosen, based on which instructions are already in each pipeline and how fast they are expected to flow through the remaining pipeline stages. k SGS-THOMSON TF UR aeLECT EMS The Address Calculation function contains two stages, AC1 and AC2. If the instruction refers to a memory operand, the AC1 calculates a linear memory address for the instruction. The AC2 stage performs any required memory management functions, cache accesses, and reg- ister file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the FPU for processing. The Execute (EX) stage executes instructions using the operands provided by the address calcu- lation stage. The Write-Back (WB) stage is the last IU stage. The WB stage stores execution results either to a register file within the IU or to a write buffer in the cache control unit. 1.2.2 Out-of-Order Processing If an instruction executes faster than the previous instruction in the other pipeline, the instructions may complete out of order. All instructions are pro- cessed in order, up to the EX stage. While in the EX and WBstages, instructions may be completed out of order. If there is a data dependency between two instruc- tions, the necessary hardware interlocks are enforced to ensure correct program execution. Even though instructions may complete out of order, exceptions and writes resulting from the instructions are always issued in program order. 4/53ST6x86 1.2.3 Pipeline Selection In most cases, instructions are processed in either pipeline and without pairing constraints on the instructions. However, certain instructions are pro- cessed only in the X pipeline: - Branch instructions - Floating point instructions - Exclusive instructions Branch and floating point instructions may be paired with a second instruction in the Y pipeline. Exclusive Instructions cannot be paired with instructions in the Y pipeline. These instructions typically require multiple memory accesses. Although exclusive instructions may not be paired, hardware from both pipelines is used to accelerate instruction completion. Listed below are the ST6x86 CPU exclusive instruction types: - Protected mode segment loads - Special register accesses (Control, Debug, and Test Registers) - String instructions - Multiply and divide - |/O port accesses - Push all (PUSHA) and pop all (POPA) - Intersegment jumps, calls, and returns 5/53 k SGS-THOMSON TF UR aeLECT EMS 1.2.4 Data Dependency Solutions When two instructions that are executing in paral- lel require access to the same data or register, one of the following types of data dependencies may occur: - Read-After-Write (RAW) - Write-After-Read (WAR) - Write-After-Write (WAW) Data dependencies typically force serialized exe- cution of instructions. However, the ST6x86 CPU implements three mechanisms that allow parallel execution of instructions containing data depen- dencies: - Register Renaming - Data Forwarding - Data Bypassing The following sections provide detailed examples of these mechanisms. 1.2.4.1 Register Renaming The ST6x86 CPU contains 32 physical general purpose registers. Each of the 32 registers in the register file can be temporarily assigned as one of the general purpose registers defined by the x86 architecture (EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP). For each register write operation a new physical register is selected to allow previous data to be retained temporarily. Register renaming effectively removes all WAW and WAR dependen- cies. The programmer does not have to consider register renaming; it is completely transparent to both the operating system and application soft- ware.ST6x86 Example #1 - Register Renaming Eliminates Write-After-Read (WAR) Dependency A WAR dependency exists when the first in a pair of instructions reads a logical register, and the second instruction writes to the same logical register. This type of dependency is illustrated by the pair of instruc- tions shown below: X PIPE Y PIPE (1) MOV BX, AX (2) ADD AX, CX BX < AX AX < AX+CX Note: In this and the following examples the original instruction order is shown in parentheses. In the absence of register renaming, the ADD instruction in the Y pipe would have to be stalled to allow the MOV instruction in the X pipe to read the AX register. The ST6x86 CPU, however, avoids the Y pipe stall (Table 1.1). As each instruction executes, the results are placed in new physical registers to avoid the possibility of overwriting a logical register value and to allow the two instructions to complete in parallel (or out of order) rather than in sequence. Table 1.1. Register Renaming with WAR Dependency Physical Register Contents Action Instruction RegO Reg1 Reg2 Reg3 Reg4 Pipe (Initial) AX BX CX MOV BX, AX AX CX BX X Reg3 < RegOd ADD AX, CX CX BX AX Y Reg4 < RegO + Reg2 Note: The representation of the MOV and ADD instructions in the final column of Table 1.1 are completely independent. 663 K77_ SGS-THOMSON + LICROELESTRONIESST6x86 Example #2 - Register Renaming Eliminates Write-After-Write (WAW) Dependency A WAW dependency occurs when two consecutive instructions perform writes to the same logical regis- ter. This type of dependency is illustrated by the pair of instructions shown below: X PIPE Y PIPE (1) ADD AX, BX (2) MOV AX, [mem] AX <AX + BX AX < [mem] Without register renaming, the MOV instruction in the Y pipe would have to be stalled to guarantee that the ADD instruction in the X pipe would write its results to the AX register first. The ST6x86 CPU uses register renaming and avoids the Y pipe stall. The contents of the AX and BX reg- isters are placed in physical registers (Table 1 2). As each instruction executes, the results are placed in new physical registers to avoid the possibility of overwriting a logical register value and to allow the two instructions to complete in parallel (or out of order) rather than in sequence. Table 1.2. Register Renaming with WAW Dependency Physical Register Contents Action Instruction RegO Reg1 Reg2 Reg3 Pipe (Initial) AX BX ADD AX, BX BX AX X Reg2 Regd + Regi MOV AX, [mem] BX AX Y Reg3 < [mem] Note: All subsequent reads of the logical register AX will refer to Reg 3, the result of the MOV instruction. 7/53 as SGS-THOMSON + LICROELESTRONIESST6x86 1.2.4.2 Data Forwarding Register renaming alone cannot remove RAW dependencies. The ST6x86 CPU uses two types of data forwarding in conjunction with register renaming to eliminate RAW dependencies: - Operand Forwarding - Result Forwarding Operand forwarding takes place when the firstin a pair of instructions performs a move from register or memory, and the data that is read by the first instruction is required by the second instruction. The ST6x86 CPU performs the read operation and makes the data read available to both instructions simultaneously. Result forwarding takes place when the first in a pair of instructions performs an operation (such as an ADD) and the result is required by the second instruction to perform a move to a register or mem- ory. The ST6x86 CPU performs the required oper- ation and stores the results of the operation to the destination of both instructions simultaneously. SGS-THOMSON 8/53 IST) WIGS@ELECTEOMCSST6x86 Example #3 - Operand Forwarding Eliminates Read-After-Write (RAW) Dependency A RAW dependency occurs when the first in a pair of instructions performs a write, and the second instruction reads the same register. This type of dependency is illustrated by the pair of instructions shown below in the X and Y pipelines: X PIPE Y PIPE (1) MOV AX, [mem] (2) ADD BX, AX AX [mem] BX AX + BX The ST6x86 CPU uses operand forwarding and avoids a Y pipe stall (Table 1.3). Operand forwarding allows simultaneous execution of both instructions by first reading memory and then making the results available to both pipelines in parallel. Table 1.3. Example of Operand Forwarding Physical Register Contents Action Instruction RegO Reg1 Reg2 Reg3 Pipe (Initial) AX BX MOV AX, [mem] BX AX x Reg2 + [mem] ADD BX, AX AX BX Y Reg3 < [mem] + Reg1 Operand forwarding can only occur if the first instruction does not modify its source data. In other words, the instruction is a move type instruction (for example, MOV, POP, LEA). Operand forwarding occurs for both register and memory operands. The size of the first instruction destination and the second instruc- tion source must match. 9/53 as SGS-THOMSON + LICROELESTRONIESST6x86 Example #4 - Result Forwarding Eliminates Read-After-Write (RAW) Dependency In this example, a RAW dependency occurs when the first in a pair of instructions performs a write, and the second instruction reads the same register. This dependency is illustrated by the pair of instructions in the X and Y pipelines, as shown below: X PIPE Y PIPE (1) ADD AX, BX (2) MOV [mem], AX AX AX + BX [mem] AX The ST6x86 CPU uses result forwarding and avoids a Y pipe stall (Table 1.4). Instead of transferring the contents of the AX register to memory, the result of the previous ADD instruction (RegO + Reg1) is written directly to memory, thereby saving a clock cycle. Table 1.4. Result Forwarding Example Physical Register Contents Action Instruction RegO Reg1 Reg2 Pipe (Initial) AX BX ADD AX, BX BX AX X Rege <Reg0 + Regi MOV [mem], AX BX AX Y [mem] < RegO +Regi The second instruction must be a move instruction and the destination of the second instruction may be either a register or memory. 10/63 K77_ SGS-THOMSON + LICROELESTRONIESST6x86 1.2.4.3 Data Bypassing In addition to register renaming and data forwarding, the ST6x86 CPU implements a third data depen- dency-resolution technique called data bypassing. Data bypassing reduces the performance penalty of those memory data RAW dependencies that cannot be eliminated by data forwarding. Data bypassing is implemented when the first in a pair of instructions writes to memory and the second instruction reads the same data from memory. The ST6x86 CPU retains the data from the first instruction and passes it to the second instruction, thereby eliminating a memory read cycle. Data bypassing only occurs for cacheable memory locations. Example #1- Data Bypassing with Read-After-Write (RAW) Dependency In this example, a RAW dependency occurs when the first in a pair of instructions performs a write to memory and the second instruction reads the same memory location. This dependency is illustrated by the pair of instructions in the X and Y pipelines as shown below: X PIPE Y PIPE (1) ADD [mem], AX (2) SUB BX, [mem] [mem] [mem] + AX BX * BX - [mem] The ST6x86 CPU uses data bypassing and stalls the Y pipe for only one clock by eliminating the Y pipes memory read cycle (Table 1.5). Instead of reading memory in the Y pipe, the result of the previous instruction ([mem] + Reg0) is used to subtract from Reg1, thereby saving a memory access cycle. Table 1.5. Example of Data Bypassing Physical Register Action Contents Instruction RegO Reg1 Reg2 Pipe (Initial) AX BX ADD [mem], AX AX BX X [mem] < [mem] + Regd SUB BX, [mem] AX BX Y Reg2 < Regi - {[mem] + Reg0} 11/53 as SGS-THOMSON + LICROELESTRONIESST6x86 1.2.5 Branch Control Branch instructions occur on average every four to six instructions in x86-compatible programs. When the normal sequential flow of a program changes due to a branch instruction, the pipeline stages may stall while waiting for the CPU to calculate, retrieve, and decode the new instruction stream. The ST6x86 CPU minimizes the performance deg- radation and latency of branch instructions through the use of branch prediction and speculative exe- cution. 1.2.5.1. Branch Prediction The ST6x86 CPU uses a 256-entry, 4-way set associative Branch Target Buffer (BTB) to store branch target addresses and branch prediction information. During the fetch stage, the instruction stream is checked for the presence of branch instructions. If an unconditional branch instruction is encountered, the ST6x86 CPU accesses the BTB to check for the branch instructions target address. If the branch instructions target address is found in the BTB, the ST6x86 CPU begins fetch- ing at the target address specified by the BTB. In case of conditional branches, the BTB also pro- vides history information to indicate whether the branch is more likely to be taken or not taken. If the conditional branch instruction is found in the BTB, the ST6x86 CPU begins fetching instructions at the predicted target address. If the conditional branch misses in the BTB, the ST6x86 CPU pre- dicts that the branch will not be taken, and instruc- tion fetching continues with the next sequential instruction. The decision to fetch the taken or not taken target address is based on a four-state branch prediction algorithm. k SGS-THOMSON TF UR aeLECT EMS Once fetched, a conditional branch instruction is first decoded and then dispatched to the X pipeline only. The conditional branch instruction proceeds through the X pipeline and is then resolved in either the EX stage or the WB stage. The condi- tional branch is resolved in the EX stage, if the instruction responsible for setting the condition codes is completed prior to the execution of the branch. If the instruction that sets the condition codes is executed in parallel with the branch, the conditional branch instruction is resolved in the WB stage. Correctly predicted branch instructions execute in a single core clock. If resolution of a branch indi- cates that a misprediction has occurred, the ST6x86 CPU flushes the pipeline and starts fetch- ing from the correct target address. The ST6x86 CPU prefetches both the predicted and the non-predicted path for each conditional branch, thereby eliminating the cache access cycle on a misprediction. If the branch is resolved in the EX stage, the resulting misprediction latency is four cycles. If the branch is resolved in the WB stage, the latency is five cycles. Since the target address of return (RET) instruc- tions is dynamic rather than static, the ST6x86 CPU caches target addresses for RET instructions in an eight-entry return stack rather than in the BTB. The return address is pushed on the return stack during a CALL instruction and popped during the corresponding RET instruction. 12/53ST6x86 1.2.5.2 Speculative Execution The ST6x86 CPU is capable of speculative execu- tion following a floating point instruction or pre- dicted branch. Speculative execution allows the pipelines to continuously execute instructions fol- lowing a branch without stalling the pipelines wait- ing for branch resolution. The same mechanism is used to execute floating point instructions (see Section 1.5) in parallel with integer instructions. The ST6x86 CPU is capable of up to four levels of speculation (i.e., combinations of four conditional branches and floating point operations). After generating the fetch address using branch predic- tion, the CPU checkpoints the machine state (reg- isters, flags, and processor environment), increments the speculation level counter, and begins operating on the predicted instruction stream. Once the branch instruction is resolved, the CPU decreases the speculation level. For a correctly predicted branch, the status of the checkpointed resources is cleared. For a branch misprediction, the ST6x86 processor generates the correct fetch address and uses the checkpointed values to restore the machine state in a single clock. In order to maintain compatibility, writes that result from speculatively executed instructions are not permitted to update the cache or external memory until the appropriate branch is resolved. Specula- tive execution continues until one of the following conditions occurs: 13/53 k SGS-THOMSON TF UR aeLECT EMS 1) A branch or floating point operation is decoded and the speculation level is already at four. 2) An exception or a fault occurs. 3) The write buffers are full. 4) An attempt is made to modify a non-check- pointed resource (i.e., segment registers, system flags). 1.3 Cache Units The ST6x86 CPU employs two caches, the Unified Cache and the Instruction Line Cache (Figure 1.2). 1.3.1 Unified Cache The 16-KByte unified write-back cache functions as the primary data cache and as the secondary instruction cache. Configured as a_ four-way set-associative cache, the cache stores up to 16 KBytes of code and data in 512 lines. The cache is dual-ported and allows any two of the fol- lowing operations to occur in parallel: - Code fetch - Data read (X pipe, Y pipeline or FPU) - Data write (X pipe, Y pipeline or FPU) The unified cache uses a pseudo-LRU replace- ment algorithm and can be configured to allocate new lines on read misses only or on read and write misses.ST6x86 1.3.2 The fully associative 256-byte instruction line cache serves as the primary instruction cache. The instruction line cache is filled from the unified cache through the data bus. Fetches from the inte- ger unit that hit in the instruction line cache do not access the unified cache. If an instruction line cache miss occurs, the instruction line data from the unified cache is transferred to the instruction line cache and the integer unit, simultaneously. Figure 1.2. Cache Unit Operations Instruction Line Cache The instruction line cache uses a pseudo-LRU replacement algorithm. To ensure proper opera- tion in the case of self-modifying code, any writes to the unified cache are checked against the con- tents of the instruction line cache. Ifa hit occurs in the instruction line cache, the appropriate line is invalidated. Instruction Data d Integer Instructian Unit [4 ree8 _ Data Instruction Line Cache Bypass xX Y - 256-Byle Fully Agsociative, & Linea Aligner Fipe|Pipa| <= FPU Data Bus. y i Bus Interface Unit Unifie Cache 16-KByta, 4-Way Sot Associative, 128 LinesSet x Instruction Sat 0 Linear Line Cache Set 1 Adfiress Miss Afidrass Set? Sat 3 Memory Management Unit > (TLE) =< = Dual Bus tre9083 = Single Bus as SGS-THOMSON + LICROELESTRONIES 14/53ST6x86 1.4 Memory Management Unit The Memory Management Unit (MMU), shown in Figure 1.3, translates the linear address supplied by the IU into a physical address to be used by the unified cache and the bus interface. Memory man- agement procedures are x86 compatible, adhering to standard paging mechanisms. The ST6x86 MMU includes two paging mecha- nisms (Figure 1.3), a traditional paging mecha- nism, and a ST6x86 variable-size paging mechanism. 1.4.1 Variable-Size Paging Mechanism The SGS-THOMSON variable-size paging mecha- nism allows software to map pages between 4 KBytes and 4 GBytes in size. The large contigu- ous memories provided by this mechanism help avoid TLB (Translation Lookaside Buffer) thrashing associated with some operating systems and applications. For example, use of a single large page instead of a series of small 4-KByte pages can greatly improve performance in an application using a large video memory buffer. Figure 1.3. Paging Mechanism within the Memory Management Unit Control Linear Address Directory Table GR3 Control Register Paging Mechanism Main TLB Page Table Physical Page Page Frame Traditional Paging Mechanism 1728901 15/53 k SGS-THOMSON TF UR aeLECT EMSST6x86 1.4.2 Traditional Paging Mechanism The traditional paging mechanism has been enhanced on the ST6x86 CPU with the addition of the Directory Table Entry (DTE) cache and the Vic- tim TLB. The main TLB (Translation Lookaside Buffer) is a direct-mapped 128-entry cache for page table entries. The four-entry fully associative DTE cache stores the most recent DTE accesses. If a Page Table Entry (PTE) miss occurs followed by a DTE hit, only a single memory access to the PTE table is required. The Victim TLB stores PTEs which have been dis- placed from the main TLB due to a TLB miss. Ifa PTE access occurs while the PTE is stored in the victim TLB, the PTE inthe victim TLB is swapped with a PTE in the main TLB. This has the effect of selectively increasing TLB associativity. The ST6x86 CPU updates the eight-entry fully associa- tive victim TLB on an oldest entry replacement basis. 1.5 Floating Point Unit The ST6x86 Floating Point Unit (FPU) interfaces to the integer unit and the cache unit through a 64-bit bus. The ST6x86 FPU is x87 instruction set com- patible and adheres to the IEEE-754 standard. Since most applications contain FPU instructions mixed with integer instructions, the ST6x86 FPU achieves high performance by completing integer and FPU operations in parallel. k SGS-THOMSON TF UR aeLECT EMS FPU Parallel Execution The ST6x86 CPU executes integer instructions in parallel with FPU instructions. Integer instructions may complete out of order with respect to the FPU instructions. The ST6x86 CPU maintains x86 com- patibility by signaling exceptions and issuing write cycles in program order. As previously discussed, FPU instructions are always dispatched to the integer unit's X pipeline. The address calculation stage of the X pipeline checks for memory management exceptions and accesses memory operands used by the FPU. If no exceptions are detected, the ST6x86 CPU checkpoints the state of the CPU and, during AC2, dispatches the floating point instruction to the FPU instruction queue. The ST6x86 CPU can then complete any subsequent integer instructions speculatively and out of order relative to the FPU instruction and relative to any potential FPU exceptions which may occur. As additional FPU instructions enter the pipeline, the ST6x86 CPU dispatches up to four FPU instructions to the FPU instruction queue. The ST6x86 CPU continues executing speculatively and out of order, relative to the FPU queue, until the ST6x86 CPU encounters one of the conditions that causes speculative execution to halt. As the FPU completes instructions, the speculation level decreases and the checkpointed resources are available for reuse in subsequent operations. The ST6x86 FPU also uses a set of four write buffers to prevent stalls due to speculative writes. 1.6 Bus Interface Unit The Bus Interface Unit (BIU) provides the signals and timing required by external circuitry. The sig- nal descriptions and bus interface timing informa- tion is provided in Chapters 3 and 4 of this manual. 16/532.0 Programming Interface In this chapter, the internal operations of the ST6x86 CPU are described mainly from an appli- cation programmer's point of view. Included in this chapter are descriptions of processor initialization, the register set, memory addressing, various types of interrupts and the shutdown and halt process. as SGS-THOMSON + LICROELESTRONIES ST6x86 An overview of real, virtual 8086, and protected operating modes is also included in this chapter. The FPU operations are described separately at the end of the chapter. This manual does not - and is not intended to - describe the ST6X86 microprocessor or its operations at the circuit level. 17/53ST6x86 Table 2.1. Initialized Register Controls REGISTER REGISTER NAME INITIALIZED CONTENTS COMMENTS EAX Accumulator XXXX XXxXxh 0000 0000h indicates self-test passed. EBX Base XXXX XXxXxh ECX Count XXXX XXxXxh . Device ID = 31h or 33h (2X clock) EDX Data 05 + Device ID Device ID = 35h or 37h (3X clock) EBP Base Pointer XXXX XXxXxh ESI Source Index XXXX XXxXxh EDI Destination Index XXXX XXxXxh ESP Stack Pointer XXXX XXxXxh EFLAGS Flag Word 0000 0002h EIP Instruction Pointer 0000 FFFOh Base address set to 0000 0000h. ES Extra Segment 0000h Limit set to FFEFh. Base address set to FFFF 0000h. CS Code Segment FOoOoh Limit set to FFEFh. Base address set to 0000 0000h. SS Stack Segment 0000h Limit set to FFEFh. Base address set to 0000 0000h. DS Data Segment 0000h Limit set to FFEFh. Base address set to 0000 0000h. FS Extra Segment 0000h Limit set to FFEFh. Base address set to 0000 0000h. GS Extra Segment 0000h Limit set to FFEFh. IDTR teres Descriptor Table Regis- Base = 0, Limit = 3FFh GDTR Global Descriptor Table 10000 3000th, 2000h Register LDTR Local Descriptor Table 10000 3000th, 2000h Register TR Task Register Xxxxh CRO Machine Status Word 6000 0010h CR2 Control Register 2 XXXX XXxXxh CR3 Control Register 3 XXXX XXxXxh CCR (0-5) | Configuration Control (0-5) 00h ARR (0-7) Address Region Registers (0-7) | 00h RCR (0-7) Region Control Registers (0-7) | 00h . ae 31h or 33h (2X clock) DIRO Device Identification 0 35h or 37h (3X clock) DIR1 Device Identification 1 Step ID + Revision ID DR7 Debug Register 7 0000 0400h Note: x = Undefined value 18/53 as SGS-THOMSON + LICROELESTRONIESST6x86 2.1 ST6x86 Configuration Registers A set of 24 on-chip ST6x86 configuration registers are used to enable features in the ST6x86 CPU. These registers assign non-cached memory areas, set up SMM, provide CPU identification information and control various features such as cache write policy, and bus locking control. There are four groups of registers within the ST6x86 con- figuration register set: - 6 Configuration Control Registers (CCRx) - 8 Address Region Registers (ARRx) - 8 Region Control Registers (RCRx) - 2 Device Identification Registers (DIRx) Access to the configuration registers is achieved by writing the register index number for the config- uration register to I/O port 22h. I/O port 23h Is then used for data transfer. Each |/O port 23h data transfer must be preceded by a valid I/O port 22h register index selection. Otherwise, the current 22h, and the second and later I/O port 23h operations communicate through the I/O port to produce external I/O cycles. All reads from I/O port 22h produce external I/O cycles. Accesses that hit within the on-chip config- uration registers do not generate external I/O cycles. k SGS-THOMSON TF UR aeLECT EMS After reset, configuration registers with indexes CO-CFh and FE-FFh are accessible. To prevent potential conflicts with other devices which may use ports 22 and 23h to access their registers, the remaining registers (indexes DO-FDh) are accessi- ble only if the MAPEN(3-0) bits in CCR3 are set to 1h. See Figure 2.4 (Page 24) for more information on the MAPEN(3-0) bit locations. lf MAPEN[3-0] = 1h, any access to indexes in the range OO-FFh will not create external I/O bus cycles. Registers with indexes CO-CFh, FE, FFh are accessible regardless of the state of MAPENJ[3-0]. If the register index number is out- side the CO-CFh or FE-FFh ranges, and MAPEN|3-0] are set to Oh, external I/O bus cycles occur. Table 2.2 (Page 20) lists the MAPEN[3-0] values required to access each ST6x86_ configu- ration register. All bits in the configuration regis- ters are initialized to zero following reset unless specified otherwise. Valid register index numbers include COh to E3h, E8h, E9h, FEh and FFh (if MAPEN[8-0] = 1). 2.1.1 Configuration Control Registers (CCRO - CCR5) control several functions, includ- ing non-cacheable memory, write-back regions, and SMM features. A list of the configuration reg- isters is listed in Table 2.2 (Page 20). The configu- ration registers are described in greater detail in the following pages. 19/53ST6x86 Table 2.2. ST6x86 CPU Configuration Registers REGISTER NAME acronym | REGISTER | WIDTH | "NEEDED FOR ACCESS Configuration Control 0 CCRO Coh 8 x Configuration Control 1 CCRI1 Cih 8 x Configuration Control 2 CCR2 C2h 8 x Configuration Control 3 CCR3 C3h 8 x Configuration Control 4 CCR4 E8h 8 1 Configuration Control 5 CCR5 E9h 8 1 Address Region 0 ARRO C4h -C6h 24 x Address Region 1 ARRI1 C7h-C9h 24 x Address Region 2 ARR2 CAh-CCh 24 x Address Region 3 ARR3 CDh - CFh 24 x Address Region 4 ARR4 DOh - D2h 24 1 Address Region 5 ARRS5 D3h - D5h 24 1 Address Region 6 ARR6 D6h - D8h 24 1 Address Region 7 ARR7 D9h - DBh 24 1 Region Control 0 RCRO DCh 8 1 Region Control 1 RCR1 DDh 8 1 Region Control 2 RCR2 DEh 8 1 Region Control 3 RCR3 DFh 8 1 Region Control 4 RCR4 Eoh 8 1 Region Control 5 RCR5S Eth 8 1 Region Control 6 RCR6 E2h 8 1 Region Control 7 RCR7 E8h 8 1 Device Identification 0 DIRO FEh 8 X Device Identification 1 DIR1 FFh 8 X Note: x = Don't Care 20/53 4&7 S&S:THOMsoN + 2 JORGELEST. ey MICSST6x86 Figure 2.1. ST6x86 Configuration Control Register 0 (CCRO) 7 6 5 4 3 2 1 0 Table 2.3. CCRO Bit Definitions BIT POSITION NAME DESCRIPTION No Cache 640 KByte- 1 MByte 1 NC1 If = 1: Address region 640 KByte to 1 MByteis non-cacheable. If = 0: Address region 640 KByte to 1 MByte is cacheable. Note: Bits 0, 2 through 7 are reserved. 21/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure 2.2. ST6x86 Configuration Control Register 1 (CCR1) USE_SMI Table 2.4. CCR1 Bit Definitions BIT POSITION NAME DESCRIPTION Enable SMM and SMIACT# Pins 1 USE_SMI | If=1:SMI# and SMIACT# pins are enabled. If = 0: SMI# pin ignored and SMIACT# pin is driven inactive. System Management Memory Access If = 1: Any access to addresses within the SMM address space, access system manage- 2 SMAC ment memory instead of main memory. SMI# input is ignored. Used when initializing or testing SMM memory. If = 0: No effect on access. Negate LOCK# If = 1: All bus cycles are issued with LOCK# pin negated except page table accesses and interrupt acknowledge cycles. Interrupt acknowledge cycles are executed as locked 4 NO_LOCK | cycles even though LOCK# is negated. With NO_LOCK set, previously noncacheable locked cycles are executed as unlocked cycles and therefore, may be cached. This results in higher performance. Refer to Region Control Registers for information on elimi- nating locked CPU bus cycles only in specific address regions. 7 SM3 SMM Address Space Address Region 3 If = 1: Address Region 3 is designated as SMM address space. Note: Bits 0, 3, 5 and 6 are reserved. 22/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure 2.3. ST6x86 Configuration Control Register 2 (CCR2) 7 6 5 4 3 2 1 0 USE_SUSP WPRI1 SUSP_HLT LOCK_NW Table 2.5. CCR2 Bit Definitions BIT NAME DESCRIPTION POSITION Lock NW 2 LOCK _NW Nw hit bit in CRO becomes read only and the CPU ignores any writes to the If = 0: NW bit in CRO can be modified. Suspend on Halt 3 SUSP_HLT If = 1: Execution of the HLT instruction causes the CPU to enter low power sus- pend mode. Write-Protect Region 1 4 WPR1 lf = 1: Designates any cacheable accesses in 640 KByte to 1 MByte address region are write protected. Use Suspend Mode (Enable Suspend Pins) 7 USE_SUSP lf = 1: SUSP# and SUSPA# pins are enabled. If = 0: SUSP# pin is ignored and SUSPA# pin floats. Note: Bits 0,1, 5 and 6 are reserved. 23/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure 2.4. ST6x86 Configuration Control Register 3 (CCR3) 7 6 5 4 3 2 1 0 MAPEN Reserved LINBRST NMI_EN SMILOCK Table 2.6. CCR3 Bit Definitions BIT POSITION NAME DESCRIPTION 0 SMI_LOCK SMI Lock If = 1: The following SMM configuration bits can only be modified while in an SMI service routine: CCR1: USE_SMI, SMAC, SM3 CCR3: NMI_EN ARR32: Starting address and block size. Once set, the features locked by SMI_LOCK cannot be unlocked until the RESET pin is asserted. 1 NMI_EN NMI Enable If = 1: NMI interrupt is recognized while servicing an SMI interrupt. NMI_EN should be set only while in SMM, after the appropriate SMI interrupt ser- vice routine has been setup. 2 LINBRST lf = 1: Use linear address sequence during burst cycles. If = 0: Use 1 + 4 address sequence during burst cycles. The 1 + 4 address sequence is compatible with Pentiums burst address sequence. 4-7 MAPEN MAP Enable If = 1h: All configuration registers are accessible. If = Oh: Only configuration registers with indexes CO-CFh, FEh and FFh are accessible. Note: Bit 3 is reserved. 24/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure 2.5. ST6x86 Configuration Control Register 4 (CCR4) IORT Table 2.7. CCR4 Bit Definitions BIT POSITION NAME DESCRIPTION /O Recovery Time Specifies the minimum number of bus clocks between |/O accesses: Oh = 1 clock delay th = 2 clock delay 2h = 4 clock delay 0-2 lORT 3h = 8 clock delay 4h = 16 clock delay 5h = 32 clock delay (default value after RESET) 6h = 64 clock delay 7h = no delay Enable Directory Table Entry Cache 4 DTE_EN If = 1: the Directory Table Entry cache is enabled. Enable CPUID instruction. lf = 1: the ID bit in the EFLAGS register can be modified and execution of the 7 CPUID CPUID instruction occurs as documented in section 6.3. If = 0: the ID bit in the EFLAGS register can not be modified and execution of the CPUID instruction causes an invalid opcode exception. Note: Bits 3 and bits 5 and 6 are reserved. 25/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure 2.6. ST6x86 Configuration Control Register 5 (CCR5) 7 WT_ALLOC Table 2.8. CCR5 Bit Definitions BIT POSITION NAME DESCRIPTION Write-Through Allocate 0 WT_ALLOC If = 1: New cache lines are allocated for read and write misses. If = 0: New cache lines are allocated only for read misses. Local Bus Region 1 4 LBR1 If = 1: LBA# pin is asserted for all accesses to the 640 KByte to 1 MByte address region. Enable ARR Registers 5 ARREN If = 1: Enables all ARR registers. If = 0: Disables the ARR registers. If SM3 is set, ARR3 is enabled regardless of the setting of ARREN. Note: Bits 1 through 3 and 6 though 7 are reserved. 26/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 2.1.2 Address Region Registers The Address Region Registers (ARRO - ARR7) (Figure 2.7) are used to specify the location and size for the eight address regions. Attributes for each address region are specified in the Region Control Registers (RCRO-RCR7). ARR7 and RCR7 are used to define system main memory and differ from ARRO-6 and RCRO-6. With non-cacheable regions defined on-chip, the ST6x86 CPU delivers optimum performance by using advanced techniques to eliminate data dependencies and resource conflicts in its execu- tion pipelines. If KEN# is active for accesses to regions defined as non-cacheable by the RCRs, the region is not cached. The RCRs take prece- dence in this case. A register index, shown in Table 2.9 (Page 28) is used to select one of three bytes in each ARR. The starting address of the ARR address region, selected by the START ADDRESS field, must be on a block size boundary. For example, a 128 KByte block is allowed to have a starting address of 0 KBytes, 128 KBytes, 256 KBytes, and so on. The SIZE field bit definition is listed in Table 2.10, on page 28. If the SIZE fieldis zero, the address region Is of zero size and thus disabled. Figure 2.7. Address Region Registers (ARRO - ARR7) START ADDRESS SIZE Memary Address Memory Address Memory Address Size Bits Bits A31-A24 Bits A23-A16 Bits A15-A12 30 7 0 7 0 7 4 3 0 27/53 k SGS-THOMSON TF UR aeLECT EMSST6x86 Table 2.9. ARRO- ARR7 Register Index Assignment Lyf TICRGSLEST: ARR Memory Address Memory Address Memory Address Address Region Register (A31 - A24) (A23 - A16) (A15 - A12) Size (3 - 0) ARRO C4h C&Sh Ch Ch ARR1 C7h C8h C9h C9h ARR2 CAh CBh CCh CCh ARR3 CDh CEh CFh CFh ARR4 DOh Dih D2h D2h ARRS5 D3h D4h D5h D5h ARR6 D6h D7h D8h D8h ARR7 D9h DAh DBh DBh Table 2.10. Bit Definitions for SIZE Field BLOCK SIZE BLOCK SIZE SIZE (3-0) SIZE (3-0) ARRO-6 ARR7 ARRO-6 ARR7 Oh Disabled Disabled 8h 512 KBytes 32 MBytes th 4 KBytes 256 KBytes 9h 1 MBytes 64 MBytes 2h 8 KBytes 512 KBytes Ah 2 MBytes 128 MBytes 3h 16 KBytes 1 MBytes Bh 4 MBytes 256 MBytes 4h 32 KBytes 2 MBytes Ch 8 MBytes 512 MBytes 5h 64 KBytes 4 MBytes Dh 16 MBytes 1 GBytes 6h 128 KBytes 8 MBytes Eh 32 MBytes 2 GBytes 7h 256 KBytes 16 MBytes Fh 4 GBytes 4 GBytes 28/53 SGS-THOMSON ey MICS2.1.3. Region Control Registers The Region Control Registers (RCRO - RCR7) specify the attributes associated with the ARRx address regions. The bit definitions for the region control registers are shown in Figure 2.8 (Page 30) and in Table 2.11 (Page 30). Cacheability, weak write ordering, weak locking, write gathering, cache write through policies and control of the LBA# pin can be activated or deactivated using the attribute bits. If an address is accessed that is not in a memory region defined by the ARRx registers, the following conditions will apply: - LBA# pin is asserted - If the memory address is cached, write-back is enabled it WB/WT# is returned high. - Writes are not gathered - Strong locking takes place - Strong write ordering takes place - The memory access is cached, if KEN# is returned asserted. k SGS-THOMSON TF UR aeLECT EMS ST6x86 Overlapping Conditions Defined. If two regions specified by ARRx registers overlap and conflict- ing attributes are specified, the following attributes take precedence: - LBA# pin is asserted - Write-back is disabled - Writes are not gathered - Strong locking takes place - Strong write ordering takes place - The overlapping regions are non-cacheable. 29/53ST6x86 Figure 2.8. Region Control Registers (RCRO-RCR7) 3 2 1 0 7 6 5 4 : NLB WT WG WL Wwo RCD / RCE* *Note: RCD is defined for RCRO-RCR6. RCE is defined for RCR7. Table 2.11. RCRO-RCR7 Bit Definitions RCRx POSITION NAME DESCRIPTION 0-6 0 RCD If = 1: Disables caching for address region specified by ARRx. 7 0 RCE If = 1: Enables caching for address region ARR7. 0-7 1 WWO If = 1: Weak write ordering for address region specified by ARRx. 0-7 2 WL If = 1: Weak locking for address region specified by ARRx. 0-7 3 WG If = 1: Write gathering for address region specified by ARRx. 0-7 4 WT If = 1: Address region specified by ARRx is write-through. 0-7 5 NLB If = 1:LBA# pin is not asserted for access to address region specified by ARRx Note: Bits 6 and 7 are reserved. Region Cache Disable (RCD). Setting RCD toa one defines the address region as non-cacheable. Whenever possible, the RCRs should be used to define non-cacheable regions rather than using external address decoding and driving the KEN# pin. Region Cache Enable (RCE). Setting RCE toa one defines the address region as cacheable. RCE is used to define the system main memory as cacheable memory. It is implied that memory out- side the region is non-cacheable. Weak Write Ordering (WWO). Setting WWO=1 enables weak write ordering for that address region. Enabling WWO allows the ST6x86 CPU to issue writes in its internal cache in an order differ- ent than their order in the code stream. External writes always occur in order (strong ordering). Therefore, this should only be enabled for memory regions that are NOT sensitive to this condition. WWO should not be enabled for memory mapped I/O. WWO only applies to memory regions that have been cached and designated as write-back. It also applies to previously cached addresses even if the cache has been disabled (CD=1). Enabling WWO removes the write-ordering restric- tion and improves performance due to reduced pipeline stalls. Weak Locking (WL). Setting WL=1 enables weak locking for that address region. With WWO enabled, all bus cycles are issued with the LOCK# pin negated except for page table accesses and interrupt acknowledge cycles. Interrupt acknowl- 30/53 k SGS-THOMSON TF UR aeLECT EMS edge cycles are executed as locked cycles even though LOCK# is negated. With WL=1, previously non-cacheable locked cycles are executed as unlocked cycles and therefore, may be cached, resulting in higher performance. The NO_LOCK bit of CCR1 enables weak locking for the entire address space. The WL bit allows weak locking only for specific address regions. WL is indepen- dent of the cacheability of the address region. Write Gathering (WG). Setting WG=1 enables write gathering for the associated address region. Write gathering allows multiple byte, word, or dword sequential address writes to accumulate in the on-chip write buffer. (As instructions are exe- cuted, the results are placed in a series of output buffers. These buffers are gathered into the finial output buffer). When access is made to a non-sequential memory location or when the 8-byte buffer becomes full, the contents of the buffer are written on the exter- nal 64-bit data bus. Performance is enhanced by avoiding as many as seven memory write cycles. WG should not be used on memory regions that are sensitive to write cycle gathering. WG can be enabled for both cacheable and non-cacheable regions. Write Through (WT). Setting WT=1 defines the address region as_ write-through instead of write-back, assuming the region is cacheable. Regions where system ROM are loaded (shad- owed or not) should be defined as write through.ST6x86 LBA # Not Asserted (NLB). Setting NLB = 1 prevents the microprocessor from asserting the Local Bus Access (LBA#) output pin for accesses to that address region. The RCR regions may be used to define non-local bus address regions. The LBA# pin could then be asserted for all regions, except those defined by the RCRs. The LBA# signal may be used by the external hardware (e.g., chipsets) as an indi- cation that local bus accesses are occurring. 31/53 as SGS-THOMSON + LICROELESTRONIESST6x86 3.0 ELECTRICAL SPECIFICATIONS 3.1. Electrical Connections This section provides information on electrical con- nections, absolute maximum ratings, recom- mended operating conditions, DC characteristics, and AC characteristics. All voltage values in Elec- trical Specifications are measured with respect to Vsg unless otherwise noted. 3.1.1. Power and Ground Connections and Decoupling Testing and operating the ST6x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. The high clock frequen- cies used in the ST6x86 CPU and its output buffer circuits can cause transient power surges when several output buffers switch output levels simulta- neously. These effects can be minimized by filter- ing the DC power leads with low-inductance decoupling capacitors, using low impedance wir- ing, and by utilizing all of the Veg and GND pins. The ST6x86 CPU contains 296 pins with 53 pins connected to Vcc and 53 connected to Vsg (ground). 3.1.2 Pull-Up/Pull-Down Resistors Table 3.1 lists the input pins that are internally con- nected to pull-up and pull-down resistors. The pull-up resistors are connected to Vcc and the pull-down resistors are connected to Vss. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. Table 3.1. Pins Connected to Internal Pull-Up and Pull Down Resistors SIGNAL PIN NO. RESISTOR BRDYC# Y3 20-kQ pull-up CLKMUL Y33 20-kQ pull-down QDUMP# AL7 20-kQ pull-up SMl# AB34 SUSP# Y34 20-kQ pull-up (see text) TCK M34 TDI N35 TMS P34 TRST# Q33 20-kQ pull-up Reserved J33 Reserved W35 Reserved Y35 Reserved AN35 20-kQ pull-down k SGS-THOMSON TF UR aeLECT EMS 32/53ST6x86 3.1.3 Unused Input Pins All inputs not used by the system designer and not listed in Table 3.1 should be connected either to ground or to Vgc. Connect active-high inputs to ground through a 20 kQ (+ 10%) pull-down resistor and active-low inputs to Veg through a 20 kQ (+ 10%) pull-up resistor to prevent possible spurious operation. 3.1.4 NC and Reserved Pins Pins designated NC have no internal connec- tions. Pins designated RESV or RESERVED should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resis- tor, or an active signal could cause unexpected results and possible circuit malfunctions. Table 3.2. Absolute Maximum Ratings 3.2 Absolute Maximum Ratings The following table lists absolute maximum ratings for the ST6x86 CPU microprocessors. Stresses beyond those listed under Table 3.2 limits may cause permanent damage to the device. These are stress ratings only and do not imply that opera- tion under any conditions other than those listed under Recommended Operating Conditions ST6x86 is possible. Exposure to conditions beyond Table 3.2 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Pro- longed exposure to conditions at or near the abso- lute maximum ratings may also result in reduced useful life and reliability. PARAMETER MIN MAX UNITS NOTES Operating Case Temperature -65 110 C Power Applied Storage Temperature -65 150 C Supply Voltage, Voc -0.5 40 Vv Voltage On Any Pin -0.5 Voc +0.5 Vv Input Clamp Current, lix 10 mA Power Applied Output Clamp Current, lox 25 mA Power Applied 33/53 k SGS-THOMSON TF UR aeLECT EMSST6x86 3.3. Recommended Operating Conditions Table 3.3 presents the recommended operating conditions for the ST6x86 CPU device. Table 3.3. Recommended Operating Conditions PARAMETER MIN MAX UNITS NOTES Te Operating Case Temperature 0 70 C Power Applied Voc Supply Voltage 3.15 3.7 Vv Vin High-Level Input Voltage 2.0 5.5 Vv Vi_ Low-Level Input Voltage -0.3 0.8 Vv lo High-Level Output Current All outputs except A20-A3 and W/R# -1.0 mA VaeV A20-A3 and W/R# -2.0 OF NOH(MIN) lo, Low-Level Output Current All outputs except A20-A3 and W/R# 5.0 mA VaeV A20-A3 and W/R# 10.0 OF NOL(MAX} 34/53 G7 SGS-THOMSON JF. Vickos leer noMcsST6x86 3.4 DC Characteristics Table 3.4. DC Characteristics (at Recommended Operating Conditions) PARAMETER MIN TYP MAX UNITS NOTES Vo_ Output Low Voltage lot =5mA 0.4 V Voy Output High Voltage lou =-1mA 2.4 V 1; Input Leakage Current For all pins except those +15 HA 0<Vin< Voc listedin Table 4-1. liq Input Leakage Current _ For all pins with internal 200 LA oad pull-downs. a . li. Input Leakage Current -400 A ViL = 0.45 V For all pins with internal pull-ups. U. See Table 3-1. loc Active loc 80 MHz 39 47 100 MHz 45 5.4 110 MHz 48 58 A | Note 1,5 120 MHz 5A 6.1 133 MHz 55 6.6 locsm Suspend Mode Iceg 80MHz 43 1 100 MHz 48 80 mA Note 1, 3, 5 110 MHz 50 83 120 MHz 51 105 133 MHz 54 115 loess Standby loc 0 MHz (Suspended/CLK Stopped) 35 75 mA Note 4,5 Ciylnput Capacitance 15 pF f = 1 MHz, Note 2 Coy Output Capacitance 20 pF f=1 MHz, Note 2 Cig l/O Capacitance 25 pF f=1 MHz, Note 2 Ce_CLK Capacitance 15 pF f=1 MHz, Note 2 Notes: 1. 2. 3. 35/53 Frequency (MHz) ratings refer to the internal clock frequency. Not 100% tested. Allinputs at 0.4 or Voc - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded Allinputs at 0.4 or Voc - 0.4 (CMOS levels). All inputs held static and all outputs unloaded (static lony7 = 0 MA). Typical, measured at Voc = 3.3 V Lyf SGS-THOMSON TICRGSLEST: eyST6x86 3.5 AC Characteristics Table 3.6 through 3.11 (Pages 38 through 43) list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Fig- ure 3.1 (Page 37) and Figure 3.2 (Page 38). The ris- ing clock edge reference level Vaeg and other reference levels are shown in Table 3.5. Input or output signals must cross these levels during testing. k SGS-THOMSON TF UR aeLECT EMS Figure 3.1 shows outout delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. 36/53ST6x86 Figure3.1. Drive Level and Measurement Points for Switching Characteristics TX CLK: ss eFC ONT TAT TT TTT Veer MAX MIN ; Valid Valid OUTPUTS: Output n veer //) //; //; //; K Veer Output att INPUTS: . Tk Veer Input MA LEGEND: A- Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification 1703406 Table 3.5. Drive Level and Measurement Points for Switching Characteristics VOLTAGE SYMBOL (Volts) Vitb 0 Note: Refer to Figure 3-1. 37/53 as SGS-THOMSON + LICROELESTRONIESST6x86 Table 3.6. Clock Specifications Tease = 0C to 70C, See Figure 3.2 40-MHz 50-MHz 55-MHz 60-MHz 66-MHz SYMBOL PARAMETER BUS BUS BUS BUS BUS UNITS MIN | MAX| MIN | MAX| MIN | MAX| MIN | MAX; MIN | MAX CLK Frequency 40 50 55 60 66.6 | MHz T1 CLK Period 25 20 18 16.67 | 33.33} 15.0} 30.0 ns T2 CLK Period Stability + 250 +250 + 250 +250 +250) ps T3 CLK High Time 9 7 4.0 4.0 4.0 ns T4 CLK Low Time 9 7 4.0 4.0 4.0 ns TS CLK Fall Time 0.15 2 0.15 2 0.15; 15 | 015) 15 | 015) 15 ns T6 CLK Rise Time 0.15 2 0.15 2 0.15; 15 | 015) 15 | 015) 15 ns Figure 3.2. CLK Timing and Measurement Points Vin(MINy Veer = Z#>---- ViIL@MAX) GF - CLK 1740602 38/53 as SGS-THOMSON + LICROELESTRONIESST6x86 Table 3.7. Output Valid Delays C,=50 pF, Tease = 0C to 70C, See Figure 3.3 40-MHz 50-MHz 55-MHz 60-MHz 66-MHz SYMBOL PARAMETER BUS BUS BUS BUS BUS UNITS MIN | MAX| MIN | MAX! MIN | MAX] MIN | MAX} MIN | MAX A31-A3, BE7#-BEO# CACHE#, D/C#, T7 LBA#, LOCK#, PCD, 3 14 1 12 1 7 1 8 1 7 ns PWT, SCYC, SMIACT#, W/R# T7b | ADS#, M/lO# 14 { 12 { 75 1 7.5 1 6 ns T8 ADSC# 14 { 12 1 7 1 8 1 ns T9 AP 14 1 12 1 85 1 8.5 1 8.5 ns APCHK#, PCHK#, T10 FERR# 3 16 1 14 1 83 1 7 1 7 ns ti | D68-DO, DP7-DPO| 3 | 44) 43) 12] 13) 9 | 13!) 9 | 13 | 75] ns (Write) T12a | HIT# 3 14 { 12 { 8 1 8 1 8 ns T12b | HITM# 3 14 | 1441] 12 | 14 7 14 7 14 6 ns T13 BREQ, HLDA 3 14 { 12 { 8 1 8 1 8 ns T14 | SUSPA# 3 16 { 14 1 8 1 8 1 8 ns Figure 3.3. Output Valid Delay Timing Tx Tx Tx Tx CLK MIN MAX <> ) 17-114 4 OUTPUTS VALID n AA VALID n+1 1740000 39/53 Lyf SGS-THOMSON TICRGSLEST: ey MICSST6x86 Table 3.8. Output Float Delays C,=50 pF ease = 0C to 70C, See Figure 3.4 40-MHz 50-MHz 55-MHz 60-MHz 66-MHz SYMBOL PARAMETER BUS BUS BUS BUS BUS UNITS MIN | MAX) MIN | MAX| MIN | MAX] MIN | MAX} MIN | MAX A31-A3, ADS#, BE7#BE0#, BREQ, CACHE#, D/C#, T15 LBA#, LOCK#, 19 16 10 10 10 ns M/O#, PCD, PWT, SCYC, SMIACTH, W/R# T16 AP 19 16 10 10 10 ns D63-D0, TI7 DP7-DPO (Write) 19 16 10 10 10 ns Figure 3.4. Output Float Delay Timing TX TX TX TX CLK T15-717 |MIN; MAX | ourrurs we A\) 1741000 40/53 Lyf SGS-THOMSON HICRGELESTECHICSST6x86 Table 3.9. Input Setup Times Tease = 0 C to 70 C, See Figure 3.5 40-MHz 50-MHz 55-MHz 60-MHz 66-MHz SYMBOL | PARAMETER BUS MIN BUS MIN BUS MIN Busmin | Bus min | UNITS A20M#, FLUSH#, M18 | \GNNE#, SUSP# 5 5 5 5 5 ns AHOLD, BHOLD, T19 | BOFF#, DHOLD, 5 5 5 5 5 ns HOLD T20 BRDY# ns T21 BRDYC# ns A31-A3, AP, 722 | Be7# BEO# 5 5 5 5 5 ns D63-D0 (Read), T22a | AB op, (Read) 38 38 38 3 3 ns T23 =~'| EADS#, INV 5 5 5 5 5 ns INTR, NMI, T24 =| RESET, SMI#, 5 5 5 5 5 ns WM_RST EWBE#, KEN#, 725 | Nat WE/WT# 5 5 45 45 45 ns T26 | QDUMP# 5 5 5 5 5 ns Table 3.10. Input Hold Times Tease = 0 Cto 70 C, See Figure 3.5 40-MHz 50-MHz 55-MHz 60-MHz 66-MHz SYMBOL | PARAMETER BUS MIN BUS MIN | BUSMIN | BUSMmIN | Bus iN | UNITS A20M#, FLUSH#, 127 | IGNNE#, SUSP# 3 2 1 1 1 ns AHOLD, BHOLD, T23 |BOFF#, DHOLD, 3 2 1 1 1 ns HOLD T29 = | BRDY# 1 1 1 ns T30 | BRDYC# 1 1 1 ns A31-A3, AP, T31la BE7#-BEO# 3 2 1 1 1 ns T3tp | D88-D0, DP7-DPo 3 2 2 2 2 ns (Read) 732. -| EADS#, INV 3 2 1 1 1 ns INTR, NMI, T33 RESET, SMI#, 3 2 1 1 1 ns WM_RST EWBE#, KEN#, 734 | Nag, WBAVT# 3 2 1 1 1 ns T35. | QDUMP# 3 2 1 1 1 ns 41/53 SGS-THOMSON Lyf TICRGSLEST: ey MICSST6x86 Figure 3.5. Input Setup and Hold Timing CLK Tx Tx T18-T26 | T27-T35 ETUPR+- HOLD->| AUK A\\ Tx TX 1740600 42/53 as SGS-THOMSON + LICROELESTRONIESST6x86 Table 3.11. JTAG AC Specifications ALL BUS FREQUENCIES SYMBOL PARAMETER UNITS | FIGURE MIN MAX TCK Frequency (MHz) 20 ns T36 TCK Period 50 ns 346 T37 TCK High Time 25 ns 36 T38 TCK Low Time 25 ns 346 T39 TCK Rise Time 5 ns 346 T40 TCK Fall Time 5 ns 346 TH TDO Valid Delay 3 20 ns 3-7 T42 Non-test Outputs Valid Delay 3 20 ns 3-7 T43 TDO Float Delay 25 ns 3-7 T44 Non-test Outputs Float Delay 25 ns 3-7 T45 TRST# Pulse Width 40 ns 38 T46 TDI, TMS Setup Time 20 ns 3-7 T47 Non-test Inputs Setup Time 20 ns 3-7 T48 TDI, TMS Hold Time 13 ns 3-7 T49 Non-test Inputs Hold Time 13 ns 3-7 Figure 3.6. TCK Timing and Measurement Points TCK 1741102 43/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 Figure3.7. JTAG Test Timings 15V roe F=f \_f }_/ T46 T48 TDI I T41 T43 TDO ( XO KY T42 T44 OUTPUT TTT 7 SIGNALS k K T4? T4g INPUT rt *| SIGNALS | 1740400 Figure 3.8. Test Reset Timing T45 TRST# FN asy 1741200 44183 K77_ SGS-THOMSON + LICROELESTRONIESST6x86 4.0 MECHANICAL SPECIFICATIONS 4.1 296-Pin CPGA Package The pin assignments for the ST6x86 CPUin a 296-pin CPGA package are shown in Figure 4.1. The pins are listed by signal name in Table 4.1 (Page 46) and by pin number in Table 4.2 (Page 47). Dimensions are shown in Table 4.2 (Page 47) and Table 4.3 (Page 49). Figure 4.1. 296-Pin CPGA Package Pin Assignments as SGS-THOMSON HICRGELESTECHICS 37 36 35 34 33 32 31 30 29 2a 27 26 25 24 23 29 21 20 19 18.17 18 1514191211108 8 76 5 4 38 2 1 AN | \@ pBy SS veo veo vo Be eu Be ee m=. & @ | an au | GB Be We eS Se He vee wh vB i GS we eer Ser | am AL o Qo 9 o o o 3 0 o AL vis Aa oA? _ AlT _ Ai2_oaaiad: ig ATR ASD _sORESV_SCYC_ BEY BE4# BED! BEOe QDUMPHHITMA PIT NC AK 9 o 5S oO o 9 o 6 oO 9 9 9 AK ae Ado) OBCOAGCiATS) SANS Ss ATT?) SORESET Clk BETS BEBE OBESE BEt# ADOME HITE D/GH AP a | 2 o 9 a VSS AIS | ASI ADS# HLDA_ REQ AH [*) 9 AH 0 oo LOCKE VSS AG | voc. ama | ADT Pop smiActz vec | AG AF 2 8g AF VSS _ A? PCHK#_ VSS a] 2 Oo 9 oO. Oo | af vee NG _ Ags APCHKE NO _ vic AD o (2 9 AD VSS __ INTR NG _ VSS ac | 9. 9" "9 ooo | ac vie 6 NE Ni NO _RESV_ vic AB v8S __ SMH HOLD v8S AB A |S, Pear 2 AA VEC JGNNEAM RST w RESV_ Vcc z v8s NC BOFFA_ VSS z Bo Rev LKMUL NA OB 9 Be x o Bs oo BROW VES x Ww W v VEC | RESV SUSPA# ST 6x86 CPU KEN EWBEE, VOC y v58 _ SUSP# AHOLD_ VES u vec. Ve8 _ vec I cates vec u T vs _ veo TOP VIEW MIO#_ VES T s | 9 00 o oO! g VEC, DHOLD RESV LBAR RESV, VOC R Q R VSS BHOLD. RESV, VSS a|/ 2 oe eo |g voc. NC | TRST# FERRH, RESV, VOC P es & P n | ooo ao oo | , vec. TDI | Too DP? p83 | WoC M ves _ Tek Wes M .|o oo ooo | , cCc. NG Co Dao D61 voc K me res K 1/9 0 oo oOo] , yoo D2 RESV D568 DS? vec H ves | Ne nee ves H |/ ef & B&B Ss ms vec | & F a8 OP bet. Oe F e|@ 98 & 2 &| & D Om Se eet eek oes ees oO te cae ooo D clo me SY eee Se & De FD oa ms er me | CS B 5 o 5 o 6 o B Dii_ O13 Die 020 VSS _VSS_vss_VSS__VSS VSS _VSS__=VSS__~VES v8s 4a NG al|o @ 9 9 9 99 Qo 9 / A Ne ois) 6bia 6p vee: Cee Cee vic (vic (vee (ve Vio vc pat NG a7 26 35 34 33 32 31 30 29 28 27 26 25 24 23.22 21 2019 181718 1514131211108 6876 5 4 39 2 1 1740200 45/53ST6x86 Table 4.1. 296-Pin CPGA Package Signal Names Sorted by Pin Number Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal A3 NC C29 D21 J35 D2 U35 Vss AE35 NC AL21 A20 A5 D41 C31 D17 J37 Veco U37 Vec AE37 Vec AL23 A18 A7 Vec C33 D14 K2 Vss V2 Vss AF2 Vss AL25 A16 AQ Vec C35 D10 K4 D59 v4 AHOLD | AF4 PCHK# AL27 Al4 Alt Veco C37 Dg K34 DO V34 SUS P# AF34 A21 AL29 Al2 A13 Vec D2 D50 K36 Vss V36 Vss AF36 Vss AL31 A111 A15 Vec D4 D48 | Veco w1 Vec AG1 Vec AL33 A7 A17 Vec D6 D44 L3 D61 W3 EWBE# | AG3 SMIACT# | AL35 A3 A19 Vec D8 D40 L5 D60 w5 KEN# AG5 PCD AL37 Vss A21 Vec D10 D39 L33 Veco W33 SUSPA# | AG33 A27 AM2 ADSC# A23 Vec D12 D37 L35 NC W35 Reserved | AG35 A24 AM4 EADS# A25 Vec D14 D35 L37 Veco W37 Vec AG37 Vec AM6 W/R# A27 Veco Di6 D33 M2 Vss x2 Vss AH2 Vss AM8 Vss A29 Vec D18 DP3 M4 D62 X4 BRDY# AH4 LOCK# AM10 Vss A311 D22 D20 D30 M34 TCK X34 Reserved | AH34 A26 AM12 Vss A33 D18 D22 D28 M36 Vss X36 Vss AH36 A22 AM14 Vss A35 D15 D24 D26 N1 Veco Y1 Vec AJ1 BREQ AM16 Vss A37 NC D26 D23 N3 D63 Y3 BRDYC# | AJ3 HLDA AM18 Vss B2 NC D28 D19 N5 DP7 Y5 NA# AJ5 ADS# AM20 Vss B4 D43 D30 DP1 N33 TDO Y33 CLKMUL | AJ33 A311 AM22 Vss B6 Vss D32 Di2 N35 TDI Y35 Reserved | AJ35 A25 AM24 Vss B8 Vss D34 D8 N37 Veco Y37 Vec AJ37 Vss AM26 Vss B10 Vss D36 DPO P2 Vss Z2 Vss AK2 AP AM28 Vss B12 Vss E1 D54 P4 NC Z4 BOFF# AK4 D/C# AM30 Vss B14 Vss E3 D52 P34 TMS Z34 NC AK6 HIT# AM32 A8 B16 Vss E5 D49 P36 Vss Z36 Vss AK8 A20M# AM34 A4 B18 Vss E7 D46 Qi Veco AA1 Vec AK10 BE1# AM36 A30 B20 Vss EQ D42 Q3 Reserved | AA3 Reserved | AK12 BE3# AN1 NC B22 Vss E33 D7 Q5 FERR# AA5 WB/WT# | AK14 BE5# AN3 NC B24 Vss E35 D6 Q33 TRST# AA33 WM_RST | AK16 BE7# AN5 NC B26 Vss E37 Veco Q35 NC AA35 IGNNE# | AK18 CLK AN7 FLUSH# B28 Vss F2 DP6 Q37 Veco AA37 Vec AK20 RESET ANQ Vec B30 D20 F4 D51 R2 Vss AB2 Vss AK22 A19 AN11 Vec B32 D16 F6 DP5 R4 Reserved | AB4 HOLD AK24 A17 AN13 Vec B34 D13 F34 D5 R34 BHOLD AB34 SMI# AK26 A15 AN15 Vec B36 D11 F36 D4 R36 Vss AB36 Vss AK28 A13 AN17 Vec C1 NC G1 Veco $1 Veco AC1 Vec AK30 AQ AN19 Vec C3 D47 G3 D55 $3 Reserved | AC3 Reserved | AK32 A5 AN21 Veco c5 D45 G5 D53 $5 LBA# AC5 NC AK34 A29 AN23 Vec C7 DP4 G33 D3 $33 Reserved | AC33 NMI AK36 A28 AN25 Vec cg D38 G35 D1 $35 DHOLD- | AC35 NC AL1 NC AN27 Vec C11 D36 G37 Veco $37 Veco AC37 Vec AL3 PWT AN29 Vec C13 D34 H2 Vss T2 Vss AD2 Vss AL5 HITM# AN31 A10 C15 D32 H4 D56 T4 MV/O# AD4 NC AL7 QDUMP# | AN33 A6 C17 D31 H34 NC T34 Veco AD34 INTR ALQ BEO# AN35 Reserved c19 D29 H36 Vss T36 Vss AD36 Vss AL11 BE2# AN37 Vss C2 D27 J1 Veco Ut Veco AE1 Vec AL13 BE4# C23 D25 J3 D57 U3 CACHE# | AE3 NC AL15 BE6# C25 DP2 J5 D58 U5 INV AE5 APCHK# | AL17 SCYC C2724 J33 Reserve U33 Voc AE33 A23 AL19 Reserved Note: Reserved pins are reserved for future use by SGS-THOMSON only. Pins marked NC are not internally connected. 46/53 as SGS-THOMSON HICRGELESTECHICSST6x86 Table 4.2. 296-Pin CPGA Package Pin Numbers Sorted by Signal Name Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin A3 AL35 CLKMUL Y33 D48 D4 Nc AN3 Vec AA37 Vss AM12 A4 AM34 DiC# AK4 D49 E5 NC AN5 Vec AC1 Vss AM14 A5 AK32 DO K34 D50 D2 NC B2 Vec AC37 Vss AM16 A6 AN33 D1 G35 D51 F4 NC ci Vec AE1 Vss AM18 A7 AL33 D2 J35 D52 E3 NC H34 Vec AE37 Vss AM20 A8& AM32 D3 G33 D53 G5 NC L35 Vec AGI Vss AM22 AQ AK30 D4 F36 D54 E1 NC P4 Vec AG37 Vss AM24 A10 AN31 D5 F34 D55 G3 NC Q35 Vee AN11 Vss AM26 Alt AL31 D6 E35 D56 H4 NC 234 Vec AN13 Vss AM28 A12 AL29 D7 E33 D57 J3 NMI AC33 Vec AN15 Vss AM30 A13 AK28 D8 D34 D58 J5 PCD AG5 Vec AN17 Vss AM8& Al4 AL27 Dg C37 D59 K4 PCHK# AF4 Vec AN19 Vss AN37 A15 AK26 D10 C35 D60 L5 PWT AL3 Vec AN21 Vss B6 A16 AL25 D11 B36 D61 L3 QDUMP# AL7 Vec AN23 Vss B8 A17 AK24 D12 D32 D62 M4 RESET AK20 Vec AN25 Vss B10 A18 AL23 D13 B34 D63 N3 SCYC AL17 Vec AN27 Vss B12 A19 AK22 D14 C33 DHOLD $35 Reserved AA3 Vec AN29 Vss B14 A20 AL21 D15 A35 DPO D36 Reserved AC3 Vec ANQ Vss B16 A20M# AK8& D16 B32 DP1 D30 Reserved AL19 Vec E37 Vss B18 A21 AF34 D17 C31 DP2 C25 Reserved AN35 Vec G1 Vss B20 A22 AH36 D18 A33 DP3 D18 Reserved J33 Vec G37 Vss B22 A23 AE33 D19 D28 DP4 C7 Reserved Q3 Vee J1 Vss B24 A24 AG35 D20 B30 DP5 F6 Reserved R4 Vec J37 Vss B26 A25 AJ35 D21 C29 DP6 F2 Reserved S3 Vec L1 Vss B28 A26 AH34 D22 A31 DP7 N5 Reserved S33 Vec L33 Vss H2 A27 AG33 D23 D26 EADS# AM4 Reserved W235 Vec L37 Vss H36 A28 AK36 D24 C27 EWBE# W3 Reserved X34 Vec N1 Vss K2 A29 AK34 D25 C23 FERR# Q5 Reserved Y35 Vec N37 Vss K36 A30 AM36 D26 D24 FLUSH# AN7 SMI# AB34 Vee Q1 Vss M2 A31 AJ33 D27 C21 HIT# AK6 SMIACT# AG3 Vee Q37 Vss M36 ADS# AJ5 D28 D22 HITM# ALS SUSP# V34 Vec $1 Vss P2 ADSC# AM2 D2g ci9 HLDA AJ3 SUSPA# W833 Vec $37 Vss P36 AHOLD V4 D30 D20 HOLD AB4 TCK M34 Vec T34 Vss R2 AP AK2 D31 Ci7 IGNNE# AA35 TDI N35 Vec U1 Vss R36 APCHK# AE5 D32 C15 INTR AD34 TDO N33 Vec U33 Vss T2 BEO# ALQ D33 D16 INV U5 TMS P34 Vec U37 Vss T36 BE1# AK10 D34 C13 KEN# Ww5 TRST# Q33 Vee wi Vss U35 BE2# AL11 D35 D14 LBA# $5 Vec A7 Vec W37 Vss v2 BES# AK12 D36 ct LOCK# AH4 Vec AQ Vec Y1 Vss V36 BE4# AL13 D37 D12 MI/O# T4 Vec All Vec Y37 Vss x2 BES# AK14 D38 cg NA# Y5 Vec A13 Vss AB2 Vss X36 BE6# AL15 D39 D10 NC A3 Vec A15 Vss AB36 Vss 22 BE7# AK16 D40 D8 NC A37 Vec A17 Vss AD2 Vss 236 BHOLD R34 D41 A5 NC AC35 Vec A19 Vss AD36 WB/WT# AAS BOFF# 24 D42 E9 NC AC5 Vec A21 Vss AF2 W/R# AM6 BRDY# X4 D43 B4 NC AD4 Vec A23 Vss AF36 WM_RST AA33 BRDYC# Y3 D44 D6 NC AE3 Vec A25 Vss AH2 BREQ AJ1 D45 C5 NC AE35 Vec A27 Vss AJ37 CACHE# U3 D46 E7 NC AL1 Vec A29 Vss AL37 CLK AK18 D47 C3 NC AN1 Vec AAI Vss AM10 Note: Reserved pins are reserved for future use by SGS-THOMSON only. Pins marked NC are not internally connected. Lyf SGS-THOMSON HICRGELESTECHICS 47/53ST6x86 Figure 4.2. 296-Pin CPGA Package SEATING PLANE > >L < va D > < o < Dt >| si > o 09 6 89 09 6 6 6 8 oe eo oe ee 8 1.65 60 69 80 6 Oo oo 89 09 0 Oo REF 0 0 6 60 o@ 8 6 6 be Oo 8 eB ee oo . 6 6 6 8 8 6 Oo o 6 6 0 6 @ 8 Oo Vv o 0 6 a) ~] 5oo UU OU 0 0 A oo o 0 ooo ooo a) ar) oo a) oo o 9 oo 6 oo 9 o 9 o 9 o 0 0 oo 9 a) e 6 9 9 eo 9 o 6 o 6 o 0 6 rr) oo o 9 o 9 6 oo 8 oo ar) oo 6 oo 6 a) oo a) a) o 9 oo 6 oo 9 o 9 o 9 ooo oo 9 o 9 oso Pin G3 ae og qo 36 | o 6 6 a) o 6 60 6 0 6 46 0 8 6 0 6 6 8 8 mo 0 6 6 G6 & 6 6 6 6 8 oo 60 6 oo 69 6 >| o >|< A 45 CHAMFER Al 2.29pe- (INDEX CORNER) A2 152 A I< D > << D3 ___+> |< b2 >| ro. | PT _ e CU WHEAT SPREADER o___+_ raze METALIZATION v < D4-> 1739000 48/53 S$GS-THOMSON Lyf HICRGELESTECHICSST6x86 Table 4.3. 296-Pin CPGA Package Dimensions MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 3.91 4.70 0.154 0.185 Al 0.33 0.43 0.013 0.017 A2 2.51 3.07 0.099 0.121 B 0.43 0.51 0.017 0.020 49.28 49.91 1.940 1.965 D1 45.47 45.97 1.790 1.810 D2 31.50 Sq. 32.00 Sq. 1.240 Sq. 1.260 Sa. D3 33.99 34.59 1.338 1362 D4 8.00 9.91 0.315 0.390 E1 2.41 2.67 0.095 0.105 E2 1.14 1.40 0.045 0.055 F - 0.127 Diag. - 0.005 Diag. 3.05 3.30 0.120 0.130 N 296 (Pin Count) S1 1.65 2.16 | 0.065 0.085 49/53 4&7 S&S:THOMsoN + LICROELESTRONIESST6x86 4.2 Thermal Characteristics The ST6x86 processor is designed to operate when the case temperature at the top center of the pack- age is between 0C and 70C. The maximum die (junction) temperature, Tj yax, and the maximum ambient temperature, Ta yax, can be calculated by substituting thermal resistance and maximum values for case or junction temperature and power dissipation in the following equations: Ty =Te + (P * 95c) Ta = Ty - (P * Oj) where Ta = Ambient temperature (C) Ty = Average junction temperature (C) To = Case temperature at top center of package (C) P = Power dissipation (W) 8j = Junction-to-case thermal resistance (C/W) 834 = Junction-to-ambient thermal resistance (C/W). Table 4.4 lists the junction-to-case and case-to-ambient thermal resistances forthe SPGA package. 50/53 K77_ SGS-THOMSON + LICROELESTRONIESST6x86 Table 4.4. Thermal Resistances for CPGA Package With and Without Heatsinks Thermal Resistance Ojo C/W Oca C/W Laminar Air Flow (ft/min) 0 0 100 200 400 600 800 1.95 x 1.95 x 0.25 Heatsink 0.9 8.4 74 6.0 4.0 3.1 26 1.95 x 1.95 x 0.40 Heatsink 0.9 7.7 6.6 49 3.2 2.7 21 1.95 x 1.95 x 0.65 Heatsink 0.9 5.9 4.7 3.2 2.1 1.7 14 Without Heatsink 1.4 147 11.5 9.1 73 7.0 6.2 Notes: For a ST6x86 processor with 1.25 x 1.25 x 0.40 inch CuW heat spreader. Heatsinks are omni-directional pin aluminum alloy. Features are based on standard extrusion practices for a given height. Heatsink attachment was made with 0.006 inch of thermal grease applied between heatsink and case. Maximum air temperature is assumed to be 40 c 51/53 ky, 2GS-THOMSON JF, UGROLLECTEOMIESST6x86 Ordering Information Example: ST 6X86 P120+ H Ss | SGS Thomson] | Device Speed Equalizer | Package Type S= Supply Voltage Prefix Name | pg04= 80MHz(internal) H = CPGA Package (3.52 V Commercial P120+=100MHcz(internal) B=BGA Package Grade Temperature) P133+4=110MHz(internal) P150+=120Mhz(internal) P166+=133MHcz(internal) P200+=150MHcz(internal) Please contact your nearest SGS-THOMSON sales office to confirm availability of specific valid combinations and to check on newly released combinations. P =PPGA Package 52/53 K77_ SGS-THOMSON + LICROELESTRONIESST6x86 The ST6x86 CPU part numbers are listed below. ST6x86 Part Numbers FREQUENCY NOM (MHz) PART NUMBER Vee (V) BUS INTERNAL ST6X86P90+HS 3.52 40 80 ST6X86P120+HS 3.52 50 100 ST6X86P133+HS 3.52 55 110 ST6X86P150+HS 3.52 60 120 ST6X86P166+HS 3.52 66 133 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. SGS-THOMSON Microelectronics. All rights reserved. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia Brazil France - Germany Hong Kong - Italy - Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Taiwan United Kingdom U.S.A. SGS-THOMSON 53/53 HICRGELESTECHICS