1/111
NOT FOR NEW DESIGN
October 2008 Rev 5
This is information on a product still in production but not recommended for new designs.
PSD813F1A
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 5 V
FEATURES SUMMARY
■DUAL BANK FLASH MEMORIES
– 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
– 256 Kbit Secondary EEPROM (4 Uniform
Sectors)
– Concurrent operation: read from one
memory while erasing and writing the
other
■16 Kbit SRAM
■PLD WITH MACROCELLS
– Over 3,000 Gates Of PLD: DPLD and
CPLD
– DPLD - User-defined Internal chip-select
decoding
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
■27 RECONFIGURABLE I/Os
– 27 individually configurable I/O port pins
that can be used for the following
functions (16 I/O ports configurable as
open-drain outputs):
MCU I/Os
PLD I/Os
Latched MCU address output; and
Special function I/Os
■ENHANCED JTAG SERIAL PORT
– Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
– Efficient manufacturing allows for easy
product testing and programming
■PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
■PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
■HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
■SINGLE SUPPLY VOLTAGE:
–5V±10% for 5V
■STANDBY CURRENT AS LOW AS 50µA
■Packages are ECOPACK®
PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
PSD813F1A
2/111
TABLE OF CONTENTS
Features Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Simultaneous read and write to Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Microcontroller Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MEMORY BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Primary Flash Memory and Secondary EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Block Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ready/Busy Pin (PC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EEPROM Power Down Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Main Flash Memory Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Main Flash Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
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PSD813F1A
Reading the OTP Row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Time-out Flag DQ3 (Flash Memory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Writing to the EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Writing a Byte to EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Writing a Page to EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EEPROM Software Data Protect (SDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Writing the OTP Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FLASH AND EEPROM MEMORY SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash Memory and EEPROM Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 31
Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PLD’S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Loading and Reading the Output Macrocells (OMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
PSD813F1A
4/111
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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PSD813F1A
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 71
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Security, Flash memory and EEPROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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SUMMARY DESCRIPTION
The PSD family of Programmable Microcontroller
(MCU) Peripherals brings In-System Programma-
bility (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded designs. PSD devices combine many
of the peripheral functions found in MCU based
applications.
PSD devices integrate an optimized “microcon-
troller macrocell” logic architecture. The Macrocell
was created to address the unique requirements
of embedded system designs. It allows direct con-
nection between the system address/data bus and
the internal PSD registers to simplify communica-
tion between the MCU and other supporting devic-
es.
The PSD family offers two methods to program
PSD Flash memory while the PSD is soldered to a
circuit board.
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG interface is in-
cluded on the PSD enabling the entire device
(Flash memory, EEPROM, the PLD, and all con-
figuration) to be rapidly programmed while sol-
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even while completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash the very first time? JTAG is the an-
swer, program the PSD while blank with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to customer. No more labels on chips and no more
wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)
Two independent memory arrays (Flash and EE-
PROM) are included so the MCU can execute
code from one memory while erasing and pro-
gramming the other. Robust product firmware up-
dates in the field are possible over any
communication channel (CAN, Ethernet, UART,
J1850, etc.) using this unique architecture. De-
signers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry. How can the MCU program the same memory
from which it is executing code? It cannot. The
PSD allows the MCU to operate the two memories
concurrently, reading code from one while erasing
and programming the other during IAP.
Complex memory mapping. I have only a 64K-
byte address space to start with. How can I map
these two memories efficiently? A Programmable
Decode PLD is the answer. The concurrent PSD
memories can be mapped anywhere in MCU ad-
dress space, segment by segment with extremely
high address resolution. As an option, the second-
ary Flash memory can be swapped out of the sys-
tem memory map when IAP is complete. A built-in
page register breaks the 64K-byte address limit.
Separate program and data space. How can I
write to Flash or EEPROM memory while it resides
in “program” space during field firmware updates,
my MCU won’t allow it! The Flash PSD provides
means to “reclassify” Flash or EEPROM memory
as “data” space during IAP, then back to “program”
space when complete.
PSDsoft Express
PSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
definitions, programmable logic inputs and out-
puts, MCU memory map definition, ANSI-C code
generation for your MCU, and merging your MCU
firmware with the PSD design. When complete,
two different device programmers are supported
directly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
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PSD813F1A
Figure 2. PQFP52 Connections
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 VCC
30 AD7
29 AD6
28 AD5
27 AD4
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
1
2
3
4
5
6
7
8
9
10
11
12
13
52
51
50
49
48
47
46
45
44
43
42
41
40
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
CNTL1
CNTL2
RESET
CNTL0
14
15
16
17
18
19
20
21
22
23
24
25
26
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AI02858
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Figure 3. PLCC52 Connections
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
CNTL1
CNTL2
RESET
CNTL0
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
VCC
AD7
AD6
AD5
AD4
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
21
22
23
24
25
26
27
28
29
30
31
32
33
47
48
49
50
51
52
1
2
3
4
5
6
7
AI02857
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PSD813F1A
Figure 4. TQFP64 Connections
48 CNTL0
47 AD15
46 AD14
45 AD13
44 AD12
43 AD11
42 AD10
41 AD9
40 AD8
39 VCC
38 VCC
37 AD7
36 AD6
35 AD5
34 AD4
33 AD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
GND
PC3
PC2
PC1
PC0
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
NC
PB0
PB1
PB2
PB3
PB4
PB5
GND
GND
PB6
PB7
CNTL1
CNTL2
RESET
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
NC
PA7
PA6
PA5
PA4
PA3
GND
GND
PA2
PA1
PA0
AD0
AD1
ND
AD2
AI09644
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PIN DESCRIPTION
Table 1. Pin Description (for the PLCC52 package)
Pin Name Pin Type Description(1)
ADIO0-7 30-37 I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, or you are using an
80C251 in page mode, connect A0-A7 to this port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
ADIO8-15 39-46 I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
CNTL0 47 I
The following control signals can be connected to this port, based on your MCU:
1. WR – active Low Write Strobe input.
2. R_W – active High READ/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL1 50 I
The following control signals can be connected to this port, based on your MCU:
1. RD – active Low Read Strobe input.
2. E – E clock input.
3. DS – active Low Data Strobe input.
4. PSEN – connect PSEN to this port when it is being used as an active Low READ
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is
actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL2 49 I
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.
Reset 48 I Active Low Reset input. Resets I/O Ports, PLD macrocells and some of the Configuration
Registers. Must be Low at Power-up.
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PSD813F1A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 20 I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 19 I/O
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2 18 I/O
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
PC3 17 I/O
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output2 for the JTAG Serial Interface.
5. Ready/Busy output for In-System parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 14 I/O
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC4) output.
3. Input to the PLDs.
4. TERR output2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
Pin Name Pin Type Description(1)
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Note: 1. The pin numbers in this table are for the PLCC package only. See the Figure 2., page 7, for pin numbers on other package type.
2. These functions can be multiplexed with other functions.
PC5 13 I/O
PC5 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC5) output.
3. Input to the PLDs.
4. TDI input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC6 12 I/O
PC6 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC6) output.
3. Input to the PLDs.
4. TDO output2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC7 11 I/O
PC7 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC7) output.
3. Input to the PLDs.
4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0 10 I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O – write or read from a standard output or input port.
3. Input to the PLDs.
4. CPLD output (External Chip Select).
PD1 9 I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
PD2 8 I/O
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/
O. When High, the PSD memory blocks are disabled to conserve power.
VCC 15, 38 Supply Voltage
GND 1, 16,
26 Ground pins
Pin Name Pin Type Description(1)
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PSD813F1A
Figure 5. Block Diagram
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 – AD15
CLKIN
CLKIN
CLKIN
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
1 MBIT MAIN
FLASH MEMORY
8 SECTORS
VSTDBY
PA0 – PA7
PB0 – PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PC0 – PC7
PD0 – PD2
ADDRESS/DATA/CONTROL BUS
PORT A ,B & C
3 EXT CS TO PORT D
24 INPUT MACROCELLS
PORT A ,B & C
73
73
256 KBIT SECONDARY
MEMORY (BOOT OR DATA)
4 SECTORS
EEPROM - F1
16 KBIT SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
PERIP I/O MODE SELECTS
MACROCELL FEEDBACK OR PORT INPUT
CSIOP
FLASH ISP CPLD
(CPLD) 16 OUTPUT MACROCELLS
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PC2)
PAGE
REGISTER EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
AI02861G
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PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 5 shows the architecture of the PSD
device. The functions of each block are described
briefly in the following sections. Many of the blocks
perform multiple functions and are user configu-
rable.
Memory
The PSD contains the following memories:
■a 1 Mbit Flash memory
■a secondary 256 Kbit EEPROM memory
■a 16 Kbit SRAM
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-
sion can be found in the section entitled MEMORY
BLOCKS, page 18.
The 1 Mbit Flash memory is the main memory of
the PSD. It is divided into 8 equally-sized sectors
that are individually selectable.
The 256 Kbit EEPROM or Flash memory is divided
into 4 equally-sized sectors. Each sector is individ-
ually selectable.
The 16 Kbit SRAM is intended for use as a
scratchpad memory or as an extension to the mi-
crocontroller SRAM.
Each sector of memory can be located in a differ-
ent address space as defined by the user. The ac-
cess times for all memory types includes the
address latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, each opti-
mized for a different function, as shown in Table 2.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The Decode PLD (DPLD) is used to decode ad-
dresses and generate chip selects for the PSD in-
ternal memory and registers. The CPLD can
implement user-defined logic functions. The DPLD
has combinatorial outputs. The CPLD has 16 Out-
put macrocells and 3 combinatorial outputs. The
PSD also has 24 Input macrocells that can be con-
figured as inputs to the PLDs. The PLDs receive
their inputs from the PLD Input Bus and are differ-
entiated by their output destinations, number of
Product Terms, and macrocells.
The PLDs consume minimal power by using Zero-
Power design techniques. The speed and power
consumption of the PLD is controlled by the Turbo
Bit (ZPSD only) in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at runtime. There is a
slight penalty to PLD propagation time when in-
voking the ZPSD features.
I/O Ports
The PSD has 27 I/O pins divided among four ports
(Port A, B, C, and D). Each I/O pin can be individ-
ually configured for different functions. Ports A, B,
C and D can be configured as standard MCU I/O
ports, PLD I/O, or latched address outputs for mi-
crocontrollers using multiplexed address/data
busses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a n on-multiplexed bus or multiplexed Ad-
dress/Data buses for certain types of 16-bit micro-
controllers.
Microcontroller Bus Interface
The PSD easily interfaces with most 8-bit micro-
controllers that have either multiplexed or non-
multiplexed address/data busses. The device is
configured to respond to the microcontroller’s con-
trol signals, which are also used as inputs to the
PLDs. Where there is a requirement to use a 16-
bit data bus to interface to a 16-bit microcontroller,
two PSDs must be used. For examples, please
see the section entitled MCU Bus Interface
Examples, page 47.
Table 2. PLD I/O
Name Inputs Outputs Product
Terms
Decode PLD (DPLD) 73 17 42
Complex PLD (CPLD) 73 19 140
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PSD813F1A
JTAG Port
In-System Programming can be performed
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 3 indicates the
JTAG signals pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller executing the programming
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
Page Register
The 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
Power Management Unit (PMU)
The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the section entitled POWER
MANAGEMENT, page 64 for more details.
Table 3. JTAG SIgnals on Port C
Table 4. Methods of Programming Different Functional Blocks of the PSD
Port C Pins JTAG Signal
PC0 TMS
PC1 TCK
PC3 TSTAT
PC4 TERR
PC5 TDI
PC6 TDO
Functional Block JTAG Programming Device Programmer In-System Parallel
Programming
Main Flash Memory Yes Yes Yes
EEPROM Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No
Optional OTP Row No Yes Yes
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DEVELOPMENT SYSTEM
The PSD is supported by PSDsoft Express a Win-
dows-based (95, 98, NT) software development
tool. A PSD design is quickly and easily produced
in a point and click environment. The designer
does not need to enter Hardware Definition Lan-
guage (HDL) equations (unless desired) to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 6 be-
low. PSDsoft Express is available from our web
site (www.st.com/psm) or other distribution chan-
nels.
PSDsoft Express directly supports two low cost
device programmers from ST, PSDpro and Flash-
LINK (JTAG). Both of these programmers may be
purchased through your local distributor/represen-
tative, or directly from our web site using a credit
card. The PSD is also supported by third party de-
vice programmers, see web site for current list.
Figure 6. PSDsoft Express Development Tool
Define PSD Pin and
Node functions
Define General Purpose
Logic in CPLD
ST PSD Programmer
*.OBJ FILE
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
PSDPro, or
FlashLINK (JTAG)
Point and click definition of
combinatorial and registered logic
in CPLD. Access to HDL is
available if needed
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
C Code Generation
Generate C Code
Specific to PSD
Functions
User's choice of
Microcontroller
Compiler/Linker
*.OBJ file
available
for 3rd party
programmers
(Conventional or JTAG-ISC)
MCU Firmware
Hex or S-Record
format
AI09215
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration.
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PSD813F1A
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. I/O Port Latched Address Output Assignments
Note: 1. See the section entitled I/O PORTS, page 52, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 6. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
MCU(1) Port A(2) Port B(2)
Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)
8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A
80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12
All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4
Register Name Port
A
Port
B
Port
C
Port
DOther(1) Description
Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode
Control 02 03 Selects mode between MCU I/O or Address Out
Data Out 04 05 12 13 Stores data for output to Port pins, MCU I/O output
mode
Direction 06 07 14 15 Configures Port pin as input or output
Drive Select 08 09 16 17
Configures Port pins as either CMOS or Open Drain
on some pins, while selecting high slew rate on other
pins.
Input Macrocell 0A 0B 18 Reads Input Macrocells
Enable Out 0C 0D 1A 1B Reads the status of the output enable to the I/O Port
driver
Output Macrocells
AB 20 20 READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
Output Macrocells
BC 21 21 READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Mask Macrocells
AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells
BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash
Protection C0 Read only – Flash Sector Protection
Secondary Flash
memory
Protection
C2 Read only – PSD Security and EEPROM Sector
Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
VM E2
Places PSD memory areas in Program and/or Data
space on an individual basis.
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DETAILED OPERATION
As shown in Figure 5., page 13, the PSD consists
of six major types of functional blocks:
■Memory Blocks
■PLD Blocks
■MCU Bus Interface
■I/O Ports
■Power Management Unit (PMU)
■JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD has the following memory blocks (see
Table 7):
– The Main Flash memory
– Secondary EEPROM memory
–SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary
EEPROM Description
The 1Mb primary Flash memory is divided evenly
into eight 16-KByte sectors. The EEPROM memo-
ry is divided into four sectors of eight KBytes each.
Each sector of either memory can be separately
protected from Program and Erase operations.
Flash memory may be erased on a sector-by-sec-
tor basis and programmed byte-by-byte. Flash
sector erasure may be suspended while data is
read from other sectors of memory and then re-
sumed after reading.
EEPROM may be programmed byte-by-byte or
sector-by-sector, and erasing is automatic and
transparent. The integrity of the data can be se-
cured with the help of Software Data Protection
(SDP). Any write operation to the EEPROM is in-
hibited during the first five milliseconds following
power-up.
During a program or erase of Flash, or during a
write of the EEPROM, the status can be output on
the Ready/Busy (PC3) pin of Port C3. This pin is
set up using PSDsoft Express Configuration.
Memory Block Select Signals. The decode
PLD in the PSD generates the chip selects for all
the internal memory blocks (refer to the section
entitled PLD’S, page 34). Each of the eight Flash
memory sectors have a Flash Select signal (FS0-
FS7) which can contain up to three product terms.
Each of the four EEPROM memory sectors have a
Select signal (EES0-3 or CSBOOT0-3) which can
contain up to three product terms. Having three
product terms for each sector select signal allows
a given sector to be mapped in different areas of
system memory. When using a microcontroller
with separate Program and Data space, these
flexible select signals allow dynamic re-mapping of
sectors from one space to the other.
Ready/Busy Pin (PC3). Pin PC3 can be used to
output the Ready/Busy status of the PSD. The out-
put on the pin will be a ‘0’ (Busy) when Flash or
EEPROM memory blocks are being written to, or
when the Flash memory block is being erased.
The output will be a ‘1’ (Ready) when no write or
erase operation is in progress.
Table 7. Memory Blocks
Device Main Flash EEPROM SRAM
PSD813F1A 128KB 32KB 2KB
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Memory Operation
The main Flash and EEPROM memory are ad-
dressed through the microcontroller interface on
the PSD device. The microcontroller can access
these memories in one of two ways:
– The microcontroller can execute a typical bus
WRITE or READ operation just as it would if
accessing a RAM or ROM device using
standard bus cycles.
– The microcontroller can execute a specific
instruction that consists of several WRITE and
READ operations. This involves writing
specific data patterns to special addresses
within the Flash or EEPROM to invoke an
embedded algorithm. These instructions are
summarized in Table 8., page 20.
Typically, Flash memory can be read by the micro-
controller using READ operations, just as it would
read a ROM device. However, Flash memory can
only be erased and programmed with specific in-
structions. For example, the microcontroller can-
not write a single byte directly to Flash memory as
one would write a byte to RAM. To program a byte
into Flash memory, the microcontroller must exe-
cute a program instruction sequence, then test the
status of the programming event. This status test
is achieved by a READ operation or polling the
Ready/Busy pin (PC3).
The Flash memory can also be read by using spe-
cial instructions to retrieve particular Flash device
information (sector protect status and ID).
The EEPROM is a bit different. Data can be written
to EEPROM memory using write operations, like
writing to a RAM device, but the status of each
WRITE event must be checked by the microcon-
troller. A WRITE event can be one to 64 contigu-
ous bytes. The status test is very similar to that
used for Flash memory (READ operation or
Ready/Busy). Optionally, the EEPROM memory
may be put into a Software Data Protect (SDP)
mode where it requires instructions, rather than
operations, to alter its contents. SDP mode makes
writing to EEPROM much like writing to Flash
memory.
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Table 8. Instructions
Note: 1. Additional sectors to be erased must be entered within 80 µs. A Sector Address is any address within the Sector.
2. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don’t cares in Instruction Bus Cycles.
3. The Reset instruction is required to return to the normal READ mode if DQ5 goes high or after reading the Flash Identifier or Pro-
tection status.
4. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other
memory when these instructions are performed.
5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended.
The MCU must operate from some other memory when these instructions are executed.
6. Writing to OTP Row is allowed only when SDP mode is disabled.
Instruction
EEPROM
Sector Select
(EESi)
Flash Sector
Select (FSi)(2) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Read Flash
Identifier3,5 01
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read
Identifier
with
(A6,A1,A0
at 0,0,1)
Read OTP
row410
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read byte
1
Read
byte 2
Read
byte N
Read Sector
Protection
Status3,5
01
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read
identifier
with (A6,
A1; A0 =
0,1,0)
Program a
Flash Byte501
AAh@
X555h
55h@
XAAAh
A0h@
X555h
Data@
address
Erase one
Flash Sector501
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@
X555h
55h@
XAAAh
30h@
Sector
address
30h@
Sector
address1
Erase the
Whole Flash501
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@
X555h
55h@
XAAAh
10h@
X555h
Suspend
Sector Erase501
B0h@
XXXXh
Resume
Sector Erase501
30h@
XXXXh
EEPROM
Power Down410
AAh@
X555h
55h@
XAAAh
30h@
X555h
SDP Enable/
EEPROM
Write4
10
AAh@
X555h
55h@
XAAAh
A0h@
X555h
Write byte
1
Write
byte 2
Write
byte N
SDP Disable410
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@
X555h
55h@
XAAAh
20h@
X555h
Write in OTP
Row4,6 10
AAh@
X555h
55h@
XAAAh
B0h@
X555h
Write byte
1
Write
byte 2
Write
byte N
Return (from
OTP Read or
EEPROM
Power-Down)4
10
F0h@
XXXX
Reset3.5 01
AAh@
X555h
55h@
XAAAh
F0h@
XXXX
Reset (short
instruction)501
F0h@
XXXX
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PSD813F1A
INSTRUCTIONS
An instruction is defined as a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value. Some instructions
are structured to include READ operations after
the initial WRITE operations.
The sequencing of any instruction must be fol-
lowed exactly. Any invalid combination of instruc-
tion bytes or time-out between two consecutive
bytes while addressing Flash memory will reset
the device logic into READ mode (Flash memory
reads like a ROM device). An invalid combination
or time-out while addressing the EEPROM block
will cause the offending byte to be interpreted as a
single operation.
The PSD supports these instructions (see Table
8., page 20):
Flash memory:
■Erase memory by chip or sector
■Suspend or resume sector erase
■Program a Byte
■Reset to READ mode
■Read Flash Identifier value
■Read Sector Protection Status
EEPROM:
■ Write data to OTP Row
■ Read data from OTP Row
■ Power down memory
■ Enable Software Data Protect (SDP)
■ Disable SDP
■ Return from read OTP Row read mode or
power down mode.
These instructions are detailed in Table
8., page 20. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of
writing the data AAh to address X555h during the
first cycle and data 55h to address XAAAh during
the second cycle. Address lines A15-A12 are don’t
cares during the instruction WRITE cycles. How-
ever, the appropriate sector select signal (FSi or
EESi) must be selected.
Power-down Instruction and Power-up Mode
EEPROM Power Down Instruction. The EE-
PROM can enter power down mode with the help
of the EEPROM power down instruction (see Ta-
ble 8., page 20). Once the EEPROM power down
instruction is decoded, the EEPROM memory can-
not be accessed unless a Return instruction (also
in Table 8., page 20) is decoded. Alternately, this
power down mode will automatically occur when
the APD circuit is triggered (see section entitled
Automatic Power-down (APD) Unit and Power-
down Mode, page 65). Therefore, this instruction
is not required if the APD circuit is used.
Power-up Mode. The PSD internal logic is reset
upon power-up to the READ mode. Any write op-
eration to the EEPROM is inhibited during the first
5ms following power-up. The FSi and EESi select
signals, along with the write strobe signal, must be
in the false state during power-up for maximum se-
curity of the data contents and to remove the pos-
sibility of a byte being written on the first edge of a
write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
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READ
Under typical conditions, the microcontroller may
read the Flash or EEPROM memory using READ
operations just as it would a ROM or RAM device.
Alternately, the microcontroller may use READ op-
erations to obtain status information about a Pro-
gram or Erase operation in progress. Lastly, the
microcontroller may use instructions to read spe-
cial data from these memories. The following sec-
tions describe these READ functions.
Read Memory Contents. Main Flash is placed in
the READ mode after power-up, chip reset, or a
Reset Flash instruction (see Table 8., page 20).
The microcontroller can read the memory contents
of main Flash or EEPROM by using READ opera-
tions any time the READ operation is not part of an
instruction sequence.
Read Main Flash Memory Identifier. The main
Flash memory identifier is read with an instruction
composed of 4 operations:
3 specific write operations and a READ operation
(see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,0,1, respec-
tively, and the appropriate sector select signal
(FSi) must be active. The Flash ID is E3h for the
PSD. The MCU can read the ID only when it is ex-
ecuting from the EEPROM.
Read Main Flash Memory Sector Protection
Status. The main Flash memory sector protection
status is read with an instruction composed of 4
operations: 3 specific WRITE operations and a
READ operation (see Table 8., page 20). During
the READ operation, address bits A6, A1, and A0
must be 0,1,0, respectively, while the chip select
FSi designates the Flash sector whose protection
has to be verified. The READ operation will pro-
duce 01h if the Flash sector is protected, or 00h if
the sector is not protected.
The sector protection status for all NVM blocks
(main Flash or EEPROM) can be read by the mi-
crocontroller accessing the Flash Protection and
PSD/EE Protection registers in PSD I/O space.
See Flash Memory and EEPROM Sector
Protect, page 30 for register definitions.
Reading the OTP Row. There are 64 bytes of
One-Time-Programmable (OTP) memory that re-
side in EEPROM. These 64 bytes are in addition
to the 32 Kbytes of EEPROM memory. A READ of
the OTP row is done with an instruction composed
of at least 4 operations: 3 specific WRITE opera-
tions and one to 64 READ operations (see Table
8., page 20). During the READ operation(s), ad-
dress bit A6 must be zero, while address bits A5-
A0 define the OTP Row byte to be read while any
EEPROM sector select signal (EESi) is active. Af-
ter reading the last byte, an EEPROM Return in-
struction must be executed (see Table
8., page 20).
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
microcontroller to confirm the completion of an
erase or programming instruction of Flash memo-
ry. Bits are also available to show the status of
WRITES to EEPROM. These status bits minimize
the time that the microcontroller spends perform-
ing these tasks and are defined in Table 9. The
status bits can be read as many times as needed.
For Flash memory, the microcontroller can per-
form a READ operation to obtain these status bits
while an Erase or Program instruction is being ex-
ecuted by the embedded algorithm. See the sec-
tion entitled PROGRAMMING FLASH
MEMORY, page 27 for details.
For EEPROM not in SDP mode, the microcon-
troller can perform a READ operation to obtain
these status bits just after a data WRITE opera-
tion. The microcontroller may write one to 64 bytes
before reading the status bits. See the section en-
titled Writing to the EEPROM, page 24 for details.
For EEPROM in SDP mode, the microcontroller
will perform a READ operation to obtain these sta-
tus bits while an SDP write instruction is being ex-
ecuted by the embedded algorithm. See section
entitled EEPROM Software Data Protect
(SDP), page 24 for details.
Table 9. Status Bit
Note: 1. X = not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
3. FSi and EESi are active High.
Device FSi/
CSBOOTi EESi DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Flash VIH VIL Data Polling Toggle
Flag
Error
Flag XErase
Timeout XXX
EEPROM VIL VIH Data Polling Toggle
Flag X X X XXX
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PSD813F1A
Data Polling Flag (DQ7)
When Erasing or Programming the Flash memory
(or when Writing into the EEPROM memory), bit
DQ7 outputs the complement of the bit being en-
tered for Programming/Writing on DQ7. Once the
Program instruction or the WRITE operation is
completed, the true logic value is read on DQ7 (in
a Read operation). Flash memory specific fea-
tures:
– Data Polling is effective after the fourth WRITE
pulse (for programming) or after the sixth
WRITE pulse (for Erase). It must be performed
at the address being programmed or at an
address within the Flash sector being erased.
– During an Erase instruction, DQ7 outputs a ‘0.’
After completion of the instruction, DQ7 will
output the last bit programmed (it is a ‘1’ after
erasing).
– If the byte to be programmed is in a protected
Flash sector, the instruction is ignored.
– If all the Flash sectors to be erased are
protected, DQ7 will be set to ‘0’ for about
100µs, and then return to the previous
addressed byte. No erasure will be performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the EEPROM write or the Flash memory Program
instruction is completed. During the internal
WRITE operation and when either the FSi or EESi
is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to
‘0’ on subsequent attempts to read any byte of the
memory.
When the internal cycle is complete, the toggling
will stop and the data read on the Data Bus D0-7
is the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The operation is finished when two successive
reads yield the same output data. Flash memory
specific features:
■The Toggle bit is effective after the fourth
WRITE pulse (for programming) or after the
sixth WRITE pulse (for Erase).
■If the byte to be programmed belongs to a
protected Flash sector, the instruction is
ignored.
■If all the Flash sectors selected for erasure are
protected, DQ6 will toggle to ‘0’ for about 100
µs and then return to the previous addressed
byte.
Error Flag (DQ5)
During a correct Program or Erase, the Error bit
will set to ‘0.’ This bit is set to ‘1’ when there is a
failure during Flash byte programming, Sector
erase, or Bulk Erase.
In the case of Flash programming, the Error Bit in-
dicates the attempt to program a Flash bit(s) from
the programmed state ('0') to the erased state ('1'),
which is not a valid operation. The Error bit may
also indicate a timeout condition while attempting
to program a byte.
In case of an error in Flash sector erase or byte
program, the Flash sector in which the error oc-
curred or to which the programmed byte belongs
must no longer be used. Other Flash sectors may
still be used. The Error bit resets after the Reset in-
struction.
Erase Time-out Flag DQ3 (Flash Memory only)
The Erase Timer bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase timer bit is set to ‘0’ after a
Sector Erase instruction for a time period of 100µs
+ 20% unless an additional Sector Erase instruc-
tion is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ‘1.’
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Writing to the EEPROM
Data may be written a byte at a time to the EE-
PROM using simple write operations, much like
writing to an SRAM. Unlike SRAM though, the
completion of each byte write must be checked be-
fore the next byte is written. To speed up this pro-
cess, the PSD offers a Page write feature to allow
writing of several bytes before checking status.
To prevent inadvertent writes to EEPROM, the
PSD offers a Software Data Protect (SDP) mode.
Once enabled, SDP forces the MCU to “unlock”
the EEPROM before altering its contents, much
like Flash memory programming.
Writing a Byte to EEPROM. A write operation is
initiated when an EEPROM select signal (EESi) is
true and the write strobe signal (WR) into the PSD
is true. If the PSD detects no additional writes with-
in 120µsec, an internal storage operation is initiat-
ed. Internal storage to EEPROM memory
technology typically takes a few milliseconds to
complete.
The status of the write operation is obtained by the
MCU reading the Data Polling or Toggle bits (as
detailed in section entitled READ, page 22), or the
Ready/Busy output pin (section Ready/Busy Pin
(PC3), page 18).
Keep in mind that the MCU does not need to erase
a location in EEPROM before writing it. Erasure is
performed automatically as an internal process.
Writing a Page to EEPROM. Writing data to EE-
PROM using page mode is more efficient than
writing one byte at a time. The PSD EEPROM has
a 64 byte volatile buffer that the MCU may fill be-
fore an internal EEPROM storage operation is ini-
tiated. Page mode timing approaches a 64:1
advantage over the time it takes to write individual
bytes.
To invoke page mode, the MCU must write to EE-
PROM locations within a single page, with no
more than 120µs between individual byte writes. A
single page means that address lines A14 to A6
must remain constant. The MCU may write to the
64 locations on a page in any order, which is de-
termined by address lines A5 to A0. As soon as
120µs have expired after the last page write, the
internal EEPROM storage process begins and the
MCU checks programming status. Status is
checked the same way it is for byte writes, de-
scribed above.
Note: Be aware that if the upper address bits (A14
to A6) change during page write operations, loss
of data may occur. Ensure that all bytes for a given
page have been successfully stored in the EE-
PROM before proceeding to the next page. Cor-
rect management of MCU interrupts during
EEPROM page write operations is essential.
EEPROM Software Data Protect (SDP). The
SDP feature is useful for protecting the contents of
EEPROM from inadvertent write cycles that may
occur during uncontrolled MCU bus conditions.
These may happen if the application software gets
lost or when VCC is not within normal operating
range.
Instructions from the MCU are used to enable and
disable SDP mode (see Table 8., page 20). Once
enabled, the MCU must write an instruction se-
quence to EEPROM before writing data (much like
writing to Flash memory). SDP mode can be used
for both byte and page writes to EEPROM. The
device will remain in SDP mode until the MCU is-
sues a valid SDP disable instruction.
PSD devices are shipped with SDP mode dis-
abled. However, within PSDsoft Express, SDP
mode may be enabled as part of programming the
device with a device programmer (PSDpro).
To enable SDP mode at run time, the MCU must
write three specific data bytes at three specific
memory locations, as shown in Figure 7., page 25.
Any further writes to EEPROM when SDP is set
will require this same sequence, followed by the
byte(s) to write. The first SDP enable sequence
can be followed directly by the byte(s) to be writ-
ten.
To disable SDP mode, the MCU must write specif-
ic bytes to six specific locations, as shown in Fig-
ure 8., page 26.
The MCU must not be executing code from EE-
PROM when these instructions are invoked. The
MCU must be operating from some other memory
when enabling or disabling SDP mode.
The state of SDP mode is not changed by power
on/off sequences (nonvolatile). When either the
SDP enable or SDP disable instructions are is-
sued from the MCU, the MCU must use the Toggle
bit (status bit DQ6) or the Ready/Busy output pin
to check programming status. The Ready/Busy
output is driven low from the first write of AAh @
555h until the completion of the internal storage
sequence. Data Polling (status bit DQ7) is not sup-
ported when issuing the SDP enable or SDP dis-
able commands.
Note: Using the SDP sequence (enabling, dis-
abling, or writing data) is initiated when specific
bytes are written to addresses on specific “pages”
of EEPROM memory, with no more than 120µs
between WRITES. The addresses 555h and
AAAh are located on different pages of EEPROM.
This is how the PSD distinguishes these instruc-
tion sequences from ordinary writes to EEPROM,
which are expected to be within a single EEPROM
page.
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PSD813F1A
Writing the OTP Row
Writing to the OTP row (64 bytes) can only be
done once per byte, and is enabled by an instruc-
tion. This instruction is composed of three specific
WRITE operations of data bytes at three specific
memory locations followed by the data to be
stored in the OTP row (refer to Table 8., page 20).
During the WRITE operations, address bit A6 must
be zero, while address bits A5-A0 define the OTP
Row byte to be written while any EEPROM Sector
Select signal (EESi) is active. Writing the OTP
Row is allowed only when SDP mode is not en-
abled.
Figure 7. EEPROM SDP Enable Flowcharts
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
SDP is set
Page Write
Instruction
SDP ENABLE ALGORITHM
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
Page Write
Instruction
SDP
Set
SDP
not Set
WRITE
is enabled
WRITE Data to
be Written in
any Address
Write
in Memory
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
ai09219
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Figure 8. Software Data Protection Disable Flowchart
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PSD813F1A
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. A byte
of Flash memory erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Al-
though erasing Flash memory occurs on a sector
basis, programming Flash memory occurs on a
byte basis.
The PSD main Flash and optional boot Flash re-
quire the MCU to send an instruction to program a
byte or perform an erase function (see Table
8., page 20). This differs from EEPROM, which
can be programmed with simple MCU bus write
operations (unless EEPROM SDP mode is en-
abled).
Once the MCU issues a Flash memory program or
erase instruction, it must check for the status of
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy output pin.
Data Polling
Polling on DQ7 is a method of checking whether a
Program or Erase instruction is in progress or has
completed. Figure 9 shows the Data Polling algo-
rithm.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ7 of this location becomes the compliment of
data bit 7of the original data byte to be pro-
grammed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on
DQ5. When the DQ7 matches data bit 7 of the
original data, and the Error bit at DQ5 remains ‘0’,
then the embedded algorithm is complete. If the
Error bit at DQ5 is ‘1’, the MCU should test DQ7
again since DQ7 may have changed simultane-
ously with DQ5 (see Figure 9).
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
When using the Data Polling method after an
erase instruction, Figure 9 still applies. However,
DQ7 will be ‘0’ until the erase operation is com-
plete. A ‘1’ on DQ5 will indicate a timeout failure of
the erase operation, a ‘0’ indicates no error. The
MCU can read any location within the sector being
erased to get DQ7 and DQ5.
PSDsoft Express will generate ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figure 9. Data Polling Flowchart
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
FAIL PASS
AI01369B
DQ7
=
DATA
YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA
YES
NO
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Data Toggle
Checking the Data Toggle bit on DQ6 is a method
of determining whether a Program or Erase in-
struction is in progress or has completed. Figure
10 shows the Data Toggle algorithm.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ6 of this location will toggle each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking DQ6 and monitoring the Error bit on
DQ5. When DQ6 stops toggling (two consecutive
reads yield the same value), and the Error bit on
DQ5 remains ‘0’, then the embedded algorithm is
complete. If the Error bit on DQ5 is ‘1’, the MCU
should test DQ6 again, since DQ6 may have
changed simultaneously with DQ5 (see Figure
10).
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
When using the Data Toggle method after an
erase instruction, Figure 10 still applies. DQ6 will
toggle until the erase operation is complete. A ‘1’
on DQ5 will indicate a timeout failure of the erase
operation, a ‘0’ indicates no error. The MCU can
read any location within the sector being erased to
get DQ6 and DQ5.
PSDsoft Express will generate ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Figure 10. Data Toggle Flowchart
READ
DQ5 & DQ6
START
READ DQ6
FAIL PASS
AI01370B
DQ6
=
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
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PSD813F1A
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six write op-
erations followed by a Read operation of the status
register, as described in Table 8., page 20. If any
byte of the Bulk Erase instruction is wrong, the
Bulk Erase instruction aborts and the device is re-
set to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27. The Error bit
(DQ5) returns a ‘1’ if there has been an Erase Fail-
ure (maximum number of erase cycles have been
executed).
It is not necessary to program the array with 00h
because the PSD will automatically do this before
erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory will not accept any instructions.
Flash Sector Erase. The Sector Erase instruc-
tion uses six write operations, as described in Ta-
ble 8., page 20. Additional Flash Sector Erase
confirm commands and Flash sector addresses
can be written subsequently to erase other Flash
sectors in parallel, without further coded cycles, if
the additional instruction is transmitted in a shorter
time than the timeout period of about 100 µs. The
input of a new Sector Erase instruction will restart
the time-out period.
The status of the internal timer can be monitored
through the level of DQ3 (Erase time-out bit). If
DQ3 is ‘0’, the Sector Erase instruction has been
received and the timeout is counting. If DQ3 is ‘1’,
the timeout has expired and the PSD is busy eras-
ing the Flash sector(s). Before and during Erase
timeout, any instruction other than Erase suspend
and Erase Resume will abort the instruction and
reset the device to READ mode. It is not neces-
sary to program the Flash sector with 00h as the
PSD will do this automatically before erasing
(byte=FFh).
During a Sector Erase, the memory status may be
checked by reading status bits DQ5, DQ6, and
DQ7, as detailed in section entitled PROGRAM-
MING FLASH MEMORY, page 27.
During execution of the erase instruction, the
Flash block logic accepts only Reset and Erase
Suspend instructions. Erasure of one Flash sector
may be suspended, in order to read data from an-
other Flash sector, and then resumed.
Flash Erase Suspend
When a Flash Sector Erase operation is in prog-
ress, the Erase Suspend instruction will suspend
the operation by writing 0B0h to any address when
an appropriate Chip Select (FSi) is true. (See Ta-
ble 8., page 20). This allows reading of data from
another Flash sector after the Erase operation has
been suspended. Erase suspend is accepted only
during the Flash Sector Erase instruction execu-
tion and defaults to READ mode. An Erase Sus-
pend instruction executed during an Erase timeout
will, in addition to suspending the erase, terminate
the time out.
The Toggle Bit DQ6 stops toggling when the PSD
internal logic is suspended. The toggle Bit status
must be monitored at an address within the Flash
sector being erased. The Toggle Bit will stop tog-
gling between 0.1 µs and 15 µs after the Erase
Suspend instruction has been executed. The PSD
will then automatically be set to Read Flash Block
Memory Array mode.
If an Erase Suspend instruction was executed, the
following rules apply:
■Attempting to read from a Flash sector that
was being erased will output invalid data.
■Reading from a Flash sector that was not
being erased is valid.
■The Flash memory cannot be programmed,
and will only respond to Erase Resume and
Reset instructions (READ is an operation and
is OK).
■If a Reset instruction is received, data in the
Flash sector that was being erased will be
invalid.
Flash Erase Resume
If an Erase Suspend instruction was previously ex-
ecuted, the erase operation may be resumed by
this instruction. The Erase Resume instruction
consists of writing 030h to any address while an
appropriate Chip Select (FSi) is true. (See Table
8., page 20.)
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FLASH AND EEPROM MEMORY SPECIFIC FEATURES
Flash Memory and EEPROM Sector Protect
Each Flash and EEPROM sector can be separate-
ly protected against Program and Erase functions.
Sector Protection provides additional data security
because it disables all program or erase opera-
tions. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Configuration program. This will
automatically protect selected sectors when the
device is programmed through the JTAG Port or a
Device Programmer. Flash and EEPROM sectors
can be unprotected to allow updating of their con-
tents using the JTAG Port or a Device Program-
mer. The microcontroller can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash
or EEPROM sector will be ignored by the device.
The Verify operation will result in a READ of the
protected data. This allows a guarantee of the re-
tention of the Protection status.
The sector protection status can be read by the
MCU through the Flash protection and PSD/EE
protection registers (CSIOP). See Table 10.
Reset
The Reset instruction resets the internal memory
logic state machine in a few milliseconds. Reset is
an instruction of either one write operation or three
write operations (refer to Table 8., page 20).
Table 10. Sector Protection/Security Bit Definition – Flash Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot 1 = Flash <i> is write protected.
Sec<i>_Prot 0 = Flash <i> is not write protected.
Table 11. Sector Protection/Security Bit Definition – PSD/EE Protection Register
Note: 1. Bit Definitions:
Sec<i>_Prot 1 = EEPROM Boot Sector <i> is write protected.
Sec<i>_Prot 0 = EEPROM Boot Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The
SRAM is enabled when RS0 the SRAM chip select
output from the DPLD is high. RS0 can contain up
to two product terms, allowing flexible memory
mapping.
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
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PSD813F1A
MEMORY SELECT SIGNALS
The main Flash (FSi), EEPROM (EESi), and
SRAM (RS0) memory select signals are all out-
puts of the DPLD. They are setup by entering
equations for them in PSDsoft Express. The fol-
lowing rules apply to the equations for the internal
chip select signals:
1. Flash memory and EEPROM sector select
signals must not be larger than the physical
sector size.
2. Any main Flash memory sector must not be
mapped in the same memory space as
another Flash sector.
3. An EEPROM sector must not be mapped in
the same memory space as another EEPROM
sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not overlap.
5. An EEPROM sector may overlap a main Flash
memory sector. In case of overlap, priority will
be given to the EEPROM.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority will
be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, EES0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 will always ac-
cess the SRAM. Any address in the range of EES0
greater than 87FFh (and less than 9FFFh) will au-
tomatically address EEPROM segment 0. Any ad-
dress greater than 9FFFh will access the Flash
memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EE-
PROM segment 0 can not be accessed in this ex-
ample. Also note that an equation that defined FS1
to anywhere in the range of 8000h to BFFFh would
not be valid.
Figure 11 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level.
Components on the same level must not overlap.
Level one has the highest priority and level 3 has
the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of microcon-
trollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have
separate address spaces for code memory (se-
lected using PSEN) and data memory (selected
using RD). Any of the memories within the PSD
can reside in either space or both spaces. This is
controlled through manipulation of the VM register
that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the microcontroller so that memory
mapping can be changed on-the-fly. For example,
I may wish to have SRAM and Flash in Data
Space at boot, and EEPROM in Program Space at
boot, and later swap EEPROM and Flash. This is
easily done with the VM register by using PSDsoft
Express to configure it for boot up and having the
microcontroller change it when desired. Table 12
describes the VM Register.
Figure 11. Priority Level of Memory and I/O
Components
Table 12. VM Register
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
EEPROM Memory
Highest Priority
Lowest Priority
Level 3
Flash Memory
AI09221
Bit 7
PIO_EN Bit 6 Bit 5 Bit 4
FL_Data
Bit 3
EE_Data
Bit 2
FL_Code
Bit 1
EE_Code
Bit 0
SRAM_Code
0 = disable
PIO mode not used not used
0 = RD can’t
access
Flash
memory
0 = RD can’t
access EEPROM
0 = PSEN
can’t access
Flash
memory
0 = PSEN can’t
access EEPROM
0 = PSEN
can’t access
SRAM
1= enable
PIO mode not used not used
1 = RD
access
Flash
memory
1 = RD access
EEPROM
1 = PSEN
access
Flash
memory
1 = PSEN
access EEPROM
1 = PSEN
access
SRAM
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Separate Space Modes
Code memory space is separated from data mem-
ory space. For example, the PSEN signal is used
to access the program code from the Flash Mem-
ory, while the RD signal is used to access data
from the EEPROM, SRAM and I/O Ports. This
configuration requires the VM register to be set to
0Ch. See Figure 12.
Combined Space Modes
The program and data memory spaces are com-
bined into one space that allows the main Flash
Memory, EEPROM, and SRAM to be accessed by
either PSEN or RD. For example, to configure the
main Flash memory in combined space mode, bits
2 and 4 of the VM register are set to “1” (see Figure
13).
Figure 12. 80C31 Memory Modes - Separate Space
Figure 13. 80C31 Memory Mode - Combined Space
Flash
Memory
DPLD EEPROM
Memory
SRAM
RS0
EES0-EES3
FS0-FS7 CS CSCS
OE OE
RD
PSEN
OE
AI09222
Flash
Memory
DPLD EEPROM
Memory
SRAM
RS0
EES0-EES3
FS0-FS7
RD
CS CSCS
RD
OE OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI09223
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PSD813F1A
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the microcontroller by a factor of up to
256. The contents of the register can also be read
by the microcontroller. The outputs of the Page
Register (PGR0-PGR7) are inputs to the DPLD
decoder and can be included in the Flash Memory,
EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 14 shows the Page Register. The eight flip
flops in the register are connected to the internal
data bus D0-D7. The microcontroller can write to
or read from the Page Register. The Page Regis-
ter can be accessed at address location CSIOP +
E0h.
Figure 14. Page Register
RESET
D0-D7
R/W
D0 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3 Flash DPLD
AND
Flash CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI09224
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PLD’S
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the sections entitled DE-
CODE PLD (DPLD) and COMPLEX PLD (CPLD).
Figure 15., page 35 shows the configuration of the
PLDs.
The DPLD performs address decoding for internal
and external components, such as memory, regis-
ters, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output macrocells (OMCs), 24 Input macrocells
(IMCs), and the AND array. The CPLD can also be
used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 13.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Setting the Turbo mode bit to off (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turbo-off
mode increases propagation delays while reduc-
ing power consumption. See the section entitled
POWER MANAGEMENT, page 64, on how to set
the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns. Each
of the two PLDs has unique characteristics suited
for its applications. They are described in the fol-
lowing sections.
Table 13. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
Input Source Input Name
Number
of
Signals
MCU Address Bus1A15-A0 16
MCU Control Signals CNTL2-CNTL0 3
Reset RST 1
Power-down PDN 1
Port A Input
Macrocells PA7-PA0 8
Port B Input
Macrocells PB7-PB0 8
Port C Input
Macrocells PC7-PC0 8
Port D Inputs PD2-PD0 3
Page Register PGR7-PGR0 8
Macrocell AB
Feedback
MCELLAB.FB7-
FB0 8
Macrocell BC
Feedback
MCELLBC.FB7-
FB0 8
EEPROM Program
Status Bit Ready/Busy 1
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PSD813F1A
Figure 15. PLD Diagram
PLD INPUT BUS
8
INPUT MACROCELL & INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
EEPROM SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
JTAG SELECT
CPLD
PT
ALLOC.
MACROCELL
ALLOC.
MCELLAB
MCELLBC
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
24 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
FLASH MEMORY SELECTS
3PORT D INPUTS
TO PORT A OR B
TO PORT B OR C
DATA
BUS
8
8
8
4
1
1
2
1
EXTERNAL CHIP SELECTS
TO PORT D
3
73
16
73
24
OUTPUT MACROCELL FEEDBACK
AI09225
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DECODE PLD (DPLD)
The DPLD, shown in Figure 16, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■8 sector selects for the main Flash memory
(three product terms each)
■4 sector selects for the EEPROM (three
product terms each)
■1 internal SRAM select signal (two product
terms)
■1 internal CSIOP (PSD configuration register)
select signal
■1 JTAG select signal (enables JTAG on Port
C)
■2 internal peripheral select signals (peripheral
I/O mode).
Figure 16. DPLD Logic Array
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I /O PORTS (PORT A,B,C)
(8)
PGR0 -PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]
(1)
(3)
(3)
PD[2:0] (ALE,CLKIN,CSI)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 FLASH MEMORY
SECTOR SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
EES 0
EES 1
EES 2
EES 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
JTAGSEL
AI09226
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
1
EEPROM
SELECTS
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PSD813F1A
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate 3 external chip selects,
routed to Port D.
Although external chip selects can be produced by
any Output Macrocell, these three external chip
selects on Port D do not consume any Output
macrocells.
As shown in Figure 15., page 35, the CPLD has
the following blocks:
■24 Input macrocells (IMCs)
■16 Output macrocells (OMCs)
■Macrocell Allocator
■Product Term Allocator
■AND array capable of generating up to 137
product terms
■Four I/O ports.
Each of the blocks are described in the subsec-
tions that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the microcon-
troller. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND logic array as required in
most standard PLD macrocell architectures.
Figure 17. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
MUX
MUX
MUX MUX
D
D
Q
Q
Q
G
D
QD
WR
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
COMB.
/REG
SELECT MACROCELL
TO
I/O PORT
ALLOC.
CPLD
OUTPUT
TO OTHER I/O PORTS
PLD INPUT BUSPLD INPUT BUS
MCU ADDRESS / DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND ARRAY
CPLD OUTPUT
I/O PIN
AI02874
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Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator will assign it to either Port
A or B. The same is true for a McellBC output on
Port B or C. Table 14 shows the macrocells and
Port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 18., page 40. As shown in the fig-
ure, there are native product terms available from
the AND array, and borrowed product terms avail-
able (if unused) from other OMCs. The polarity of
the product term is controlled by the XOR gate.
The OMC can implement either sequential logic,
using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a Port pin and has a feedback path to the
AND array inputs.
The flip-flop in the OMC can be configured as a D,
T, JK, or SR type in the PSDabel program. The
flip-flop’s clock, preset, and clear inputs may be
driven from a product term of the AND array. Alter-
natively, the external CLKIN signal can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of the clock input. The
preset and clear are active-high inputs. Each clear
input can use up to two product terms.
Table 14. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment Native Product Terms Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
McellAB0 Port A0, B0 3 6 D0
McellAB1 Port A1, B1 3 6 D1
McellAB2 Port A2, B2 3 6 D2
McellAB3 Port A3, B3 3 6 D3
McellAB4 Port A4, B4 3 6 D4
McellAB5 Port A5, B5 3 6 D5
McellAB6 Port A6, B6 3 6 D6
McellAB7 Port A7, B7 3 6 D7
McellBC0 Port B0, C0 4 5 D0
McellBC1 Port B1, C1 4 5 D1
McellBC2 Port B2, C2 4 5 D2
McellBC3 Port B3, C3 4 5 D3
McellBC4 Port B4, C4 4 6 D4
McellBC5 Port B5, C5 4 6 D5
McellBC6 Port B6, C6 4 6 D6
McellBC7 Port B7, C7 4 6 D7
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PSD813F1A
Product Term Allocator
The CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and place product terms from one macro-
cell to another. The following list summarizes how
product terms are allocated:
■McellAB0-McellAB7 all have three native
product terms and may borrow up to six more
■McellBC0-McellBC3 all have four native
product terms and may borrow up to five more
■McellBC4-McellBC7 all have four native
product terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which will consume other Output
Macrocells (OMC). If external product terms are
used, extra delay will be added for the equation
that required the extra product terms.
This is called product term expansion. PSDsoft
Express will perform this expansion as needed.
Loading and Reading the Output Macrocells
(OMC). The OMCs occupy a memory location in
the MCU address space, as defined by the CSIOP
(refer to the I/O section). The flip-flops in each of
the 16 OMCs can be loaded from the data bus by
a microcontroller. Loading the OMCs with data
from the MCU takes priority over internal func-
tions. As such, the preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the OMCs on the trailing
edge of the WR signal (edge loading) or during the
time that the WR signal is active (level loading).
The method of loading is specified in PSDsoft Ex-
press Configuration.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight OMCs. The Mask Registers can be
used to block the loading of data to individual
OMCs. The default value for the Mask Registers is
00h, which allows loading of the OMCs. When a
given bit in a Mask Register is set to a ‘1’, the MCU
will be blocked from writing to the associated
OMC. For example, suppose McellAB0-3 are be-
ing used for a state machine. You would not want
a MCU write to McellAB to overwrite the state ma-
chine registers. Therefore, you would want to load
the Mask Register for McellAB (Mask Macrocell
AB) with the value 0Fh.
The Output Enable of the OMC
The OMC can be connected to an I/O port pin as
a PLD output. The output enable of each Port pin
driver is controlled by a single product term from
the AND array, ORed with the Direction Register
output. The pin is enabled upon power up if no out-
put enable equation is defined and if the pin is de-
clared as a PLD output in PSDsoft Express.
If the OMC output is declared as an internal node
and not as a Port pin output in the PSDabel file,
then the Port pin can be used for other I/O func-
tions. The internal node feedback can be routed as
an input to the AND array.
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Figure 18. CPLD Output Macrocell
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND ARRAY
PLD INPUT BUS
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PRDIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
MACROCELL
ALLOCATOR
INTERNAL DATA BUS D[7:0]
DIRECTION
REGISTER
CLEAR (.RE)
PROGRAMMABLE
FF (D/T/JK /SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI02875B
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PSD813F1A
Input Macrocells (IMC)
The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in Figure 19., page 42. The IMCs are individually
configurable, and can be used as a latch, register,
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port in-
puts 3-0 can be controlled by one product term
and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions written in PSDabel (see Application Note 55).
Outputs of the IMCs can be read by the MCU via
the IMC buffer. See the I/O Port section on how to
read the IMCs.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication applications where two proces-
sors pass data back and forth through a common
mailbox. Figure 20., page 43 shows a typical con-
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A IMCs and
the Master can then read the IMCs directly.
Note that the “Slave-Read” and “Slave-wr” signals
are product terms that are derived from the Slave
MCU inputs RD, WR, and Slave_CS.
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Figure 19. Input Macrocell
OUTPUT
MACROCELLS BC
AND
MACROCELL AB
PT
PT
FEEDBACK
AND ARRAY
PLD INPUT BUS
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS D[7:0]
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH INPUT MACROCELL
ENABLE (.OE)
D FF
INPUT MACROCELL _ RD
AI02876B
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PSD813F1A
Figure 20. Handshaking Communication Using Input Macrocells
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVE–WR
SLAVE – CS
MCU-WR
D[7:0]
D[7:0]
CPLD DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVE–READ
SLAVE
MCU
RD
WR
AI02877C
PSD
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MCU BUS INTERFACE
The “no-glue logic” PSD MCU Bus Interface block
can be directly connected to most popular MCUs
and their control signals.
Key 8-bit MCUs, with their bus types and control
signals, are shown in Table 15. The interface type
is specified using the PSDsoft Express Configura-
tion.
Table 15. MCUs and their Control Signals
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
MCU Data Bus
Width CNTL0 CNTL1 CNTL2 PC7 PD02ADIO0 PA3-PA0 PA7-PA3
8031 8 WR RD PSEN (Note 1)ALE A0 (Note 1)(Note
1)
80C51XA 8 WR RD PSEN (Note 1)ALE A4 A3-A0 (Note 1)
80C251 8 WR PSEN (Note 1)(Note
1)ALE A0 (Note 1)(Note
1)
80C251 8 WR RD PSEN (Note 1)ALE A0 (Note 1)(Note
1)
80198 8 WR RD (Note 1)(Note
1)ALE A0 (Note 1)(Note
1)
68HC11 8 R/W E(Note 1)(Note
1)AS A0 (Note 1)(Note
1)
68HC912 8 R/W E(Note 1)DBE AS A0 (Note 1)(Note
1)
Z80 8 WR RD (Note 1)(Note
1)(Note
1)A0 D3-D0 D7-D4
Z8 8 R/W DS (Note 1)(Note
1)AS A0 (Note 1)(Note
1)
68330 8 R/W DS (Note 1)(Note
1)AS A0 (Note 1)(Note
1)
M37702M2 8 R/W E(Note 1)(Note
1)ALE A0 D3-D0 D7-D4
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PSD813F1A
PSD Interface to a Multiplexed 8-Bit Bus
Figure 21 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port A or
B. The PSD drives the ADIO data bus only when
one of its internal resources is accessed and Read
Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, Ports A, B, C, or
D may be used as additional address inputs.
Figure 21. An Example of a Typical 8-bit Multiplexed Bus Interface
MCU
WR
RD
BHE
ALE
RESET
AD[7:0]
A[15:8]
A[15:8]
A[7: 0]
ADIO
PORT
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
(OPTIONAL)
PSD
AI02878C
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PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 22 shows an example of a system using a
microcontroller with an 8-bit non-multiplexed bus
and a PSD. The address bus is connected to the
ADIO Port, and the data bus is connected to Port
A. Port A is in tri-state mode when the PSD is not
accessed by the microcontroller. Should the sys-
tem address bus exceed sixteen bits, Ports B, C,
or D may be used for additional address inputs.
Figure 22. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
MCU
WR
RD
BHE
ALE
RESET
D[7:0]
A[15:0]
A[23:16]
D[7:0]
ADIO
PORT
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
PSD
AI02879C
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PSD813F1A
Data Byte Enable Reference
Microcontrollers have different data byte orienta-
tions. The following table shows how the PSD in-
terprets byte/word operations in different bus
WRITE configurations. Even-byte refers to loca-
tions with address A0 equal to zero and odd byte
as locations with A0 equal to one.
Table 16. Eight-Bit Data Bus
MCU Bus Interface Examples
Figure 23 to 26 show examples of the basic con-
nections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PSD-
soft Express Configuration.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in Figure 23. The second and third configu-
rations have the same bus connection as shown in
Table 17., page 48. There is only one READ input
(PSEN) connected to the CNTL1 pin on the PSD.
The A16 connection to the PA0 pin allows for a
larger address input to the PSD. Configuration 4 is
shown in Figure 24., page 49. The RD signal is
connected to Cntl1 and the PSEN signal is con-
nected to the CNTL2.
80C31
Figure 23 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports. The ALE input (pin PD0) latches the ad-
dress.
Figure 23. Interfacing the PSD with an 80C31
BHE A0 D7-D0
X 0 Even Byte
X 1 Odd Byte
EA/VP
X1
X2
RESET
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
RD
WR
PSEN
ALE/P
TXD
RXD
RESET
29
28
27
25
24
23
22
21
30
39
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
50
49
10
9
8
7
6
5
4
3
2
52
51
PSD
80C31
AD7-AD0
AD[7:0]
21
22
23
24
25
26
27
28
17
16
29
30
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
11
10
RESET
20
19
18
17
14
13
12
11
AI02880C
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80C251
The Intel 80C251 MCU features a user-configu-
rable bus interface with four possible bus configu-
rations, as shown in Table 18., page 49.
The 80C251 has two major operating modes:
Page Mode and Non-Page Mode. In Non-Page
Mode, the data is multiplexed with the lower ad-
dress byte, and ALE is active in every bus cycle.
In Page Mode, data D[7:0] is multiplexed with ad-
dress A[15:8]. In a bus cycle where there is a Page
hit, the ALE signal is not active and only addresses
A[7:0] are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to ALE is not re-
quired. The PSD access time is measured from
address A[7:0] valid to data in valid.
Table 17. Interfacing the PSD with the 80C251, with One READ Input
Note: 1. The A16 and A17 connections are optional.
2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL 2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
A16
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
A161
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
AI02881C
A171
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PSD813F1A
Figure 24. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
Table 18. 80C251 Configurations
Configuration 80C251 READ/WRITE
Pins Connecting to PSD Pins Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
2 WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A7-A0 multiplex with D7-D0
3 WR
PSEN only
CNTL0
CNTL1
Page Mode
A15-A8 multiplex with D7-D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL 2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
PSEN
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
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80C51XA
The Philips 80C51XA microcontroller family sup-
ports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode. (shown in Figure 25).
The 80C51XA improves bus throughput and per-
formance by executing Burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 lines to fetch up to 16 bytes of code. The
PSD access time is then measured from address
A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the nor-
mal bus cycle, except the address setup and hold
time with respect to ALE does not apply.
Figure 25. Interfacing the PSD with the 80C51X, 8-bit Data Bus
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL 2(PSEN)
PD0-ALE
PD1
PD2
RESET
31
33
36
2
3
4
5
43
42
41
40
39
38
37
24
25
26
27
28
29
30
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A18
A19
A17
A15
A16
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A16
A17
A18
A19
A15
A13
A14
TXD1
T2EX
T2
T0
RST
EA/WAIT
BUSW
A1
A0/WRH
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
PSEN
RD
WRL
PC0
PC1
PC3
PC4
PC5
PC6
PC7
ALE
PSEN
RD
WR
ALE
32
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
7
9
8
16
XTAL1
XTAL2
RXD0
TXD0
RXD1
21
20
11
13
6
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
A0
A1
A2
A3
80C51XA PSD
RESET
RESET
35
17
INT0
INT1
14
10
15
PC2
AI02883C
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PSD813F1A
68HC11
Figure 26 shows an interface to a 68HC11 where
the PSD is configured in 8-bit multiplexed mode
with E and R/W settings. The DPLD can generate
the READ and WR signals for external devices.
Figure 26. Interfacing the PSD with a 68HC11
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0 (R_W)
CNTL1(E)
CNTL 2
PD0–AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A14
A15
A13
A11
A12
AD1
AD2
AD3
AD4
AD5
AD6
AD7
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
31
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
30
29
28
27
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
PSD
RESET
RESET
AD7-AD0
AD7-AD0
PC2
AI02884C
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PSD813F1A
52/111
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP address space.
The topics discussed in this section are:
■General Port architecture
■Port Operating Modes
■Port Configuration Registers (PCR)
■Port Data Registers
■Individual Port Functionality.
General Port Architecture
The general architecture of the I/O Port is shown
in Figure 27., page 53. Individual Port architec-
tures are shown in Figure 29., page 60 to Figure
32., page 63. In general, once the purpose for a
port pin has been defined, that pin will no longer be
available for other purposes. Exceptions will be
noted.
As shown in Figure 27., page 53, the ports contain
an output multiplexer whose selects are driven by
the configuration bits in the Control Registers
(Ports A and B only) and PSDsoft Express Config-
uration. Inputs to the multiplexer include the fol-
lowing:
■Output data from the Data Out Register
■Latched address outputs
■CPLD Macrocell output
■External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND array enable product term
and the Direction Register. If the enable product
term of any of the array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the microcontroller. The PDB feedback path al-
lows the microcontroller to check the contents of
the registers.
Ports A, B, and C have embedded Input Macro-
cells (IMCs). The IMCs can be configured as latch-
es, registers, or direct inputs to the PLDs. The
latches and registers are clocked by the address
strobe (AS/ALE) or a product term from the PLD
AND array. The outputs from the IMCs drive the
PLD input bus and can be read by the microcon-
troller. See the section entitled Input
Macrocell, page 42.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Ex-
press must be programmed into the device and
cannot be changed unless the device is repro-
grammed. The modes that can be changed by the
microcontroller can be done so dynamically at run-
time. The PLD I/O, Data Port, Address Input, and
Peripheral I/O modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the microcon-
troller at run-time.
Table 19., page 54 summarizes which modes are
available on each port. Table 22., page 57 shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following subsections.
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PSD813F1A
Figure 27. General I/O Port Architecture
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MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the
PSD ports to expand its own I/O ports. By setting
up the CSIOP space, the ports on the PSD are
mapped into the microcontroller address space.
The addresses of the ports are listed in Table
6., page 17.
A port pin can be put into MCU I/O mode by writing
a ‘0’ to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled Peripheral I/O
Mode, page 56. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the micro-
controller can read the port input through the Data
In buffer. See Figure 27., page 53.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equation are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells, and/or as an output from
the CPLD’s Output Macrocells. The output can be
tri-stated with a control signal. This output enable
control signal can be defined by a product term
from the PLD, or by setting the corresponding bit
in the Direction Register to ‘0.’ The corresponding
bit in the Direction Register must not be set to ‘1’ if
the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by de-
claring the port pins, and then writing an equation
assigning the PLD I/O to a port.
Address Out Mode
For microcontrollers with a multiplexed address/
data bus, Address Out Mode can be used to drive
latched addresses onto the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a ‘1’ for pins to use Address Out Mode. This
must be done by the MCU at run-time. See Table
21., page 55 for the address output pin assign-
ments on Ports A and B for various MCUs.
For non-multiplexed 8-bit bus mode, address lines
A7-A0 are available to Port B in Address Out
Mode.
Note: do not drive address lines with Address Out
Mode to an external memory device if it is intended
for the MCU to boot from the external device. The
MCU must first boot from PSD memory so the Di-
rection and Control register bits can be set.
Table 19. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Port Mode Port A Port B Port C Port D
M C U I / O Yes Ye s Ye s Ye s
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Ye s
No
No
Ye s
Ye s
Ye s
No
Ye s
No
Ye s
No
Ye s
No
No
Ye s
Ye s
Address Out Yes (A7-A0 Ye s ( A 7 - A 0 )
or (A15-A8) No No
Address In Yes Yes Yes Yes
Data Port Yes (D7-D0) No No No
Peripheral I/O Yes No No No
JTAG ISP No No Ye s 1 No
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PSD813F1A
Table 20. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.
Table 21. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
Mode Defined in
PSDabel
Defined in PSD
Configuration
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
JTAG Enable
MCU I/O Declare pins only N/A1 0
1 = output,
0 = input
(Note 2)
N/A N/A
PLD I/O Logic equations N/A N/A (Note 2)N/A N/A
Data Port (Port A) N/A Specify bus type N/A N/A N/A N/A
Address Out (Port A,B) Declare pins only N/A 1 1 (Note 2)N/A N/A
Address In
(Port A,B,C,D)
Logic equation for
Input Macrocells N/A N/A N/A N/A N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1) N/A N/A N/A PIO bit = 1 N/A
JTAG ISP (Note 3)JTAGSEL JTAG Configuration N/A N/A N/A JTAG_Enable
MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4)
8051XA (8-Bit) N/A1 Address a7-a4 Address A11-A8 N/A
80C251
(Page Mode) N/A N/A Address A11-A8 Address A15-A12
All Other
8-Bit Multiplexed Address A3-A0 Address A7-A4 Address A3-A0 Address A7-A4
8-Bit
Non-Multiplexed Bus N/A N/A Address A3-A0 Address A7-A4
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Address In Mode
For microcontrollers that have more than 16 ad-
dress lines, the higher addresses can be connect-
ed to Port A, B, C, and D. The address input can
be latched in the Input Macrocell by the address
strobe (ALE/AS). Any input that is included in the
DPLD equations for the PLD’s Flash, EEPROM, or
SRAM is considered to be an address input.
Data Port Mode
Port A can be used as a data bus port for a micro-
controller with a non-multiplexed address/data
bus. The Data Port is connected to the data bus of
the microcontroller. The general I/O functions are
disabled in Port A if the port is configured as a
Data Port.
Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-stateable, bi-directional data buffer
for the microcontroller. Peripheral I/O Mode is en-
abled by setting Bit 7 of the VM Register to a ‘1.’
Figure 28 shows how Port A acts as a bi-direction-
al buffer for the microcontroller data bus if Periph-
eral I/O Mode is enabled. An equation for PSEL0
and/or PSEL1 must be written in PSDabel. The
buffer is tri-stated when PSEL 0 or PSEL1 is not
active.
Figure 28. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0 - PA7
D0-D7
DATA BUS
AI02886
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PSD813F1A
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because ISP is not performed during normal sys-
tem operation. For more information on the JTAG
Port, see the section entitled PROGRAMMING IN-
CIRCUIT USING THE JTAG SERIAL
INTERFACE, page 71.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6., page 17. The addresses in Ta-
ble 6., page 17 are the offsets in hexadecimal from
the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h.
Control Register
Any bit reset to ‘0’ in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a ‘1’
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated
Control Register.
Table 22. Port Configuration Registers (PCR)
Note: 1. See Table 26., page 58 for Drive Register bit definition.
Register Name Port MCU Access
Control A,B WRITE/READ
Direction A,B,C,D WRITE/READ
Drive Select1A,B,C,D WRITE/READ
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Direction Register
The Direction Register, in conjunction with the out-
put enable (except for Port D), controls the direc-
tion of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corre-
sponding pin to be an output, and any bit set to ‘0’
will cause it to be an input. The default mode for all
port pins is input.
Figure 29., page 60 and Figure 30., page 61 show
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in Figure
32., page 63), the Direction Register for Port D
has only the three least significant bits active.
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
‘1.’ The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to ‘1.’ The default rate is slow slew.
Table 26 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Table 25. Port Direction Assignment Example
Table 26. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Direction Register Bit Port Pin Mode
0 Input
1 Output
Direction
Register Bit
Output Enable
P.T. Port Pin Mode
0 0 Input
0 1 Output
1 0 Output
1 1 Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 1 1 1
Drive
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port A Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D NA1NA1NA1NA1NA1Slew
Rate
Slew
Rate
Slew
Rate
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Port Data Registers
The Port Data Registers, shown in Table 27, are
used by the MCU to write data to or read data from
the ports. Table 27 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In
Port pins are connected directly to the Data In buf-
fer. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to ‘1.’ The
contents of the register can also be read back by
the MCU.
Output Macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a lo-
cation in the microcontroller’s address space. The
microcontroller can read the output of the OMCs.
If the Mask Macrocell Register bits are not set,
writing to the Macrocell loads data to the Macrocell
flip flops. See the section entitled PLD’S, page 34.
Mask Macrocell Register
Each Mask Register bit corresponds to an OMC
flip flop. When the Mask Register bit is set to a “1”,
loading data into the OMC flip flop is blocked. The
default value is “0” or unblocked.
Input Macrocells (IMC)
The IMCs can be used to latch or store external in-
puts. The outputs of the IMCs are routed to the
PLD input bus, and can be read by the microcon-
troller. Refer to the section entitled
PLD’S, page 34 for a detailed description.
Table 27. Port Data Registers
Register Name Port MCU Access
Data In A,B,C,D READ – input on pin
Data Out A,B,C,D WRITE/READ
Output Macrocell A,B,C READ – outputs of macrocells
WRITE – loading macrocell flip-flop
Mask Macrocell A,B,C WRITE/READ – prevents loading into a given
macrocell
Input Macrocell A,B,C READ – outputs of the Input Macrocells
Enable Out A,B,C READ – the output enable control of the port driver
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Enable Out
The Enable Out register can be read by the micro-
controller. It contains the output enable values for
a given port. A ‘1’ indicates the driver is in output
mode. A ‘0’ indicates the driver is in tri-state and
the pin is in input mode.
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 29. The two ports can be
configured to perform one or more of the following
functions:
■MCU I/O Mode
■CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
■CPLD Input – Via the Input Macrocells (IMC).
■Latched Address output – Provide latched
address output as per Table 21., page 55.
■Address In – Additional high address inputs
using the Input Macrocells (IMC).
■Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
■Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
■Multiplexed Address/Data port for certain
types of MCU bus interfaces.
■Peripheral Mode – Port A only
Figure 29. Port A and Port B Structure
INTERNAL DATA BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT
A OR B PIN
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI02887
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Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 30):
■MCU I/O Mode
■CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
■CPLD Input – via the Input Macrocells (IMC)
■Address In – Additional high address inputs
using the Input Macrocells (IMC).
■In-System Programming (ISP) – JTAG port
can be enabled for programming/erase of the
PSD device. (See the section entitled
PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE, page 71, for
more information on JTAG programming.)
■Open Drain – Port C pins can be configured in
Open Drain Mode
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU interfaces.
Figure 30. Port C Structure
Note: 1. ISP.
INTERNAL DATA BUS
DATA OUT
REG.
DQ
DQ
WR
WR
MCELLBC[7:0]
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD- INPUT
DIR REG.
INPUT
MACROCELL
ENABLE OUT
SPECIAL FUNCTION1
SPECIAL FUNCTION1
CONFIGURATION
BIT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT C PIN
DATA OUT
AI02888B
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Port D – Functionality and Structure
Port D has three I/O pins. See Figure 31 and Fig-
ure 32., page 63. This port does not support Ad-
dress Out mode, and therefore no Control
Register is required. Port D can be configured to
perform one or more of the following functions:
■MCU I/O Mode
■CPLD Output – External Chip Select (ECS0-
ECS2)
■CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
■Slew rate – pins can be set up for fast slew
rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■PD0 – ALE, as address strobe input
■PD1 – CLKIN, as clock input to the macrocells
flip-flops and APD counter
■PD2 – CSI, as active Low chip select input. A
High input will disable the Flash memory,
EEPROM, SRAM and CSIOP.
Figure 31. Port D Structure
INTERNAL DATA BUS
DATA OUT
REG.
DQ
DQ
WR
WR
ECS[2:0]
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI02889
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External Chip Select
The CPLD also provides three External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used to select external devices. Each External
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 32.)
Figure 32. Port D External Chip Select Signals
PLD INPUT BUS
POLARITY
BIT
PD2 PIN
PT2 ECS2
DIRECTION
REGISTER
POLARITY
BIT
PD1 PIN
PT1 ECS1
ENABLE (.OE)
ENABLE (.OE) DIRECTION
REGISTER
POLARITY
BIT
PD0 PIN
PT0 ECS0
ENABLE (.OE) DIRECTION
REGISTER
CPLD AND ARRAY
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POWER MANAGEMENT
The PSD offers configurable power saving op-
tions. These options may be used individually or in
combinations, as follows:
– All memory types in a PSD (Flash, EEPROM,
and SRAM) are built with Zero-Power
technology. In addition to using special silicon
design methodology, Zero-Power technology
puts the memories into standby mode when
address/data inputs are not changing (zero
DC current). As soon as a transition occurs on
an input, the affected memory “wakes up”,
changes and latches its outputs, then goes
back to standby. The designer does not have
to do anything special to achieve memory
standby mode when no inputs are changing—
it happens automatically.
The PLD sections can also achieve standby
mode when its inputs are not changing, as de-
scribed in the section entitled PLD Power
Management, page 66.
– Like the Zero-Power feature, the Automatic
Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The
APD will block MCU address/data signals from
reaching the memories and PLDs. This
feature is available on all PSD devices. The
APD Unit is described in more detail in the
sections entitled Automatic Power-down
(APD) Unit and Power-down Mode, page 65.
Built in logic will monitor the address strobe of
the MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
logic initiates Power Down Mode (if enabled).
Once in Power Down Mode, all address/data
signals are blocked from reaching PSD
memories and PLDs, and the memories are
deselected internally. This allows the
memories and PLDs to remain in standby
mode even if the address/data lines are
changing state externally (noise, other
devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input signals that are
changing states keeps the PLD out of standby
mode, but not the memories.
– The PSD Chip Select Input (CSI) on all
families can be used to disable the internal
memories, placing them in standby mode
even if inputs are changing. This feature does
not block any internal signals or disable the
PLDs. This is a good alternative to using the
APD logic, especially if your MCU has a chip
select output. There is a slight penalty in
memory access time when the CSI signal
makes its initial transition from deselected to
selected.
– The PMMR registers can be written by the
MCU at run-time to manage power. PSD
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 36., page 73 and Figure 37., page 73).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations.
The PSD has a Turbo Bit in the PMMR0
register. This bit can be set to disable the
Turbo Mode feature (default is Turbo Mode
on). While Turbo Mode is disabled, the PLDs
can achieve standby current when no PLD
inputs are changing (zero DC current). Even
when inputs do change, significant power can
be saved at lower frequencies (AC current),
compared to when Turbo Mode is enabled.
When the Turbo Mode is enabled, there is a
significant DC current component and the AC
component is higher.
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Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 33, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), the Power-down (PDN) signal becomes ac-
tive, and the PSD enters Power-down mode, as
discussed next.
Power-down Mode
By default, if you enable the PSD APD unit, Power
Down Mode is automatically enabled. The device
will enter Power Down Mode if the address strobe
(ALE/AS) remains inactive for fifteen CLKIN (pin
PD1) clock periods.
The following should be kept in mind when the
PSD is in Power Down Mode:
– If the address strobe starts pulsing again, the
PSD will return to normal operation. The PSD
will also return to normal operation if either the
CSI input returns low or the Reset input
returns high.
– The MCU address/data bus is blocked from all
memories and PLDs.
– Various signals can be blocked (prior to Power
Down Mode) from entering the PLDs by
setting the appropriate bits in the PMMR
registers. The blocked signals include MCU
control signals and the common clock
(CLKIN). Note that blocking CLKIN from the
PLDs will not block CLKIN from the APD unit.
– All PSD memories enter standby mode and
are drawing standby current. However, the
PLDs and I/O ports do not go into standby
mode because you don’t want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 28 for Power
Down Mode effects on PSD ports.
– Typical standby current are of the order of the
microampere (see Table 29). These standby
current values assume that there are no
transitions on any PLD input.
Table 28. Power-down Mode’s Effect on Ports
Figure 33. APD Unit
Table 29. PSD Timing and Standby Current during Power-down Mode
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
Port Function Pin Level
MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State
Mode PLD Propagation
Delay
Memory
Access Time
Access Recovery Time
to Normal Access
Typical Standby Current
5V VCC 3V VCC
Power-down Normal tPD(1) No Access tLVDV 50µA(2) 25µA(2)
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
SELECT
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For Users of the HC11 (or compatible)
The HC11 turns off its E clock when it sleeps.
Therefore, if you are using an HC11 (or compati-
ble) in your design, and you wish to use the Pow-
er-down mode, you must not connect the E clock
to CLKIN (PD1). You should instead connect an
independent clock signal to the CLKIN input
(PD1). The clock frequency must be less than 15
times the frequency of AS. The reason for this is
that if the frequency is greater than 15 times the
frequency of AS, the PSD will keep going into
Power-down mode.
Other Power Saving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the SRAM Standby and Chip Se-
lect Input (CSI, PD2) features, they are enabled by
setting bits in the PMMR0 and PMMR2 registers.
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in the PMMR0. By setting
the bit to ‘1’, the Turbo mode is disabled and the
PLDs consume Zero Power current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time will be in-
creased by 10ns after the Turbo bit is set to ‘1’
(turned off) when the inputs change at a composite
frequency of less than 15 MHz. When the Turbo bit
is set to a ‘0’ (turned on), the PLDs run at full power
and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay.
Note: Blocking MCU control signals with PMMR2
bits can further reduce PLD AC power consump-
tion.
PSD Chip Select Input (CSI, PD2)
Pin PD2 of Port D can be configured in PSDsoft
Express as the CSI input. When low, the signal se-
lects and enables the internal Flash, EEPROM,
SRAM, and I/O for READ or WRITE operations in-
volving the PSD. A high on the CSI pin will disable
the Flash memory, EEPROM, and SRAM, and re-
duce the PSD power consumption. However, the
PLD and I/O pins remain operational when CSI is
High.
Note: There may be a timing penalty when using
the CSI pin depending on the speed grade of the
PSD that you are using. See the timing parameter
tSLQV in Table 63., page 95 or Table 64., page 95.
Input Clock
The PSD provides the option to turn off the CLKIN
input to the PLD to save AC power consumption.
The CLKIN is an input to the PLD AND array and
the Output Macrocells. During Power Down Mode,
or, if the CLKIN input is not being used as part of
the PLD logic equation, the clock should be dis-
abled to save AC power. The CLKIN will be dis-
connected from the PLD AND array or the
Macrocells by setting bits 4 or 5 to a ‘1’ in PMMR0.
Figure 34. Enable Power-down Flow Chart
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
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Table 30. Power Management Mode Registers PMMR0 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Table 31. Power Management Mode Registers PMMR2 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 APD Enable
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 PLD Turbo
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Bit 4 PLD Array clk
0 = on CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
Bit 5 PLD MCell clk
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 PLD Array
CNTL0
0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
Bit 3 PLD Array
CNTL1
0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
Bit 4 PLD Array
CNTL2
0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
Bit 5 PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6 PLD Array
DBE
0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
Bit 7 X 0 Not used, and should be set to zero.
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Input Control Signals
The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, ALE, and
DBE) to the PLD to save AC power consumption.
These control signals are inputs to the PLD AND
array.
During Power Down Mode, or, if any of them are
not being used as part of the PLD logic equation,
these control signals should be disabled to save
AC power. They will be disconnected from the
PLD AND array by setting bits 2, 3, 4, 5, and 6 to
a ‘1’ in the PMMR2.
Table 32. APD Counter Operation
APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)
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RESET TIMING AND DEVICE STATUS AT RESET
Power-On Reset
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration tNLNH-PO (See Tables 67
and 68 for values) after VCC is steady. During this
period, the device loads internal configurations,
clears some of the registers and sets the Flash
memory or EEPROM into Operating mode. After
the rising edge of Reset (RESET), the PSD re-
mains in the Reset mode for an additional period,
tOPR (See Tables 67 and 68 for values), before the
first memory access is allowed.
The PSD Flash or EEPROM memory is reset to
the READ mode upon power up. The FSi and
EESi select signals along with the write strobe sig-
nal must be in the false state during power-up re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of a write strobe signal. The PSD au-
tomatically prevents write strobes from reaching
the EEPROM memory array for about 5ms (tEEH-
WL). Any Flash memory WRITE cycle initiation is
prevented automatically when VCC is below VLKO.
Warm Reset
Once the device is up and running, the device can
be reset with a much shorter pulse of tNLNH (See
Tables 67 and 68 for values). The same tOPR time
is needed before the device is operational after
warm reset. Figure 35 shows the timing of the
power on and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33., page 70 shows the I/O pin, register and
PLD status during Power On Reset, Warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the VCC ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDabel equa-
tions.
Figure 35. Reset (RESET) Timing
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
V
CC
VCC(min)
Power-On Reset Warm Reset
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Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to ‘0’ on Power-On Reset or Warm Reset.
Port Configuration Power-On Reset Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated
Register Power-On Reset Warm Reset Power-down Mode
PMMR0 and PMMR2 Cleared to ‘0’ Unchanged Unchanged
Macrocells flip-flop status Cleared to ‘0’ by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
All other registers Cleared to ‘0’ Cleared to ‘0’ Unchanged
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PSD813F1A
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG interface on the PSD can be enabled on
Port C (see Table 34., page 72). All memory
(Flash and EEPROM), PLD logic, and PSD config-
uration bits may be programmed through the
JTAG interface. A blank part can be mounted on a
printed circuit board and programmed using
JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up program and erase operations.
Note: By default, on a blank PSD (as shipped from
factory or after erasure), four pins on Port C are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLink or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller, TDO be-
comes an output and the JTAG channel is fully
functional inside the PSD. The same command
that enables the JTAG channel may optionally en-
able the two additional JTAG pins, TSTAT and
TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON will be used. When JTAG_ON is
true, the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD
is set by the designer in the PSDsoft
Express Configuration utility. This
dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-
time by writing to the PSD register,
JTAG Enable. This register is located
at address CSIOP + offset C7h. Setting
the JTAG_ENABLE bit in this register
will enable the pins for JTAG use. This
bit is cleared by a PSD reset or the
microcontroller. See Table
35., page 72 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the
PSD can be used to enable the JTAG pins.
This PT has the reserved name JTAGSEL.
Once defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when the
Port C JTAG pins are multiplexed with
other I/O signals. It is recommended to
logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. (AN1153)
The PSD supports JTAG In-System-Configuration
(ISC) commands, but not Boundary Scan. A defi-
nition of these JTAG-ISC commands and se-
quences are defined in a supplemental document
available from ST. ST’s PSDsoft Express software
tool and FlashLink JTAG programming cable im-
plement these JTAG-ISC commands. This docu-
ment is needed only as a reference for designers
who use a FlashLink to program their PSD.
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JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG pins (TMS, TCK, TDI,
and TDO). They are used to speed programming
and erase functions by indicating status on PSD
pins instead of having to scan the status out seri-
ally using the standard JTAG channel.
TERR will indicate if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal will go Low (active) when an
error condition occurs, and stay Low until an
“ISC_CLEAR” command is executed or a chip re-
set pulse is received after an “ISC-DISABLE” com-
mand. TERR does not apply to EEPROM.
TSTAT behaves the same as the Ready/Busy sig-
nal described in the section entitled Ready/Busy
Pin (PC3), page 18. TSTAT will be High when the
PSD device is in READ mode (Flash memory and
EEPROM contents can be read). TSTAT will be
Low when Flash memory programming or erase
cycles are in progress, and also when data is be-
ing written to EEPROM.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from several PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
Security, Flash memory and EEPROM
Protection
When the security bit is set, the device cannot be
read on a device programmer or through the JTAG
Port. When using the JTAG Port, only a full chip
erase command is allowed. All other program/
erase/verify commands are blocked. Full chip
erase returns the part to a non-secured blank
state. The Security Bit can be set in PSDsoft Ex-
press Configuration.
All Flash Memory and EEPROM sectors can indi-
vidually be sector protected against erasures. The
sector protect bits can be set in PSDsoft Express
Configuration.
Table 34. JTAG Port Signals
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to '1.' The PSD
Configuration Register bits are set to '0.' The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
Table 35. JTAG Enable Register
Note: The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configura-
tion bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
Port C Pin JTAG Signals Description
PC0 TMS Mode Select
PC1 TCK Clock
PC3 TSTAT Status
PC4 TERR Error Flag
PC5 TDI Serial Data In
PC6 TDO Serial Data Out
Bit 0 JTAG_Enable
0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 X 0 Not used, and should be set to zero.
Bit 4 X 0 Not used, and should be set to zero.
Bit 5 X 0 Not used, and should be set to zero.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
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PSD813F1A
AC/DC PARAMETERS
The following tables describe the AD and DC pa-
rameters of the PSD:
■DC Electrical Specification
■AC Timing Specification
PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
MCU Timing
–READ Timing
– WRITE Timing
– Peripheral Mode Timing
– Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
■In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo bit is ‘0.’
■The AC power component gives the PLD,
EEPROM and SRAM mA/MHz specification.
Figures 36 and 37 show the PLD mA/MHz as
a function of the number of Product Terms
(PT) used.
■In the PLD timing parameters, add the
required delay when Turbo bit is ‘0.'
Figure 36. PLD ICC /Frequency Consumption (5V range)
Figure 37. PLD ICC /Frequency Consumption (3V range)
0
10
20
30
40
60
70
80
90
100
110
VCC = 5V
50
010155 20 25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
PT 100%
PT 25%
AI02894
0
10
20
30
40
50
60
VCC = 3V
010155 20 25
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI03100
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Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8MHz
MCU ALE frequency (Freq ALE) = 4MHz
% Flash memory Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x 2mA/MHz x Freq PLD
+ #PT x 400µA/PT)
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4MHz
+ 0.15 x 1.5mA/MHz x 4MHz
+ 2mA/MHz x 8MHz
+ 45 x 0.4mA/PT)
= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)
= 45µA + 0.1 x 42.9
= 45µA + 4.29mA
= 4.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles. Calculation is based on IOUT =
0mA.
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PSD813F1A
Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8MHz
MCU ALE frequency (Freq ALE) = 4MHz
% Flash memory Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4MHz
+ 0.15 x 1.5mA/MHz x 4MHz
+ 24mA)
= 45µA + 0.1 x (8 + 0.9 + 24)
= 45µA + 0.1 x 32.9
= 45µA + 3.29mA
= 3.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles. Calculation is based on IOUT =
0mA.
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MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 38. Absolute Maximum Ratings
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 125 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.6 7.0 V
VCC Supply Voltage –0.6 7.0 V
VPP Device Programmer Supply Voltage –0.6 14.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
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PSD813F1A
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 39. Operating Conditions (5V devices)
Table 40. Operating Conditions (3V devices)
Table 41. AC Signal Letters for PLD Timings
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Table 42. AC Signal Behavior Symbols for PLD
Timings
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Table 43. AC Measurement Conditions
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TA
Ambient Operating Temperature (Industrial) –40 85 °C
Ambient Operating Temperature (Commercial) 0 70 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TA
Ambient Operating Temperature (Industrial) –40 85 °C
Ambient Operating Temperature (Commercial) 0 70 °C
A Address Input
C CEout Output
D Input Data
E E Input
G Internal WDOG_ON signal
I Interrupt Input
L ALE Input
N Reset Input or Output
P Port Signal Output
Q Output Data
RWR
, UDS, LDS, DS, IORD, PSEN Inputs
S Chip Select Input
TR/W
Input
W Internal PDN Signal
M Output Macrocell
tTime
L Logic Level Low or ALE
H Logic Level High
VValid
X No Longer a Valid Logic Level
Z Float
PW Pulse Width
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
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Table 44. Capacitance
Note: 1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 38. AC Measurement I/O Waveform Figure 39. AC Measurement Load Circuit
Figure 40. Switching Waveforms – Key
Table 45. DC Characteristics (5V devices)
Symbol Parameter Test Condition Typ.2Max. Unit
CIN Input Capacitance (for input pins) VIN = 0V 46
pF
COUT Output Capacitance (for input/
output pins) VOUT = 0V 812
pF
CVPP Capacitance (for CNTL2/VPP)V
PP = 0V 18 25 pF
3.0V
0V
Test Point 1.5V
AI03103b
Device
Under Test
2.01 V
195 Ω
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
Symbol Parameter Test Condition (in addition
to those in Table 39)Min. Typ. Max. Unit
VIH Input High Voltage 4.5V < VCC < 5.5V 2VCC +0.5 V
VIL Input Low Voltage 4.5V < VCC < 5.5V –0.5 0.8 V
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON'T CARE
OUTPUTS ONLY
STEADY OUTPUT
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
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PSD813F1A
Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 36., page 73 for the PLD current calculation.
5. IOUT = 0mA
Table 46. DC Characteristics (3V devices)
VIH1 Reset High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 2.5 4.2 V
VOL Output Low Voltage
IOL = 20µA, VCC = 4.5V 0.01 0.1 V
IOL = 8mA, VCC = 4.5V 0.25 0.45 V
VOH Output High Voltage
IOH = –20µA, VCC = 4.5V 4.4 4.49 V
IOH = –2mA, VCC = 4.5V 2.4 3.9 V
ISB Standby Supply Current
for Power-down Mode CSI >VCC –0.3V (Notes 2,3)50 200 µA
ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VOUT < VCC –10 ±5 10 µA
ICC (DC)
(Note 5)
Operating
Supply
Current
ZPLD Only
ZPLD_TURBO = Off,
f = 0MHz (Note 5)0mA
ZPLD_TURBO = On,
f = 0MHz 400 700 µA/PT
Flash memory
or EEPROM
During Flash memory or
EEPROM WRITE/Erase
Only
15 30 mA
Read only, f = 0MHz 0 0 mA
SRAM f = 0MHz 0 0 mA
ICC (AC)
(Note 5)
ZPLD AC Adder See Figure
36, note 4
Flash memory or EEPROM AC
Adder 2.5 3.5 mA/
MHz
SRAM AC Adder 1.5 3.0 mA/
MHz
Symbol Parameter Conditions Min. Typ. Max. Unit
VIH High Level Input Voltage 3.0V < VCC < 3.6V 0.7VCC VCC +0.5 V
VIL Low Level Input Voltage 3.0V < VCC < 3.6V –0.5 0.8 V
VIH1 Reset High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
Symbol Parameter Test Condition (in addition
to those in Table 39)Min. Typ. Max. Unit
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Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal PD is active.
3. IOUT = 0mA
Figure 41. Input to Output Disable / Enable
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 1.5 2.2 V
VOL Output Low Voltage
IOL = 20µA, VCC = 3.0V 0.01 0.1 V
IOL = 4mA, VCC = 3.0V 0.15 0.45 V
VOH Output High Voltage
IOH = –20µA, VCC = 3.0V 2.9 2.99 V
IOH = –1mA, VCC = 3.0V 2.7 2.8 V
ISB Standby Supply Current
for Power-down Mode CSI >VCC –0.3V (Notes 2)25 100 µA
ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VIN < VCC –10 ±5 10 µA
ICC (DC)
(Note 3)
Operating
Supply
Current
ZPLD Only
ZPLD_TURBO = Off,
f = 0MHz (Note 3)0 µA/PT
ZPLD_TURBO = On,
f = 0MHz 200 400 µA/PT
Flash memory
or EEPROM
During Flash memory or
EEPROM WRITE/Erase
Only
10 25 mA
Read only, f = 0MHz 0 0 mA
SRAM f = 0MHz 0 0 mA
ICC (AC)
(Note 3)
ZPLD AC Adder See Figure 37., page 73
Flash memory or EEPROM AC
Adder 1.5 2.0 mA/
MHz
SRAM AC Adder 0.8 1.5 mA/
MHz
Symbol Parameter Conditions Min. Typ. Max. Unit
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
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PSD813F1A
Figure 42. Combinatorial Timing PLD
Table 47. CPLD Combinatorial Timing (5V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. ZPSD versions only.
Symbol Parameter Conditions
-90 -12 -15 Fast
PT
Aloc
Turbo
Off2
Slew
rate1Unit
Min Max Min Max Min Max
tPD
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
25 30 32 + 2 + 10 – 2 ns
tEA CPLD Input to CPLD
Output Enable 26 30 32 + 10 – 2 ns
tER CPLD Input to CPLD
Output Disable 26 30 32 + 10 – 2 ns
tARP CPLD Register Clear
or Preset Delay 26 30 33 + 10 – 2 ns
tARPW CPLD Register Clear
or Preset Pulse Width 20 24 29 + 10 ns
tARD CPLD Array Delay Any
macrocell 16 18 22 + 2 ns
tPD
CPLD INPUT
CPLD
OUTPUT
ai09228
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Table 48. CPLD Combinatorial Timing (3V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. ZPSD versions only.
Figure 43. Synchronous Clock Mode Timing – PLD
Symbol Parameter Conditions
-15 -20 PT
Aloc
Turbo
Off2
Slew
rate1Unit
Min Max Min Max
tPD
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
48 55 + 4 + 20 – 6 ns
tEA CPLD Input to CPLD Output
Enable 43 50 + 20 – 6 ns
tER CPLD Input to CPLD Output
Disable 43 50 + 20 – 6 ns
tARP CPLD Register Clear or
Preset Delay 48 55 + 20 – 6 ns
tARPW CPLD Register Clear or
Preset Pulse Width 30 35 + 20 ns
tARD CPLD Array Delay Any
macrocell 29 33 + 4 ns
tCH tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
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PSD813F1A
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Symbol Parameter Conditions
-90 -12 -15 Fast
PT
Aloc
Turbo
Off
Slew
rate1Unit
Min Max Min Max Min Max
fMAX
Maximum
Frequency
External
Feedback
1/(tS+tCO)30.3
026.3 23.8 MHz
Maximum
Frequency
Internal
Feedback
(fCNT)
1/(tS+tCO–10) 43.4
835.7 31.25 MHz
Maximum
Frequency
Pipelined Data
1/(tCH+tCL)50.0
041.67 33.3 MHz
tSInput Setup
Time 15 18 20 + 2 + 10 ns
tHInput Hold Time 0 0 0 ns
tCH Clock High
Time Clock Input 10 12 15 ns
tCL Clock Low Time Clock Input 10 12 15 ns
tCO Clock to Output
Delay Clock Input 18 20 22 – 2 ns
tARD CPLD Array
Delay Any macrocell 16 18 22 + 2 ns
tMIN
Minimum Clock
Period 2 tCH+tCL 20 24 30 ns
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Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Figure 44. Asynchronous Reset / Preset
Figure 45. Asynchronous Clock Mode Timing (Product Term Clock)
Symbol Parameter Conditions
-15 -20 PT
Aloc
Turbo
Off
Slew
rate1Unit
Min Max Min Max
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO)17.8 14.7 MHz
Maximum Frequency
Internal Feedback (fCNT)1/(tS+tCO–10) 19.6 17.2 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL)33.3 31.2 MHz
tSInput Setup Time 27 35 + 4 + 20 ns
tHInput Hold Time 0 0 ns
tCH Clock High Time Clock Input 15 16 ns
tCL Clock Low Time Clock Input 15 16 ns
tCO Clock to Output Delay Clock Input 35 39 – 6 ns
tARD CPLD Array Delay Any macrocell 29 33 + 4 ns
tMIN Minimum Clock Period2tCH+tCL 29 32 ns
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA tCLA
tCOA
tHAtSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
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Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
Note: 1. ZPSD versions only.
Symbol Parameter Conditions
-90 -12 -15 PT
Aloc
Turbo
Off1
Slew
Rate Unit
Min Max Min Max Min Max
fMAXA
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)26.3
223.25 20.4 MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10) 35.7
130.30 25.64 MHz
Maximum
Frequency
Pipelined
Data
1/(tCHA+tCLA)41.6
735.71 33.3 MHz
tSA Input Setup
Time 8 10 12 + 2 + 10 ns
tHA Input Hold
Time 12 14 14 ns
tCHA Clock Input
High Time 12 14 15 + 10 ns
tCLA Clock Input
Low Time 12 14 15 + 10 ns
tCOA Clock to
Output Delay 30 33 37 + 10 – 2 ns
tARDA CPLD Array
Delay Any macrocell 16 18 22 + 2 ns
tMINA Minimum
Clock Period 1/fCNTA 28 33 39 ns
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Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
Note: 1. ZPSD Versions only.
Symbol Parameter Conditions
-15 -20 PT
Aloc
Turbo
Off1
Slew
Rate Unit
Min Max Min Max
fMAXA
Maximum Frequency
External Feedback 1/(tSA+tCOA)19.2 16.9 MHz
Maximum Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10) 23.8 20.4 MHz
Maximum Frequency
Pipelined Data 1/(tCHA+tCLA)27 24.4 MHz
tSA Input Setup Time 12 13 + 4 + 20 ns
tHA Input Hold Time 15 17 ns
tCHA Clock High Time 22 25 + 20 ns
tCLA Clock Low Time 15 16 + 20 ns
tCOA Clock to Output Delay 40 46 + 20 – 6 ns
tARD CPLD Array Delay Any macrocell 29 33 + 4 ns
tMINA Minimum Clock Period 1/fCNTA 42 49 ns
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Figure 46. Input Macrocell Timing (product term clock)
Table 53. Input Macrocell Timing (5V devices)
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
2. ZPSD versions only.
Table 54. Input Macrocell Timing (3V Devices)
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
2. ZPSD Versions only.
Symbol Parameter Conditions
-90 -12 -15 PT
Aloc
Turbo
Off2Unit
Min Max Min Max Min Max
tIS Input Setup Time (Note 1)000 ns
tIH Input Hold Time (Note 1)20 22 26 + 10 ns
tINH NIB Input High Time (Note 1)12 15 18 ns
tINL NIB Input Low Time (Note 1)12 15 18 ns
tINO NIB Input to Combinatorial
Delay (Note 1)46 50 59 + 2 + 10 ns
Symbol Parameter Conditions
-15 -20 PT
Aloc
Turbo
Off2Unit
Min Max Min Max
tIS Input Setup Time (Note 1)00 ns
tIH Input Hold Time (Note 1)25 30 + 20 ns
tINH NIB Input High Time (Note 1)13 15 ns
tINL NIB Input Low Time (Note 1)13 15 ns
tINO NIB Input to Combinatorial Delay (Note 1)62 70 + 4 + 20 ns
t
INH
t
INL
t
INO
t
IH
t
IS
PT CLOCK
INPUT
OUTPUT
AI03101
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Figure 47. READ Timing
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
tAVLX tLXAX
1
tLVLX
tAVQV
tSLQV
tRLQV tRHQX
tRHQZ
tELTL
tEHEL
tRLRH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
RD
(PSEN, DS)
E
R/W
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Table 55. READ Timing (5V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 10ns to tAVQV.
Symbol Parameter Conditions
-90 -12 -15 Turbo
Off Unit
Min Max Min Max Min Max
tLVL X ALE or AS Pulse Width 20 22 28 ns
tAVLX Address Setup Time (Note 3)6 8 10 ns
tLXAX Address Hold Time (Note 3)8 9 11 ns
tAVQV Address Valid to Data Valid (Notes 3,6)90 120 150 + 10 ns
tSLQV CS Valid to Data Valid 100 135 150 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)32 35 40 ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251 (Note 2)38 42 45 ns
tRHQX RD Data Hold Time (Note 1)000 ns
tRLRH RD Pulse Width (Note 1)32 35 38 ns
tRHQZ RD to Data High-Z (Note 1)25 35 38 ns
tEHEL E Pulse Width 32 36 38 ns
tTHEH R/W Setup Time to Enable 10 13 18 ns
tELTL R/W Hold Time After Enable 0 0 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)25 28 32 ns
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Table 56. READ Timing (3V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 20ns to tAVQV.
Symbol Parameter Conditions
-15 -20 Turbo
Off Unit
MinMaxMinMax
tLVL X ALE or AS Pulse Width 26 30 ns
tAVLX Address Setup Time (Note 3)10 12 ns
tLXAX Address Hold Time (Note 3)12 14 ns
tAVQV Address Valid to Data Valid (Note 3,6)150 200 + 20 ns
tSLQV CS Valid to Data Valid 150 200 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)35 40 ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251 (Note 2)50 55 ns
tRHQX RD Data Hold Time (Note 1)00 ns
tRLRH
RD Pulse Width (also DS, LDS, UDS)4045ns
RD or PSEN Pulse Width (8031, 80251) 55 60 ns
tRHQZ RD to Data High-Z (Note 1)40 45 ns
tEHEL E Pulse Width 45 52 ns
tTHEH R/W Setup Time to Enable 18 20 ns
tELTL R/W Hold Time After Enable 0 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)35 40 ns
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Figure 48. WRITE Timing
tAVLX tLXAX
tLVLX
tAVWL
tSLWL
tWHDX
tWHAX
tELTL
tEHEL
tWLMV
tWLWH
tDVWH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
tWHPV
STANDARD
MCU I/O OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
WR
(DS)
E
R/ W
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Table 57. WRITE, Erase and Program Timing (5V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Symbol Parameter Conditions
-90 -12 -15
Unit
MinMaxMinMaxMinMax
tLVL X ALE or AS Pulse Width 20 22 28 ns
tAVLX Address Setup Time (Note 1)6 8 10 ns
tLXAX Address Hold Time (Note 1)8 9 11 ns
tAVWL Address Valid to Leading
Edge of WR (Notes 1,3)15 18 20 ns
tSLWL CS Valid to Leading Edge of WR (Note 3)15 18 20 ns
tDVWH WR Data Setup Time (Note 3)35 40 45 ns
tWHDX WR Data Hold Time (Note 3)555ns
tWLWH WR Pulse Width (Note 3)35 40 45 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)8 9 10 ns
tWHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)000ns
tWHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)30 35 38 ns
tDVMV
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes 3,5)55 60 65 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)25 28 30 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)55 60 65 ns
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Table 58. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Flash Program, WRITE and Erase Times (5V devices)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol Parameter Conditions
-15 -20
Unit
Min Max Min Max
tLVL X ALE or AS Pulse Width 26 30
tAVLX Address Setup Time (Note 1)10 12 ns
tLXAX Address Hold Time (Note 1)12 14 ns
tAVWL Address Valid to Leading
Edge of WR (Notes 1,3)20 25 ns
tSLWL CS Valid to Leading Edge of WR (Note 3)20 25 ns
tDVWH WR Data Setup Time (Note 3)45 50 ns
tWHDX WR Data Hold Time (Note 3)810ns
tWLWH WR Pulse Width (Note 3)48 53 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)12 17 ns
tWHAX2 Trailing Edge of WR to DPLD Address Invalid (Note 3,6)00ns
tWHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)45 50 ns
tDVMV Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear (Notes 3,5)90 100 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)48 55 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)90 100 ns
Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
Flash Bulk Erase1 (pre-programmed) 330s
Flash Bulk Erase (not pre-programmed) 10 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)230 ns
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Table 60. Flash Program, WRITE and Erase Times (3V devices)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Table 61. EEPROM WRITE Times (5V devices)
Note: 1. If the maximum time has elapsed between successive WRITE cycles to an EEPROM page, the transfer of this data to EEPROM
cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
Table 62. EEPROM WRITE Times (3V devices)
Note: 1. If the maximum time has elapsed between successive WRITE cycles to an EEPROM page, the transfer of this data to EEPROM
cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type.
2. These specifications are for writing a page to EEPROM cells.
Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
Flash Bulk Erase1 (pre-programmed) 330s
Flash Bulk Erase (not pre-programmed) 10 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)230 ns
Symbol Parameter Min Typ Max Unit
tEEHWL Write Protect After Power Up 5 ms
tBLC EEPROM Byte Load Cycle Timing (Note 1)0.2 120 µs
tWCB EEPROM Byte Write Cycle Time 4 10 ms
tWCP EEPROM Page Write Cycle Time (Note 2)630ms
Program/Erase Cycles (Per Sector) 10,000 cycles
Symbol Parameter Min Typ Max Unit
tEEHWL Write Protect After Power Up 5 ms
tBLC EEPROM Byte Load Cycle Timing (Note 1)0.2 120 µs
tWCB EEPROM Byte Write Cycle Time 4 10 ms
tWCP EEPROM Page Write Cycle Time (Note 2)630ms
Program/Erase Cycles (Per Sector) 10,000 cycles
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PSD813F1A
Figure 49. Peripheral I/O Read Timing
Table 63. Port A Peripheral Data Mode READ Timing (5V devices)
Table 64. Port A Peripheral Data Mode READ Timing (3V devices)
Symbol Parameter Conditions
-90 -12 -15 Turbo
Off Unit
Min Max Min Max Min Max
tAVQV–PA Address Valid to Data Valid (Note 3)40 45 45 + 10 ns
tSLQV–PA CSI Valid to Data Valid 35 40 45 + 10 ns
tRLQV–PA
RD to Data Valid (Notes 1,4)32 35 40 ns
RD to Data Valid 8031 Mode 38 42 45 ns
tDVQV–PA Data In to Data Out Valid 30 35 38 ns
tQXRH–PA RD Data Hold Time 0 0 0 ns
tRLRH–PA RD Pulse Width (Note 1)32 35 38 ns
tRHQZ–PA RD to Data High-Z (Note 1)25 28 30 ns
Symbol Parameter Conditions
-15 -20 Turbo
Off Unit
Min Max Min Max
tAVQV–PA Address Valid to Data Valid (Note 3)55 60 + 20 ns
tSLQV–PA CSI Valid to Data Valid 45 50 + 20 ns
tRLQV–PA
RD to Data Valid (Notes 1,4)40 45 ns
RD to Data Valid 8031 Mode 45 50 ns
tDVQV–PA Data In to Data Out Valid 60 65 ns
tQXRH–PA RD Data Hold Time 0 0 ns
tRLRH–PA RD Pulse Width (Note 1)36 46 ns
tRHQZ–PA RD to Data High-Z (Note 1)40 45 ns
tQXRH (PA)
tRLQV (PA)
tRLRH (PA)
tDVQV (PA)
tRHQZ (PA)
tSLQV (PA)
tAVQV (PA)
ADDRESS DATA VALID
ALE/AS
A/ D BUS
RD
DATA ON PORT A
CSI
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Figure 50. Peripheral I/O WRITE Timing
Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol Parameter Conditions
-90 -12 -15
Unit
MinMaxMinMaxMinMax
tWLQV–PA WR to Data Propagation Delay (Note 2)35 38 40 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 5)30 35 38 ns
tWHQZ–PA WR Invalid to Port A Tri-state (Note 2)25 30 33 ns
Symbol Parameter Conditions
-15 -20
Unit
Min Max Min Max
tWLQV–PA WR to Data Propagation Delay (Note 2)45 55 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 5)40 45 ns
tWHQZ–PA WR Invalid to Port A Tri-state (Note 2)33 35 ns
tDVQV (PA)
tWLQV (PA) tWHQZ (PA)
ADDRESS DATA OUT
A/ D BUS
WR
PORT A
DATA OUT
ALE/AS
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Figure 51. Reset (RESET) Timing
Table 67. Reset (RESET) Timing (5V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 68. Reset (RESET) Timing (3V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. tNLNH-PO is 10ms for devices manufactured before the rev.A.
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1150 ns
tNLNH–PO Power On Reset Active Low Time 1 ms
tOPR RESET High to Operational Device 120 ns
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1300 ns
tNLNH–PO Power On Reset Active Low Time21ms
tOPR RESET High to Operational Device 300 ns
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
V
CC
VCC(min)
Power-On Reset Warm Reset
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Figure 52. ISC Timing
Table 69. ISC Timing (5V devices)
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Symbol Parameter Conditions
-90 -12 -15
Unit
MinMaxMinMaxMinMax
tISCCF Clock (TCK, PC1) Frequency (except for
PLD) (Note 1)18 16 14 MHz
tISCCH Clock (TCK, PC1) High Time (except for
PLD) (Note 1)26 29 31 ns
tISCCL Clock (TCK, PC1) Low Time (except for
PLD) (Note 1)26 29 31 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)222MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 240 240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 240 240 ns
tISCPSU ISC Port Set Up Time 8 10 10 ns
tISCPH ISC Port Hold Up Time 5 5 5 ns
tISCPCO ISC Port Clock to Output 23 24 25 ns
tISCPZV ISC Port High-Impedance to Valid Output 23 24 25 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 23 24 25 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
ISCCL
t
ISCPH
t
ISCPSU
t
ISCPVZ
t
ISCPZV
t
ISCPCO
t
AI02865
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Table 70. ISC Timing (3V devices)
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Table 71. Power-down Timing (5V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Table 72. Power-down Timing (3V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Symbol Parameter Conditions
-15 -20
Unit
Min Max Min Max
tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1)10 9 MHz
tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1)45 51 ns
tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1)45 51 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)22MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 240 ns
tISCPSU ISC Port Set Up Time 13 15 ns
tISCPH ISC Port Hold Up Time 10 10 ns
tISCPCO ISC Port Clock to Output 36 40 ns
tISCPZV ISC Port High-Impedance to Valid Output 36 40 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 36 40 ns
Symbol Parameter Conditions
-90 -12 -15
Unit
MinMaxMinMaxMinMax
tLVDV ALE Access Time from Power-down 90 120 150 ns
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1) 15 * tCLCL1µs
Symbol Parameter Conditions
-15 -20
Unit
Min Max Min Max
tLVDV ALE Access Time from Power-down 150 200 ns
tCLWH Maximum Delay from APD Enable to
Internal PDN Valid Signal
Using CLKIN
(PD1) 15 * tCLCL1µs
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PACKAGE MECHANICAL
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level in-
terconnect. The category of second level intercon-
nect is marked on the package and on the inner
box label, in compliance with JEDEC Standard
JESD97.
The maximum ratings related to soldering condi-
tions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 53. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing
Note: Drawing is not to scale.
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
E
Ne
c
D2
E2
L1
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Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
Symb.
mm inches
Typ. Min. Max. Typ. Min. Max.
A 2.35 0.093
A1 0.25 0.010
A2 2.00 1.80 2.10 0.079 0.077 0.083
b 0.22 0.38 0.009 0.015
c 0.11 0.23 0.004 0.009
D 13.20 13.15 13.25 0.520 0.518 0.522
D1 10.00 9.95 10.05 0.394 0.392 0.396
D2 7.80 – – 0.307 – –
E 13.20 13.15 13.25 0.520 0.518 0.522
E1 10.00 9.95 10.05 0.394 0.392 0.396
E2 7.80 – – 0.307 – –
e 0.65 – – 0.026
L 0.88 0.73 1.03 0.035 0.029 0.041
L1 1.60 – – 0.063
α0° 7° 0° 7°
N52 52
Nd 13 13
Ne 13 13
CP 0.10 0.004
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Figure 54. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing
Note: Drawing is not to scale.
Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions
Symbol
mm inches
Typ. Min. Max. Typ. Min. Max.
A 4.19 4.57 0.165 0.180
A1 2.54 2.79 0.100 0.110
A2 – 0.91 – 0.036
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
C 0.246 0.261 0.0097 0.0103
D 19.94 20.19 0.785 0.795
D1 19.05 19.15 0.750 0.754
D2 17.53 18.54 0.690 0.730
E 19.94 20.19 0.785 0.795
E1 19.05 19.15 0.750 0.754
E2 17.53 18.54 0.690 0.730
e 1.27 – – 0.050 – –
R 0.89 – – 0.035 – –
N52 52
Nd 13 13
Ne 13 13
PLCC-B
D
E1 E
1 N
D1
CP
b
D2/E2 e
b1
A1
A
A2
D3/E3
M
L1
L
C
M1
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Figure 55. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline
Note: Drawing is not to scale.
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
E
Ne
c
D2
E2
L1
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Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data
Symb.
mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.42 1.54 0.056 0.061
A1 0.10 0.07 0.14 0.004 0.003 0.005
A2 1.40 1.36 1.44 0.055 0.054 0.057
α3.5° 0.0° 7.0° 3.5° 0.0° 7.0°
b 0.35 0.33 0.38 0.014 0.013 0.015
c 0.17 0.006
D 16.00 15.90 16.10 0.630 0.626 0.634
D1 14.00 13.98 14.03 0.551 0.550 0.552
D2 12.00 11.95 12.05 0.472 0.470 0.474
E 16.00 15.90 16.10 0.630 0.626 0.634
E1 14.00 13.98 14.03 0.551 0.550 0.552
E2 12.00 11.95 12.05 0.472 0.470 0.474
e 0.80 0.75 0.85 0.031 0.030 0.033
L 0.60 0.45 0.75 0.024 0.018 0.030
L1 1.00 0.94 1.06 0.039 0.037 0.042
CP 0.10 0.004
N64 64
Nd 16 16
Ne 16 16
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PART NUMBERING
Table 76. Ordering Information Scheme
Example: PSD8 1 3 F 1 A – 15 J 1 T
Device Type
PSD8 = 8-bit PSD with Register Logic
SRAM Capacity
1 = 16 Kbit
Flash Memory Capacity
3 = 1 Mbit (128Kb x 8)
2nd Flash Memory
1 = 256 Kbit EEPROM
Operating Voltage
blank = VCC = 4.5 to 5.5V
Speed
70 = 70ns
90 = 90ns
12 = 120ns
15 = 150ns
Package
J = ECOPACK PLCC52
M = ECOPACK PQFP52
U = ECOPACK TQFP64
Temperature Range
blank = 0 to 70°C (commercial)
1 = –40 to 85°C (industrial)
Option
T = Tape & Reel Packing
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For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
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APPENDIX A. PQFP52 PIN ASSIGNMENTS
Table 77. PQFP52 Connections (Figure 2)
Pin Number Pin Assignments
1PD2
2PD1
3PD0
4PC7
5PC6
6PC5
7PC4
8VCC
9GND
10 PC3
11 PC2
12 PC1
13 PC0
14 PA7
15 PA6
16 PA5
17 PA4
18 PA3
19 GND
20 PA2
21 PA1
22 PA0
23 AD0
24 AD1
25 AD2
26 AD3
Pin Number Pin Assignments
27 AD4
28 AD5
29 AD6
30 AD7
31 VCC
32 AD8
33 AD9
34 AD10
35 AD11
36 AD12
37 AD13
38 AD14
39 AD15
40 CNTL0
41 RESET
42 CNTL2
43 CNTL1
44 PB7
45 PB6
46 GND
47 PB5
48 PB4
49 PB3
50 PB2
51 PB1
52 PB0
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APPENDIX B. PLCC52 PIN ASSIGNMENTS
Table 78. PLCC52 Connections (Figure 3)
Pin Number Pin Assignments
1GND
2 PB5
3 PB4
4 PB3
5 PB2
6 PB1
7 PB0
8PD2
9PD1
10 PD0
11 PC7
12 PC6
13 PC5
14 PC4
15 VCC
16 GND
17 PC3
18 PC2
19 PC1
20 PC0
21 PA7
22 PA6
23 PA5
24 PA4
25 PA3
26 GND
Pin Number Pin Assignments
27 PA2
28 PA1
29 PA0
30 AD0
31 AD1
32 AD2
33 AD3
34 AD4
35 AD5
36 AD6
37 AD7
38 VCC
39 AD8
40 AD9
41 AD10
42 AD11
43 AD12
44 AD13
45 AD14
46 AD15
47 CNTL0
48 RESET
49 CNTL2
50 CNTL1
51 PB7
52 PB6
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APPENDIX C. TQFP64 PIN ASSIGNMENTS
Table 79. TQFP64 Connections (Figure 4)
Pin Number Pin Assignments
1PD2
2PD1
3PD0
4PC7
5PC6
6PC5
7PC4
8VCC
9VCC
10 GND
11 GND
12 PC3
13 PC2
14 PC1
15 PC0
16 NC
17 NC
18 NC
19 PA7
20 PA6
21 PA5
22 PA4
23 PA3
24 GND
25 GND
26 PA2
27 PA1
28 PA0
29 AD0
30 AD1
31 N/D
32 AD2
Pin Number Pin Assignments
33 AD3
34 AD4
35 AD5
36 AD6
37 AD7
38 VCC
39 VCC
40 AD8
41 AD9
42 AD10
43 AD11
44 AD12
45 AD13
46 AD14
47 AD15
48 CNTL0
49 NC
50 RESET
51 CNTL2
52 CNTL1
53 PB7
54 PB6
55 GND
56 GND
57 PB5
58 PB4
59 PB3
60 PB2
61 PB1
62 PB0
63 NC
64 NC
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REVISION HISTORY
Table 80. Document Revision History
Date Rev. Description of Revision
August-2000 1.0 Document written in WSI format.
04-Jan-03 1.1
Front page, and back two pages, in ST format, added to the PDF file. References to
Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft
Express.
06-Dec-03 2.0 Document converted to ST format. Package references corrected (Figure 1).
03-Jun-04 3.0 Document reformatted for DMS; Ordering Information corrected (Table 76); added TQFP64
package (Figure 1, 55; Table 75)
04-Aug-04 4.0 Correct connection, assignment (Figure 4; Table 79)
02-Oct-2008 5
Part number changed to PSD813F1A.
Added ECOPACK text in cover page and in section PACKAGE MECHANICAL, page 100.
Updated datasheet status to “not for new design”.
Backup battery feature removed: updated Features Summary, Table 1 (pins PC2 and PC4),
Block Diagram figure, Memory section, SRAM section, Port C – Functionality and Structure
section. Removed SRAM standby mode in POWER MANAGEMENT. Updated PC2 in Table
78. Removed VSTBY
, ISTBY
, VOH1, VDF
, and IIDLE from Table 45 and Table 46. Removed
VSTBYON timings tables.
Added 15ns speed in Table 76 Ordering information scheme.
Updated disclaimer text.
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