12-Bit ADC in 6-Lead SOT-23 AD7476-EP FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW at 600 kSPS with 3 V supplies 15 mW at 600 kSPS with 5 V supplies Wide input bandwidth 70 dB SNR at 100 kHz input frequency High speed serial interface SPI/QSPITM/MICROWIRETM/DSP compatible Standby mode: 1 A maximum 6-lead SOT-23 package VDD VIN 12-BIT SUCCESSIVEAPPROXIMATION ADC SCLK CONTROL LOGIC SDATA CS GND Military temperature range (-55C to +125C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available upon request 09224-001 AD7476-EP ENHANCED PRODUCT FEATURES Figure 1. APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems GENERAL DESCRIPTION The AD74761 is a 12-bit, high speed, low power, successive approximation ADC. The part operates from a single 2.35 V to 5.25 V power supply and features throughput rates up to 600 kSPS. The part contains a low noise, wide bandwidth, trackand-hold amplifier that can handle input frequencies in excess of 6 MHz. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK pin. Additional application and technical information can be found in the AD7476 data sheet. PRODUCT HIGHLIGHTS 1. 2. 3. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with this part. The AD7476 uses advanced design techniques to achieve very low power dissipation at high throughput rates. 1 4. 5. First 12-Bit ADC in a SOT-23 Package. High Throughput with Low Power Consumption. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput rates. Current consumption is 1 A maximum when in shutdown mode. Reference Derived from the Power Supply. No Pipeline Delay. The part features a standard successiveapproximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Protected by U.S. Patent No. 6,681,332. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. AD7476-EP TABLE OF CONTENTS Features .............................................................................................. 1 Timing Specifications ...................................................................5 Enhanced Product Features ............................................................ 1 Absolute Maximum Ratings ............................................................6 Applications....................................................................................... 1 ESD Caution...................................................................................6 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Outline Dimensions ..........................................................................9 Revision History ............................................................................... 2 Ordering Guide .............................................................................9 Specifications..................................................................................... 3 REVISION HISTORY 8/10--Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD7476-EP SPECIFICATIONS VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) S Version Unit 69 70 70 -78 -80 dB min dB min dB min dB typ dB typ -78 -78 10 30 6.5 dB typ dB typ ns typ ps typ MHz typ Offset Error 12 1.5 0.6 -0.9/+1.5 0.75 2 Gain Error 2 Bits LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUT Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 2 LOGIC OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate Test Conditions/Comments fIN = 100 kHz sine wave TA = 25C fa = 103.5 kHz, fb = 113.5 kHz fa = 103.5 kHz, fb = 113.5 kHz At 3 dB VDD = (2.35 V to 3.6 V) 1 Guaranteed no missed codes to 12 bits 0 to VDD 1 30 V A max pF typ 2.4 1.8 0.4 0.8 1 1 10 V min V min V max V max A max A typ pF max VDD - 0.2 0.4 10 10 Straight (natural) binary V min V max A max pF max ISOURCE = 200 A; VDD = 2.35 V to 5.25 V ISINK = 200 A 1.33 500 400 600 s max ns max ns max kSPS max 16 SCLK cycles Full-scale step input Sine wave input 100 kHz Rev. 0 | Page 3 of 12 VDD = 2.35 V VDD = 3 V VDD = 5 V Typically 10 nA, VIN = 0 V or VDD AD7476-EP Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down S Version Unit 2.35/5.25 V min/max 2 1 3 mA typ mA typ mA max 1.4 mA max 1 80 A max A max Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = fSAMPLEMAX 3 VDD = 2.35 V to 3.6 V, fSAMPLE = fSAMPLEMAX4 SCLK off SCLK on 15 4.2 5 3 mW max mW max W max W max VDD = 5 V, fSAMPLE = fSAMPLEMAX4 VDD = 3 V, fSAMPLE = fSAMPLEMAX4 VDD = 5 V, SCLK off VDD = 3 V, SCLK off 1 S version specifications apply as typical figures when VDD = 5.25 V. Guaranteed by characterization. 3 fSAMPLEMAX = 600 kSPS. 2 Rev. 0 | Page 4 of 12 Test Conditions/Comments AD7476-EP TIMING SPECIFICATIONS VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter fSCLK3 tCONVERT tQUIET t1 t2 t34 t44 t5 t6 t7 t85 tPOWER-UP 2 Limit at TMIN, TMAX1 3V 5V 10 10 12 12 16 x tSCLK 16 x tSCLK 50 50 10 10 10 10 20 20 40 20 70 20 0.4 x tSCLK 0.4 x tSCLK 0.4 x tSCLK 0.4 x tSCLK 10 10 10 10 25 25 1 1 Unit kHz min MHz max Description ns min ns min ns min ns max ns max ns max ns min ns min ns min ns min ns max s typ Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge, A version Data access time after SCLK falling edge, B version SCLK low pulse width SCLK high pulse width SCLK to data valid hold time SCLK falling edge to SDATA high impedance SCLK falling edge to SDATA high impedance Power-up time from full power-down 1 3 V specifications apply from VDD = 2.35 V to 3.6 V; 5 V specifications apply from VDD = 4.75 V to 5.25 V. Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 5 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. 2 200A 1.6V CL 50pF 200A IOH 09224-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 12 AD7476-EP ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Enhanced Plastic (EP Version) Storage Temperature Range Junction Temperature SOT-23 Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Reflow (10 sec to 30 sec) Pb-free Temperature Soldering Reflow ESD 1 Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V 10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -55C to +125C -65C to +150C 150C 230C/W 92C/W 235 (0/+5)C 255 (0/+5)C 3.5 kV Transient currents of up to 100 mA do not cause SCR latch-up. Rev. 0 | Page 6 of 12 AD7476-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 6 CS AD7476-EP VIN 3 5 SDATA TOP VIEW (Not to Scale) 4 SCLK 09224-003 GND 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD GND 3 4 VIN SCLK 5 SDATA 6 CS Description Power Supply Input. The VDD range for the AD7476-EP is from 2.35 V to 5.25 V. Analog Ground. Ground reference point for all circuitry on the part. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7476-EP conversion process. Data Out. Logic output. The conversion result is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476-EP consists of four leading zeros followed by the 12 bits of conversion data; this is provided MSB first. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7476-EP and framing the serial data transfer. Rev. 0 | Page 7 of 12 AD7476-EP TYPICAL PERFORMANCE CHARACTERISTICS -69.0 8192 POINT FFT fSAMPLE = 600kSPS fIN = 100kHz SINAD = 71.71dB THD = -80.88dB SFDR = -83.23dB -15 VDD = 2.35V SINAD (dB) -70.0 -55 VDD = 2.7V -70.5 -71.0 VDD = 5.25V -75 -71.5 -115 0 50 100 150 200 250 VDD = 4.75V VDD = 3.6V -72.0 -72.5 10k 300 FREQUENCY (kHz) 100k INPUT FREQUENCY (kHz) Figure 4. AD7476-EP Dynamic Performance at 600 kSPS Figure 5. AD7476-EP SINAD vs. Input Frequency at 605 kSPS Rev. 0 | Page 8 of 12 09224-009 -95 09224-005 SNR (dB) -35 SCLK = 12MHz -69.5 1M AD7476-EP OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 3.00 2.80 2.60 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.50 MAX 0.30 MIN 0.20 MAX 0.08 MIN SEATING PLANE 10 4 0 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-AB 0.55 0.45 0.35 121608-A 1.30 1.15 0.90 Figure 6. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7476SRTZ-EP-RL7 1 2 Temperature Range -55C to +125C Linearity Error (LSB)2 1.5 maximum Z = RoHS Compliant Part, # denotes RoHS compliant part maybe top or bottom marked. Linearity error refers to integral linearity error. Rev. 0 | Page 9 of 12 Package Description 6-Lead SOT-23 Package Option RJ-6 Branding C73# AD7476-EP NOTES Rev. 0 | Page 10 of 12 AD7476-EP NOTES Rev. 0 | Page 11 of 12 AD7476-EP NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09224-0-8/10(0) Rev. 0 | Page 12 of 12