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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8737I-11 is a low skew, high performance
Differential-to-3.3V LVPECL ClockGenerator/Divider. The
ICS8737I-11 has two selectable clock inputs. The CLK,
nCLK pair can acceptmost standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML,
or SSTL input levels.The clock enable is internally
synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS8737I-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
FEATURES
•Two divide by 1 differential 3.3V LVPECL outputs;
Two divide by 2 differential 3.3V LVPECL outputs
•Selectable differential CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•Maximum output frequency: 650MHz
•Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•Output skew: 75ps (maximum)
•Part-to-part skew: 300ps (maximum)
•Bank skew: Bank A - 30ps (maximum)
Bank B - 45ps (maximum)
•3.3V operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8737I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
VEE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
MR
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
VCC
QA1
nQA1
QB0
nQB0
VCC
QB1
nQB1
QA0
nQA0
QA1
nQA1
÷1
÷2
D
Q
LE
CLK_EN
CLK
nCLK
PCLK
nPCLK
MR
QB0
nQB0
QB1
nQB1
CLK_SEL
0
1
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
EE
rewoP.nipylppusevitageN
2NE_KLCrewoPpulluP
.tupnikcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.
hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW
.slevelecafretniLTTVL/SOMCVL
3LES_KLCtupnInwodlluP .stu
pniKLCPn,KLCPstceles,HGIHnehW.tupnitceleSkcolC
.slevelecafretniLTTVL/SOMCVL.stupniKLCn,KLCstceles,WOLn
ehW
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6KLCPtu
pnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevn
I
8cndesunU.tcennocoN
9RMtupnInwodlluP
sredividlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA
.delbasidsiteseR
retsaMeht,WOLnehW.teserera
.slevelecafretniLTTVL/SOMCVL
81,31,01V
CC
rewoP.snipylppusevitisoP
21,111BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,410BQ,0BQntuptuO.
slevelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnere
ffiD
02,910AQ,0AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
RMNE_KLCLES_KLCecruoSdetceleS1AQ,0AQ1AQn,0AQn1BQ,0BQ1BQn,0BQn
1X X X WOLHGIHWOLHGIH
00 0 KLCn,KLCWOL;delbasiDHGIH;d
elbasiDWOL;delbasiDHGIH;delbasiD
00 1 KLCPn,KLCPWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
01 0 KLCn,KLCdelbanEde
lbanEdelbanEdelbanE
01 1 KLCPn,KLCPdelbanEdelbanEdelbanEdelbanE
egdekcolctupnignillafdnagnisiragniwollofdelbanerod
elbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
.1erugiFninwohssa
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCe
htfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
.B3elbaTni
stupnIstuptuO edoMtuptuOottupnIytiraloP
KLCProKLCKLCPnroKLCnxAQxAQnxBQxBQn
00WOLHGIHWOLHGIHlaitnereffiDotlaitnereffiDg
nitrevnInoN
11HGIHWOLHGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHWOLHGIHlaitnereffiDotdednEelg
niSgnitrevnInoN
11ETON;desaiBHGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLHGIHWOLlaitneref
fiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpec
cAottupnIlaitnereffiDehtgniriW",noitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
Enabled
Disabled
FIGURE 1 - CLK_EN TIMING DIAGRAM
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQA0, nQA1;
nQB0, nQB1
QA0, QA1;
QB0, QB1
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP531.33.3564.3V
I
EE
tnerruCylppuSrewoP 55Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
CC
V564.3=5Aµ
KLCV
NI
V=
CC
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
CC
V564.3=051-Aµ
KLCV
NI
V,V0=
CC
V564.3=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON V
EE
5.0+V
CC
58.0-V
snoitacilppadedneelgnisroF:1ETON ,VsiKLCn,KLCrofegatlovtupnimumixameht
CC
.V3.0+
siegatlovedomnommoC:2ETONVsadenifed
HI
.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI NE_KLCV
NI
V=
CC
V564.3=5Aµ
RM,LES_KLCV
NI
V=
CC
V564.3=051Aµ
I
LI
tnerruCwoLtupnI NE_KLCV
NI
V,V0=
CC
V564.3=051-Aµ
RM,LES_KLCV
NI
V,V0=
CC
V564.3=5-Aµ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 056zHM
t
DP
1ETON;yaleDnoitagaporP KLCn,KLCIJzHM0562.18.1sn
KLCPn,KLCPIJzHM0561.17.1sn
t
)o(ks4,2ETON;wekStuptuO 57sp
t
)b(ks4ETON;wekSknaB AknaB03sp
BknaB54sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 003sp
t
R
emiTesiRtuptuOzHM05@%08ot%02003007sp
t
F
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO 740535%
.esiwrehtodetonsselnuzHM005taderusaemsretemarapl
lA
.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI V
NI
V=
CC
V564.3=051Aµ
V
NI
V=
CC
V564.3=5Aµ
I
LI
tnerruCwoLtupnI V
NI
V,V0=
CC
V564.3=5-Aµ
V
NI
V,V0=
CC
V564.3=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 3.01V
V
RMC
2,1ETON;egatloVtupnIedoMnommoCV
EE
5.1+V
CC
V
V
HO
3ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
3ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
05htiwdetanimretstuptuO:3ETON ΩVot
CC
.V2-
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PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
2V
PART-TO-PART SKEW
-1.3V ± 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
VCC
VEE
CLK,
PCLK
nCLK,
nPCLK
OUTPUT RISE/FALL TIME PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
QA0, Q1,
QB0, QB1
nQA0, nQ1,
nQB0, nQB1
VCC
VEE
t
PD
CLK, PCLK
nCLK,
nPCLK
QA0, Q1,
QB0, QB1
nQA0, nQ1,
nQB0, nQB1
t
sk(pp)
nQx
Qx
nQy
Qy
Part 1
Part 2
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
VCC
CLK_IN +
-
R1
1K
C1
0.1uF
V_REF
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and VCC = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
VCC - 2V
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
INPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8737I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8737I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 55mA = 190.6mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 120mW = 310.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.311W * 66.6°C/W = 105.7°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-PIN TSSOP, FORCED CONVECTION
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in
Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCC_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8737I-11 is: 510
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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