© INTEL CORPORATION, 1997 December 1997 Order Number: 272771-002
EMBEDDED WRITE-BACK ENHANCED
IntelDX4™ PROCESSOR
Figure 1. Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram
■Up to 100 MHz Oper ation
■Integrated Floating-Point Unit
■Speed-Multiplying Technology
■32-Bit RISC Technolog y Core
■16-Kbyte Write-Back Cache
■3.3 V Core Operation with 5 V Tolerant
I/O Buffers
■Burst Bus Cycl es
■Dynami c Bus Sizi ng for 8- and 16-bit
Data Bus Devices
■SL Technology
■Data Bus Parity Generation and Checking
■Boundary Scan (JTAG)
■3.3-Vol t Processor, 75 MHz, 25 MHz CLK
— 208-Lead Shrink Quad Flat Pack ( SQF P)
■3.3-Vol t Processor, 100 MHz, 33 MHz CLK
— 208-Lead Shrink Quad Flat Pack ( SQF P)
— 168-Pin Pin Grid Array (PGA)
■Binary Compatible with Large Software
Base
Paging
Unit
Prefetcher
32-Byte Code
Queue
2 x 16 Bytes
Code
Stream
Floating
Point Unit
Barrel
Shifter
24
Cache Unit
Burst Bus
Control
Bus Control
Write Buffers
4 x 32
64-Bit Interunit Transfer Bus
Register
File
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
32
Base/
Index
Bus
Translation
Lookaside
Buffer
20
16 Kbyte
Cache
Clock
Multiplier
Floating
Point
Register File
Control &
Protection
Test Unit
Control
ROM
Address
Drivers
CLK
Core
Clock
32
Data Bus
Transceivers
32
Request
Sequencer
Bus Size
Control
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
Bus Interface
D31-D0
A31-A2 BE3#- BE0#
ADS# W/R# D/C# M/IO# PCD
PWT RDY# LOCK# PLOCK#
BOFF# A20M# BREQ HOLD
HLDA RESET SRESET INTR
NMI SMI# SMIACT# FERR#
IGNNE# STPCLK#
BRDY# BLAST#
BS16# BS8#
KEN# FLUSH# AHOLD EADS#
CACHE# HITM# INV WB/WT#
TCK TMS TDI TDO
128
Instruction
Decode
32
Decoded
Instruction
Path
PCD
PWT
2
Physical
Address
32-Bit Data Bus
32-Bit Data Bus
Linear Address
Micro-
Instruction
Displacement Bus
PCHK# DP3-DP0
32
A3232-01
32
CLKMUL
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estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
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or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make c hanges to specification s and product descript ions at any ti me, without notice.
Designers must not rely on the absence or characteristics of an y feature s or instructio ns marked "reserved" or
"undefined." In tel reserves these for future definition and shall have no re sponsibility whatsoev er for conflicts or
incompatibilities arising from future changes to them.
The E mbedded Write-Back En hanced IntelDX4™ pro cesso r may contain design defects or errors known as
erra ta w hi ch m ay c au se th e p roduct to devi ate fr om pu b lis he d specif ic ations . C u rr en t c ha r a cte riz e d e r ra ta a r e
avai lable on r eq ue st.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1997
*Third-party brands and names are the pro per ty of their resp ective owners.
Contents
iii
EMBE DDED WRITE-BACK ENHA NCED
Intel DX4™ PROCESSOR
1.0 INTR OD U CTIO N ....... .................... ................... ................... ................... ................... ........................... ......1
1.1 Features .............................................................................................................................................1
1.2 Family Members .................................................................................................................................2
2.0 HOW TO USE THIS DOCUMENT .............................................................................................................3
3.0 PIN DESCR IP TIO NS .... .... .... .... ........... ................... ................... ................... .................... ...................... ... 3
3.1 Pin Assignme nts .................................................................................................................................3
3.2 Pin Quick Reference .........................................................................................................................16
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW .............................................................................26
4.1 CPUID Instru c tio n .. ............ ................... ........... ................... ................... ............ ............... .... ............26
4.1.1 Operation of the CPUID Instruction .......................................................................................26
4.2 Identification Afte r Reset ..................................................................................................................28
4.3 Bound a ry Scan (JT AG ) . .... ................... ................... ........... ................... .................... ........... .... .... ... .28
4.3.1 Device Identification ...............................................................................................................28
4.3.2 Boundary Scan Register Bits and Bit Order ...........................................................................29
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30
5.1 Maxi mum Ratings .............................................................................................................................30
5.2 DC Specifications .............................................................................................................................30
5.3 AC Specifications .............................................................................................................................33
5.4 Capacitive Derating Curves ..............................................................................................................40
6.0 MECHANICAL DATA ..............................................................................................................................42
6.1 Pack ag e Dimen si on s ............. ................... ........... ................... ................... ............ ....................... ....42
6.2 Pack ag e Ther mal Spec if ic ati on s .. .... .... .... ... ............ ................... ................... ............ ................... ... . 44
FIGURES
Figu r e 1. Em bedded Write-Back Enhanced IntelDX4™ Proces sor Block Diagram ................................... i
Figure 2. Packag e Diagram for 208- Lead SQF P Embedded Wr ite-Back Enhanced
Inte lD X 4™ Proc e sso r ............... ................... ............ ................... ................... ........... ............ ... ..4
Figure 3. Package Diagram for 168-Pin PGA Emb edded Writ e-Bac k Enhanced
Inte lD X 4™ Proc e sso r ............... ................... ............ ................... ................... ........... ............ ...1 0
Figu re 4. CL K Wav e form .. .... .... .... ........... ................... ................... ............ ................... ........... .... .... .... ...3 6
Figu re 5. I np ut Set up and Hold Tim in g .... .... .... ........... ................... ................... ............ ....................... ...3 6
Figu re 6. I np ut Set up and Hold Tim in g .... .... .... ........... ................... ................... ............ ....................... ...3 7
Figu re 7. P CH K# Val id Delay Tim ing ... .... ................... ............ ................... ................... ........... ........ .... ...3 7
Figu re 8. Ou tp ut Val id Delay Timin g ........ ........... .................... ........... ................... ................... ...............3 8
Figure 9. Maximum Float Delay Timing ..................................................................................................38
Figu re 10 . TC K Wav ef orm ..................... ............ ................... ................... ........... ................... .... .... .... .... ...3 9
Figure 11. Test Signal Timing Diagram ....................................................................................................39
Contents
iv
Figur e 12. Typic al Loading Delay versus Load Capacitance under Worst-Ca se Conditions
for a Low- to -Hig h Tra ns ition ................... ........... ................... ................... ............ .....................40
Figur e 13. Typic al Loading Delay versus Load Capacitance under Worst-Ca se Conditions
for a High-t o-L ow Tra ns iti on .... ... .... ................... ............ ................... ................... ........... ..........40
Figure 14. Typical Loading Delay versus Load Capacitance in Mixed Voltage System ...........................41
Figure 15 . 208-Lead SQFP Package Dimensions .................................................................................... 42
Figure 16. Principal Dimensions and Data fo r 168-Pin Grid Array Package .............................................43
TABLES
Table 1. The Embedded Write-Back Enhanced IntelDX4™ Processor Family .......................................2
Table 2. Pinout Di fferences for 208-Le ad SQFP Package ......................................................................5
Tab le 3. Pin Ass ignm en t for 20 8-L ea d SQFP Pac k age .. ............ ................... ................... ........... ............6
Table 4. Pin Cross Reference for 208-Lead SQFP Packa ge ...................................................................8
Table 5. Pinout Di fferences for 168-Pin PGA Package .........................................................................11
Tab le 6. Pin Ass ignm en t for 16 8-P in PG A Pac kage ... .... ............ ................... ................... ........... ..........12
Table 7. Pin Cross Reference for 168-Pin PGA Package ......................................................................14
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions .............................16
Table 9. Output Pins ........................................................................................................... ...................24
Table 10 . Input/Output Pins .....................................................................................................................24
Table 11 . Test Pins ..................................................................................................................................25
Table 12 . Input Pins .................................................................................................................................25
Tab le 13. CPUID In str uc tio n Des c rip tio n ... .... ............ ................... ................... ........... ................... ..........26
Table 14 . Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) ...........28
Tab le 15. Bo un dar y Scan Comp on en t Ide nti fic a tio n Cod e (Wri te-B ac k/ En ha nced Bus Mo d e) .. ... .... .... ..29
Table 16 . Absolute Maximum Ratings .....................................................................................................30
Table 17 . Operating Supply Voltages ......................................................................................................30
Table 18 . DC Specifications .....................................................................................................................31
Table 19. ICC Values ................................................................................................................................32
Table 20 . AC Characteristics ...................................................................................................................33
Table 21 . AC Specifications for the Test Access Port .............................................................................35
Table 22 . 168-Pin Ceramic PGA Package Dimensions ...........................................................................43
Table 23 . Ceramic PGA Packa ge Di mension Symb ols ...........................................................................44
Table 24. Thermal Resistance, θJA (°C/W) ............................................................................................. 45
Table 25. Thermal Resistance, θJC (°C/W) .............................. ................... ................... .........................45
Table 26. Ma x imum Tambient, TA max (°C) . .... ............ ................... ........... ................... ................... ..........45
Embedded Write-Back Enhanced IntelDX4™ Processor
1
1.0 INTRODUCTION
The embedded Write-Back Enhanced IntelDX4™
processor provides high performance to 32-bit,
embedded applications. Designed for applications
that need a fl oatin g- poin t un it, the p roces sor is idea l
for embedded designs running DOS*, Microsoft
Windows*, OS/2*, or UNIX* applications written for
the Intel architecture. Projects can be completed
quickly using the wide range of software tools,
ut il iti es , as s em b lers a nd co m pil er s th at ar e av ai la ble
for deskt op computer syst ems. Also, devel opers can
find advantages in using existing chipsets and
peripheral components in their embedded designs.
The Embedded Write-Back Enhanced IntelDX4
processor is binary compatible with the Intel386™
and earlier Intel processors. Compared with the
Intel386 processor, it provides faster execution of
many commonly-used instructions. It also provides
the benefits of an integrated, 16-Kbyte, write-back
cache for code and data. Its data bus can operate in
burst mode which provides up to 106-Mbyte-per-
second transfers for cache-line fills and instruction
prefetches.
Intel’s SL technology is incorporated in the
Embedded Write-Back Enhanced IntelDX4
processor. Utilizing Intel’s System Management
Mode (SMM) enables designers to develop energy-
efficient syst ems.
Two component packages are available:
• 168-pin Pin Grid Array (PGA)
• 208-lead Shrink Qu ad Flat Pack (SQFP)
The pr ocess or operate s at eit her two or three times
the external bus freque ncy. At two times the external
bus freque ncy the pr ocesso r operates up to 66 MHz,
(33-MHz CLK). At three times the external bus
frequency the processor operates up to 100 MHz
(33-MHz CLK).
1.1 Features
The Embedded Write-Back Enhanced IntelDX4
processor offers these features:
•32-bit RISC-Technology Core — The Embedded
Write-Back Enhanced IntelDX4 processor
performs a c omplete set of arithmetic and logical
operations on 8-, 16-, and 32-bit data types using
a full-width ALU and eight general purpose
registers.
•Single Cycle Execution — Many instructions
ex ecute in a sing le clock c y cle.
•Instr u cti on Pipe lin ing — Overl apped instruction
fetching, decoding, address translation and
execution.
•On-Chip Floating-Point Unit — Intel486™
processors support the 32-, 64-, and 80-bit formats
specified in IEE E standard 754. The u nit i s binary
compatib le with the 8087, Intel287™, Intel387™
coprocessors, and Intel OverDrive® processor.
•On-Chip Cache with Cache Consistency
Support — A 16-Kbyte internal ca che is used fo r
both da ta and instructi ons. It i s conf igur able to be
write-back or write-through on a line-by-line basis.
Th e internal cache implements a modified MESI
protocol, which is applicable to uniprocessor
sy stems. Ca che hits prov ide zero wait-state
ac ces s ti me s f or da ta wi th in t h e c ac he. Bu s ac ti vi ty
is tracke d to detect alterations in the memory
represent ed by the internal c ache. The internal
cache can be invalidated or flushed so that an
external cache controller can maintain cache
consistency.
•External Cache Control — Write-back and flush
controls for an external cache are p rovided so the
proce ssor can maintain cache co nsiste ncy.
•On-Chip Memory Management Unit — Address
management and memory space protection
mechanisms maintain the integrity of memory in a
mult ita sking an d virtua l memory e nviro nment . Bot h
memory segmentation and paging are supported.
•Burst Cycl es — Burst transfers allow a new
double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Data written from the processor to me mory
can also be burst transfers.
•Write Buffers — The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus .
2
Embedded Write-Back Enhanced IntelDX4™ Processor
•Bus Backoff — When another bu s master needs
control of the bus during a processor initiated bus
cycle, the Embedded Write-Back Enhanced
IntelDX4 proc essor floats its bus signals, then
restarts the cycle when the bus becomes available
again.
•Instruction Restart — Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memo ry. This
feat ure is important for supporting de mand-paged
v irtual memory applications.
•Dynamic Bus Sizin g — External controllers can
dynamica lly alter the effective width of the data
bus. B us wi dths of 8, 16 , or 32 bits can be used.
•Boundary Sc an (JTAG) — Boundary Scan
provides in-circuit testing of c omponents on
printed cir c uit board s . The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Po rt and Boundary Scan Archite cture.
•Enhanced Bus Mode — The definitions of some
signals have been changed t o su pp ort writ e-b ac k
c ache mode.
Intel’s SL technology provides these features:
•Intel Syst em Management Mode (SMM) — A
unique Intel architecture operating mode provides
a dedicated special purpose interrupt and address
space that can be used to implement intelligent
power management and other enhanced functions
in a manner that is completely transparent to the
oper ating system and applications sof tware.
•I/O Restart — An I/O instruction interrupted by a
System Management Interrupt (SMI#) can
automatically be restarted following the execution
of the RSM instruction.
•Sto p Cl ock — The Embedd ed Write-Ba ck
Enhanced IntelDX4 processor has a stop clock
c ontrol mechanism th at provides two low-power
s tat es: a Stop G ra nt st ate (2 0–50 mA t y pical ,
depending on input clock frequency) and a Stop
Clock state (~600 µA typical, with input clock
frequency of 0 MHz).
•Auto HALT Power Down — After the execution of
a HALT instruction, the Embedded Write-Back
Enhanced IntelDX4 processor issues a normal
Halt bus cycle and the clock input to the p roce ssor
core is automatically stopped, causing the
processor to enter the Auto HALT Power Down
s tat e (20 –50 mA typica l, depending on inpu t clock
frequency).
•Auto Idle Powe r Down — Th is f un ct io n al lo w s th e
processor to reduce th e core frequency to the bus
frequency when both the core and bus are idle.
Auto Idle Power Down is software transparent and
does not affe ct processor per formance. Auto Idle
Power Down p rovides an average power savings
of 10% and is only applicable to clock multiplied
processors.
1.2 Family Members
Table 1 shows the Embe dded Write-Back En hanced
IntelDX4 processors and briefly describes their
characteristics.
T abl e 1. The Embedded Write-Back Enhanced IntelDX4™ Processor Family
Product S upp ly Vol tag e
VCC
Maximu m
Processor
Frequency
Maximu m
Extern al Bus
Frequency Package
FC80486DX4WB75 3.3 V 75 MHz 25 MHz 208-Lead SQFP
FC80486DX4WB100 3.3 V 100 MHz 33 MHz 208-Lead SQFP
A80486DX4WB100 3.3 V 100 MHz 33 MHz 168-Pin PGA
Embedded Write-Back Enhanced IntelDX4™ Processor
3
2.0 HO W TO USE THIS DOCUMENT
For a complete set of documentation related to the
Embedded Write-Back Enhanced IntelDX4
pr oc es s or, use this docum en t in c on ju nc tio n w it h the
following reference documents:
•
Embedded Inte l486™ Pr ocessor Family
Developer’s Manual
— O rde r N o. 273 021
•
Emb edde d Intel48 6™ Processor Hardware
Reference Manual
— Order No. 273025
•
Intel486 Microprocessor Family Programmer’s
Reference Manual
— Ord er N o. 24 04 86
• Intel Ap plicat ion Note AP- 485 —
Intel Processor
Identification with the CPUID Instruction
—
Order No. 24 16 18
The information in the reference documents for the
IntelDX4 processor applies to the Embedded W rite-
Back Enhanced IntelDX4 processor. Some of the
IntelDX4 processor information is duplicated in this
document to minimize the dependence on the
reference docu ment s.
3.0 PIN DESCRIPTIONS
3.1 Pin Assignments
The following figures and tables show the pin assign-
ments of each package type for the Embedded
Write-Back Enhanced IntelDX4 processor. Tables
are provided showing the pin differences between
the Embedded Write-Back Enhanced IntelDX4
processor and other embedded Intel486 processor
products.
208-Lead SQFP - Quad Flat Pack
• Figure 2, Package Diagram for 208-Lead SQFP
Embedded Write-Back Enha nced IntelDX4™
Proce ssor (pg. 4)
• Tabl e 2, P inout Differences for 208-Lead SQFP
Package (pg. 5)
• Table 3, Pin Assignment for 208-Lead SQFP
Package (pg. 6)
• Table 4, Pin Cross Reference for 208-Lead SQFP
Package (pg. 8)
168-Pin PGA - Pin Grid Array
• Figure 3, Package Diagram for 168-Pin PGA
Embedded Write-Back Enha nced IntelDX4™
Proce ssor (pg. 10)
• Table 5, Pinout Differences for 168-Pin PGA
Pac kage (pg. 11)
• Table 6, Pin Assignment for 168-Pin PGA
Pac kage (pg. 12)
• Table 7, Pin Cross Reference for 168-Pin PGA
Pac kage (pg. 14)
Embedded Write-Back Enhanced IntelDX4™ Processor
4
Figure 2. Package Diagram for 208-Lead SQFP Em bed ded Write-Back Enhanced IntelDX4™ Processor
156
155
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121
120
119
118
117
116
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113
112
111
110
109
108
107
106
105
208-Lead SQFP
Embedded Write-Back Enhanced
IntelDX4™ Processor
Top View
1
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173
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169
168
167
166
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164
163
162
161
160
159
158
157
V
SS
LOCK#
PLOCK#
V
CC
BLAST#
ADS#
A2
V
SS
V
CC
V
SS
V
CC
A3
A4
A5
RESERVED#
A6
A7
V
CC
A8
V
SS
V
CC
A9
A10
V
CC
V
SS
V
CC
A11
V
SS
A12
V
CC
A13
A14
V
CC
V
SS
A15
A16
V
CC
A17
V
SS
V
CC
TDI
TMS
A18
A19
A20
V
CC
V
CC
A21
A22
A23
A24
V
SS
V
SS
V
CC
V
CC5
PCHK#
BRDY#
BOFF#
BS16#
BS8#
V
CC
V
SS
CLKMUL
RDY#
KEN#
V
CC
V
SS
HOLD
AHOLD
TCK
V
CC
V
CC
V
SS
V
CC
V
CC
CLK
V
CC
HLDA
W/R#
V
SS
V
CC
BREQ
BE0#
BE1#
BE2#
BE3#
V
CC
V
SS
M/IO#
V
CC
D/C#
PWT
PCD
V
CC
V
SS
V
CC
V
CC
EADS#
A20M#
RESET
FLUSH#
INTR
NMI
V
SS
V
SS
V
CC
A25
A26
A27
A28
V
CC
A29
A30
A31
V
SS
DP0
D0
D1
D2
D3
D4
V
CC
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
CC
D5
D6
V
CC
NC
D7
DP1
D8
D9
V
SS
V
CC
V
SS
D10
D11
D12
D13
V
SS
V
CC
D14
D15
V
CC
V
SS
DP2
D16
V
SS
V
CC
V
SS
V
SS
V
CC
V
SS
V
CC
V
SS
SRESET
SMIACT#
V
CC
V
SS
V
CC
HITM#
WB/WT#
SMI#
FERR#
NC
TDO
V
CC
CACHE#
INV
IGNNE#
STPCLK#
D31
D30
V
SS
V
CC
D29
D28
V
CC
V
SS
V
CC
D27
D26
D25
V
CC
D24
V
SS
V
CC
DP3
D23
D22
D21
V
SS
V
CC
NC
V
SS
V
CC
D20
D19
D18
V
CC
D17
V
SS
A3230-01
Embedded Write-Back Enhanced IntelDX4™ Processor
5
Table 2. Pinout Differences for 208-Lead SQFP Package
Pin # Embedded
Intel48 6™ SX
Processor
Embedded
IntelDX2™
Processor
Em bedded Write-Back
Enhanced IntelDX4™
Processor
3VCC1VCC VCC5
11 INC2INC CLKMUL
63 INC INC HITM#
64 INC INC WB/WT#
66 INC FERR# FERR#
70 INC INC CACHE#
71 INC INC INV
72 INC IGNNE# IGNNE#
NOTES:
1. This pin location is for the VCC5 pin on the embedded IntelDX4 proc essor. For compatibility with 3.3V processor s that
have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to
the VCC plane.
2. INC. Internal No Connect. These pins are not connected to any internal pad. However, signals are defined for the loca-
tion of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these pro-
cessors provided the purpose of each INC pin is understood before it is used.
Embedded Write-Back Enhanced IntelDX4™ Processor
6
Table 3. Pin Assignment for 208-Lead SQFP Pack age (Sheet 1 of 2)
Pin# Description Pin# Description Pin# Description Pin# Description
1V
SS 53 VSS 105 VSS 157 VSS
2V
CC 54 VCC 106 VCC 158 A24
3V
CC555 VSS 107 VSS 159 A23
4 PCHK# 56 VCC 108 D16 160 A22
5 BRDY#57V
SS 109 DP2 161 A21
6 BOFF# 58 SRESET 110 VSS 162 VCC
7 BS16# 59 SMIACT# 111 VCC 163 VCC
8BS8#60
V
CC 112 D15 164 A20
9V
CC 61 VSS 113 D14 165 A19
10 VSS 62 VCC 114 VCC 166 A18
11 CLKMUL 63 HITM# 115 VSS 167 TMS
12 RDY# 64 WB/WT# 116 D13 168 TDI
13 KEN# 65 SMI# 117 D12 169 VCC
14 VCC 66 FERR# 118 D11 170 VSS
15 VSS 67 NC1119 D10 171 A17
16 HOLD 68 TDO 120 VSS 172 VCC
17 AHOLD 69 VCC 121 VCC 173 A16
18 TCK 70 CACHE# 122 VSS 174 A15
19 VCC 71 INV 123 D9 175 VSS
20 VCC 72 IGNNE# 124 D8 176 VCC
21 VSS 73 STPCLK# 125 DP1 177 A14
22 VCC 74 D31 126 D7 178 A13
23 VCC 75 D30 127 NC1179 VCC
24 CLK 76 VSS 128 VCC 180 A12
25 VCC 77 VCC 129D6181V
SS
26 HLDA 78 D29 130 D5 182 A11
27 W/R# 79 D28 131 VCC 183 VCC
28 VSS 80 VCC 132 VSS 184 VSS
29 VCC 81 VSS 133 VCC 185 VCC
30 BREQ 82 VCC 134 VCC 186 A10
31 BE0# 83 D27 135 VSS 187 A9
32 BE1# 84 D26 136 VCC 188 VCC
33 BE2# 85 D25 137 VCC 189 VSS
34 BE3# 86 VCC 138 VSS 190 A8
35 VCC 87 D24 139 VCC 191 VCC
Embedded Write-Back Enhanced IntelDX4™ Processor
7
36 VSS 88 VSS 140 D4 192 A7
37 M/IO# 89 VCC 141 D3 193 A6
38 VCC 90 DP3 142 D2 194 RESERVED#
39 D/C# 91 D23 143 D1 195 A5
40 PWT 92 D22 144 D0 196 A4
41 PCD 93 D21 145 DP0 197 A3
42 VCC 94 VSS 146 VSS 198 VCC
43 VSS 95 VCC 147 A31 199 VSS
44 VCC 96 NC1148 A30 200 VCC
45 VCC 97 VSS 149 A29 201 VSS
46 EADS# 98 VCC 150 VCC 202 A2
47 A20M# 99 D20 151 A28 203 ADS#
48 RESET 100 D19 152 A27 204 BLAST#
49 FLUSH# 101 D18 153 A26 205 VCC
50 INTR 102 VCC 154 A25 206 PLOCK#
51 NMI 103 D17 155 VCC 207 LOCK#
52 VSS 104 VSS 156 VSS 208 VSS
NOTE:
1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other
signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)
Pin# Description Pin# Description Pin# Description Pin# Description
Embedded Write-Back Enhanced IntelDX4™ Processor
8
Table 4. Pin Cro ss R eferen ce for 208-L ead SQFP P a ckage (Sheet 1 of 2)
Address Pin # Data Pin # Control Pin # NC VCC5 VCC VSS
A2 202 D0 144 A20M# 47 67 3 2 1
A3 197 D1 143 ADS# 203 96 9 10
A4 196 D2 142 AHOLD 17 127 14 15
A5 195 D3 141 BE0# 31 19 21
A6 193 D4 140 BE1# 32 20 28
A7 192 D5 130 BE2# 33 22 36
A8 190 D6 129 BE3# 34 23 43
A9 187 D7 126 BLAST# 204 25 52
A10 186 D8 124 BOFF# 6 29 53
A11 182 D9 123 BRDY# 5 35 55
A12 180 D10 119 BREQ 30 38 57
A13 178 D11 118 BS16# 7 42 61
A14 177 D12 117 BS8# 8 44 76
A15 174 D13 116 CACHE# 70 45 81
A16 173 D14 113 CLK 24 54 88
A17 171 D15 112 CLKMUL 11 56 94
A18 166 D16 108 D/C# 39 60 97
A19 165 D17 103 DP0 145 62 104
A20 164 D18 101 DP1 125 69 105
A21 161 D19 100 DP2 109 77 107
A22 160 D20 99 DP3 90 80 110
A23 159 D21 93 EADS# 46 82 115
A24 158 D22 92 FERR# 66 86 120
A25 154 D23 91 FLUSH# 49 89 122
A26 153 D24 87 HITM# 63 95 132
A27 152 D25 85 HLDA 26 98 135
A28 151 D26 84 HOLD 16 102 138
A29 149 D27 83 IGNNE# 72 106 146
A30 148 D28 79 INTR 50 111 156
A31 147 D29 78 INV 71 114 157
D30 75 KEN# 13 121 170
D31 74 LOCK# 207 128 175
M/IO# 37 131 181
Embedded Write-Back Enhanced IntelDX4™ Processor
9
NMI 51 133 184
PCD 41 134 189
PCHK# 4 136 199
PLOCK# 206 137 201
PWT 40 139 208
RDY# 12 150
RESERVED# 194 155
RESET 48 162
SMI# 65 163
SMIACT# 59 169
SRESET 58 172
STPCLK# 73 176
TCK 18 179
TDI 168 183
TDO 68 185
TMS 167 188
WB/WT# 64 191
W/R# 27 198
200
205
Table 4. Pin Cross Reference for 208-Lead SQFP Package (S he et 2 of 2)
Address Pin # Data Pin # Control Pin # NC VCC5 VCC VSS
Embedded Write-Back Enhanced IntelDX4™ Processor
10
Figure 3. Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4™ Processor
A3231-01
D20
A
D19
B
D11
C
D22 D21 D18
D9
D
V
SS
E
D13 V
CC
DP1
F
V
SS
G
D8 V
CC
V
SS
H
V
CC5
J
D3 D5
V
SS
K
V
SS
L
V
CC
D6
V
SS
M
D2
N
V
CC
D1
D0
P
A31
Q
A29 V
SS
A28
R
A27
S
A25 A26
1
2
1
2
TCK V
SS
CLK D17 D10 D15 D12 DP2 D16 D14 D7 D4 DP0 A30 A17
V
CC
A23
33
D23 V
SS
V
CC
A19
V
SS
VOLDET
4
5
4
5
6 6
7
8
7
8
99
10
11
10
11
12 12
13 13
14 14
15
16
15
16
17 17
DP3 V
SS
V
CC
D24 D25 D27
V
SS
V
CC
D26
A21 A18 A14
A24 V
CC
V
SS
A22 A15 A12
A20
A16
A13
A9
A5 A11 V
SS
A7 A8 A10
A2 V
CC
V
SS
D29 D31 D28
V
SS
V
CC
D30
INV SMI# SRESET
RESERVED#
HITM# CACHE# SMIACT#
INC WB/WT# NC
TDI TMS FERR#
IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2# BE0# PWT D/C# LOCK# HLDA BREQ A3 A6
INTR TDO RESET BS8# RDY# BE1# M/IO# PLOCK# BLAST# A4
AHOLD EADS# BS16# BOFF# BE3# PCD W/R# PCHK# CLKMUL ADS#
ABCDEFGHJKLMNPQRS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
168-Pin PGA
Embedded Write-Back Enhanced
IntelDX4™ Processor
Pin Side View
Embedded Write-Back Enhanced IntelDX4™ Processor
11
Tab le 5. Pinout Differen ces for 168-Pin PGA P acka ge
Pin # Em be dde d Inte lDX 2 ™ Proc es so r Embedded Write-Back Enhanced
IntelDX4™ Proces sor
A10 INC INV
A12 INC HITM#
B12 INC CACHE#
B13 INC WB/WT#
J1 VCC VCC5
R17 INC CLKMUL
S4 NC VOLDET
Embedded Write-Back Enhanced IntelDX4™ Processor
12
T ab le 6. Pin As sig nm ent for 168- Pi n P GA Pack age (Sheet 1 of 2)
Pin # Description Pin # Description Pin # Description
A1 D20 D17 BOFF# P2 A29
A2 D22 E1 VSS P3 A30
A3 TCK E2 VCC P15 HLDA
A4D23E3D10P16
V
CC
A5 DP3 E15 HOLD P17 VSS
A6 D24 E16 VCC Q1 A31
A7 VSS E17 VSS Q2 VSS
A8 D29 F1 DP1 Q3 A17
A9 VSS F2 D8 Q4 A19
A10 INV F3 D15 Q5 A21
A11 VSS F15 KEN# Q6 A24
A12 HITM# F16 RDY# Q7 A22
A13 INC F17 BE3# Q8 A20
A14 TDI G1 VSS Q9 A16
A15 IGNNE# G2 VCC Q10 A13
A16 INTR G3 D12 Q11 A9
A17 AHOLD G15 STPCLK# Q12 A5
B1 D19 G16 VCC Q13 A7
B2 D21 G17 VSS Q14 A2
B3 VSS H1 VSS Q15 BREQ
B4 VSS H2 D3 Q16 PLOCK#
B5 VSS H3 DP2 Q17 PCHK#
B6 D25 H15 BRDY# R1 A28
B7 VCC H16 VCC R2 A25
B8 D31 H17 VSS R3 VCC
B9 VCC J1 VCC5 R4 VSS
B10 SMI# J2 D5 R5 A18
B11 VCC J3 D16 R6 VCC
B12 CACHE# J15 BE2# R7 A15
B13 WB/WT# J16 BE1# R8 VCC
B14 TMS J17 PCD R9 VCC
B15 NMI K1 VSS R10 VCC
B16 TDO K2 VCC R11 VCC
B17 EADS# K3 D14 R12 A11
C1 D11 K15 BE0# R13 A8
C2 D18 K16 VCC R14 VCC
C3 CLK K17 VSS R15 A3
C4 VCC L1 VSS R16 BLAST#
C5 VCC L2 D6 R17 CLKMUL
Embedded Write-Back Enhanced IntelDX4™ Processor
13
C6 D27 L3 D7 S1 A27
C7 D26 L15 PWT S2 A26
C8 D28 L16 VCC S3 A23
C9 D30 L17 VSS S4 VOLDET
C10 SRESET M1 VSS S5 A14
C11 RESERVED# M2 VCC S6 VSS
C12 SMIACT# M3 D4 S7 A12
C13 NC M15 D/C# S8 VSS
C14 FERR# M16 VCC S9 VSS
C15 FLUSH# M17 VSS S10 VSS
C16 RESET N1 D2 S11 VSS
C17 BS16# N2 D1 S12 VSS
D1 D9 N3 DP0 S13 A10
D2 D13 N15 LOCK# S14 VSS
D3 D17 N16 M/IO# S15 A6
D15 A20M# N17 W/R# S16 A4
D16 BS8# P1 D0 S17 ADS#
Table 6. Pin Assignment for 168-Pin PGA Package (S he et 2 of 2)
Pin # Description Pin # Description Pin # Description
Embedded Write-Back Enhanced IntelDX4™ Processor
14
Table 7. Pin Cross Reference for 168-Pin PGA Pack age (Sheet 1 of 2)
Addres
sPin # Data Pin # Control Pin # NC INC Vcc5 Vcc Vss
A2 Q14 D0 P1 A20M# D15 C13 A13 J1 B7 A7
A3 R15 D1 N2 ADS# S17 B9 A9
A4 S16 D2 N1 AHOLD A17 B11 A11
A5 Q12 D3 H2 BE0# K15 C4 B3
A6 S15 D4 M3 BE1# J16 C5 B4
A7 Q13 D5 J2 BE2# J15 E2 B5
A8 R13 D6 L2 BE3# F17 E16 E1
A9 Q11 D7 L3 BLAST# R16 G2 E17
A10 S13 D8 F2 BOFF# D17 G16 G1
A11 R12 D9 D1 BRDY# H15 H16 G17
A12 S7 D10 E3 BREQ Q15 K2 H1
A13 Q10 D11 C1 BS16# C17 K16 H17
A14 S5 D12 G3 BS8# D16 L16 K1
A15 R7 D13 D2 CLK C3 M2 K17
A16 Q9 D14 K3 CLKMUL R17 M16 L1
A17 Q3 D15 F3 CACHE# B12 P16 L17
A18 R5 D16 J3 D/C# M15 R3 M1
A19 Q4 D17 D3 DP0 N3 R6 M17
A20 Q8 D18 C2 DP1 F1 R8 P17
A21 Q5 D19 B1 DP2 H3 R9 Q2
A22 Q7 D20 A1 DP3 A5 R10 R4
A23 S3 D21 B2 EADS# B17 R11 S6
A24 Q6 D22 A2 FERR# C14 R14 S8
A25 R2 D23 A4 FLUSH# C15 S9
A26 S2 D24 A6 HITM# A12 S10
A27 S1 D25 B6 HLDA P15 S11
A28 R1 D26 C7 HOLD E15 S12
A29 P2 D27 C6 IGNNE# A15 S14
A30 P3 D28 C8 INTR A16
A31 Q1 D29 A8 INV A10
D30 C9 KEN# F15
D31 B8 LOCK# N15
M/IO# N16
Embedded Write-Back Enhanced IntelDX4™ Processor
15
NMI B15
PCD J17
PCHK# Q17
PLOCK# Q16
PWT L15
RDY# F16
RESERVED# C11
RESET C16
SMI# B10
SMIACT# C12
SRESET C10
STPCLK# G15
TCK A3
TDI A14
TDO B16
TMS B14
VOLDET S4
WB/WT# B13
W/R# N17
T ab le 7. Pin Cross Refe rence for 16 8-Pin PGA Pack age (Sheet 2 of 2)
Addres
sPin # Data Pin # Control Pin # NC INC Vcc5 Vcc Vss
Embedded Write-Back Enhanced IntelDX4™ Processor
16
3.2 Pin Quick Reference
The follo wing is a brief pin descripti on. For detailed sig nal descriptions refe r to Appendix A, “Signal Descrip-
tions,” in the
Embedded Inte l486™ Pr ocessor Family Developer’s Manual,
order No. 2730 21.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 1 of 8)
Symbol Type Name and Function
CLK IClock
provides the fun damental timing and internal operating f req uency for the
Embedd ed Write -Back Enhanced IntelD X4 p rocessor . All ext ernal timing
parameters are sp ecified with respect to the risi ng edge of CLK.
ADDRESS BUS
A31-A4
A3–A2 I/O
OAdd r es s Lin es A31–A2, together with the byte enable signals, BE3#–BE0#,
define the physical area of memory or input/output space accessed. Address lines
A31–A4 are used to d riv e addr esses into the Embedded Wri te-Bac k Enhanced
IntelDX4 processor to perform cache line invalidation. Input signals must meet
setup and hold times t22 and t23. A31–A2 are not driven during bus or address
hold.
BE3#
BE2#
BE1#
BE0#
O
O
O
O
Byte Ena ble
signals indicate active bytes during read and write cycles. During the
first cycle of a cache fill, the ex ternal system should assume that all byte enab les
are active. BE3#–BE0# are active LOW and are not dri v en during bu s hold.
BE3# applies to D31–D24
BE2# applies to D23–D16
BE1# applies to D15–D8
BE0# applies to D7–D0
DATA BUS
D31–D0 I/O Data Lines. D7–D0 define the least significant byte of the data bus; D31–D24
define the most significant byte of the data bus. These signals must meet setup
and hold times t22 and t23 for proper operation on reads. These pins are driven
during the second and subsequent clocks of write cycles.
DATA PARITY
DP3–DP0 I/ O T he re i s on e Data Parity pin for each byte of the data bus. Data parity is generated
on all write data cycles with the same timing as the data driven by t he Embedded
Write-Back Enhanced IntelDX4 processor. Even parity information must be driven
back into the processor on the data parity pins with the same timing as read
inform ation to en sur e that the correct pari ty check status is indicat ed by the
Embedd ed Write -Back Enhanced IntelD X4 p rocessor . The signals read on these
pins do not affect program executio n.
Input signals must meet setup and hold times t22 and t23. DP3–DP0 must be
connecte d to VCC through a pull-up resistor in syst ems that do not use parity.
DP 3–DP0 are active HIG H and are driven during the se cond and s ubseque nt
clocks of wri te cyc les.
PCHK# OParity Status is driven on the PCHK# pin the clock after ready for read operations.
The parity status is for data sampled at the end of the previous clock. A parity error
is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes
as indicated by the byte en able and bus size signals. PCHK# is valid only in the
clock immed iately after read data i s returned to the processor. At all other ti mes
PCHK# is inactive (HIGH). PCHK# is never floated.
Embedded Write-Back Enhanced IntelDX4™ Processor
17
BUS CYCLE DEFINITION
M/IO#
D/C#
W/R#
O
O
O
Memory/Input-Output
,
Data/Control
and Write/Read
lines are the primary bus
definitio n signals. These signals are driven valid as the ADS # signa l is asserte d.
M/IO# D/C# W/R# Bus Cycle Initiated
0 0 0 Interru pt Acknowledge
0 0 1 HALT/Special Cycle (see details below)
0 1 0 I/O Rea d
0 1 1 I/O Wri te
1 0 0 Code Read
101 Reserved
1 1 0 Memory Read
1 1 1 Memory Write
HALT/Special Cycle
Cycle Name BE3# - BE0# A4-A2
Shutdown 1110 000
HALT 1011 000
Stop Grant bus cycle 1011 100
LOCK# OB us Loc k
indicates that the current bus cycle is locked. The Embedded Write-
Back Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is
as serted (address holds are allowed). LOCK# goes active in the fir s t clock of the
first locked bus cycle and g oes inactive af ter the la st cl ock of the last locked bus
c y cle. The last locked cycle ends when Read y is returned. LOC K# is active LOW
and not driven during bus hold. Locked read cycle s ar e not transformed into cache
fill cycles when KEN# is returned active.
PLOCK# OPseudo-Lock indicates that the current bus t ran saction requires more tha n one
bus cycle to c omplete. Fo r the Embedded Write-Back En hanced Intel DX4
processor, examples of su ch operations are segment table descriptor reads (64
bits) and cache line fills (128 bits). For Intel486 pr ocessors with on-chip Floating-
Poin t Unit , f loating-point long read s and writes (6 4 bits) also requi re mor e than one
bus cycle to complete.
The Embedded Write-Back Enhanced I ntel DX4 pr ocessor drives PLOCK# active
unt i l th e add r ess es f or the la st bus cyc le of the t ran sac ti on a r e d riv en, re ga rdl ess of
whether RDY# or BRDY# have been returned.
Normally PLOCK# and BLAST# are inverse of ea ch other. However, during the
firs t bus cyc le of a 64-bit floating-point write (for Intel4 86 pr ocessors with on-chip
Floating-Point Unit) both PLOCK# and BLAST# are as serted.
PLOC K# is a func tion of the B S8#, BS16# and KEN# inpu ts. PLOCK# should be
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and
is not dri ven during bus hold.
BUS CONTROL
ADS# OAddress Status
output indicates that a valid bus cycle definition and address are
available on the cy cle definition lines and address bus. ADS# is driven active in the
same clock in which the addresses are driven. ADS# is active LOW and not driven
during bus hold.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 2 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
18
RDY# INon-burst Read y
input indicates that the current bus cycle is complete. RDY#
indicates that the external system has presented valid data on the data pins in
response to a read or that the external system has accepted data from the
Embe dd ed Wri te- B ack Enh an ced Int el DX 4 pro ce sso r in resp on se to a wri t e. RDY#
is ignored when the bus is id le and at the en d of t he first cl ock of the bus cycle.
RDY# is active duri ng address hold. Data can be returned to the Embedded Write-
Back Enhanced IntelDX4 pr ocessor whi le AHO LD is active.
RDY# is active LOW and is not pr ovided with an internal pull-up resistor. RDY#
must satisfy setup and hold times t16 and t17 for proper c hip operation.
BURST CONTROL
BRDY# IBurst Ready
input performs the same function during a burst cycle that RDY#
performs during a non-burst cyc le. BRDY# indicates that the external sy stem h as
presented val id data in response to a read or that the external s ystem has
ac cept ed dat a in re spo ns e to a w ri te . B RD Y# i s ig no r ed wh en the bu s i s id le an d at
the end of th e first cloc k in a bus cycle.
BR DY# is samp led in the second and su bsequent clocks of a burst cycle. D ata
presented on the data bus is strobed into the Embedded Write-Back Enhanced
IntelDX4 processor when BRDY# is sampled ac tive. If RDY# is returned simulta-
neously wit h BRDY#, BRDY# is ignor ed and the burst cycle is prematurely
aborted.
BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must
satisfy th e setup and hol d times t16 and t17.
BLAST# OBurst Last
signal indicates that the next time BRDY# is re turned, the burs t bus
cycle is complete. BLAST# is active for both burst and non-burst bus cyc les.
BLAST# is active LOW and is not driven during bus hold.
INTERRUPTS
RESET IReset input for c es the Embedded Write-Back Enha nced IntelDX4 processor to
begin exec uti on at a known sta te. The processor cann ot begin executing i nstr uc-
tions until at least 1 ms after VCC, and CLK have re ached th eir prop er DC and A C
specifications. The RESET pin must remain active during this time to ensure
proper p rocessor operation. However, for warm resets, RESET should remain
active for at least 15 CLK perio ds. RESET is active HIGH. RESET i s asynchronous
but mu st me et setup and hold times t20 and t21 for recognition in any sp ecif ic cloc k.
INTR IMask able Interrupt
indicates that an ex ternal interrupt has been generated. When
the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated.
The Embedded Write-Back Enhanced IntelDX4 processorgenerates two locked
interrupt acknowledge bus cycles in response to the INTR pin going active. INTR
must remain act ive until the int errupt acknowledges have been performed to
ensure processor recognition of the interrupt.
IN TR i s a ct iv e H IG H an d i s n ot pr o vi de d wi th an in te rn al pu ll -do wn r es is to r. IN TR is
as ynchr onous, but m ust meet setup and hold times t20 and t 21 for recognition in
any specific cl ock.
NMI INon-Mask able Interrupt
request signal indicates that an external non-maskable
interrupt has been gen erated. NMI is rising-edge sensitive and must be held LOW
for at least four CLK periods before this rising edge. NMI is not provided with an
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold
times t20 an d t21 for recognition in any specific clock.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 3 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
19
SRESET ISoft Res et pi n duplic ates all functionality of the RESET pin except that the
SMBASE register retain s its previous val ue. For soft resets, SRESET must remain
active for at least 15 CLK periods. SRESET is active HIGH. SRESET is
asynchronous but must meet setup and hold times t20 and t21 for recognition in any
specific clock.
SMI# ISy ste m Ma na ge me nt I nt err u pt input invokes System Management Mode (SMM).
SMI# is a falling-edge triggered sig nal which forces the Embedded Write-Ba ck
En ha nce d In t el DX 4 pr oce ss ori nt o SMM a t the co mpl et ion of th e c ur re nt i nstr uct io n.
SMI# is recognized on an instruction boundary and at each iteration for repeat
string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a
currently executing SMM. The Embedded Write-Back Enhanced IntelDX4 proces-
sorlatches the falling edge of one pending SMI# signal while it is executing an
existing SMI#. The nested SMI# is not recognized until after the exec ution of a
Resume (RSM) instruction.
SMIACT# OSystem Management Interrupt Active, an active LO W ou tp ut, in di ca te s tha t the
Embedded Write-B ack Enhanced IntelD X4 processoris operating in SMM. It is
asserted when the processor begins to execute the SMI# state save sequence and
remains active LOW until the processor executes the last state restore cycle out of
SMRAM.
STPCLK# IStop Clo ck Request inpu t signal indicates a r equest was m ade to turn off or
change the CLK input frequency. When the Embedded Write-Back Enhanced
IntelDX4 processorrecognizes a STPCLK#, it stops execution on the next
instruction boundary (unless superseded by a higher priority interrupt), empties all
internal pipelines and write buffers, and generates a Stop Grant bus cycle.
STPC LK# i s active LOW. S TPCLK# must be pulled high via a 10- KW pullup
resistor. STPCLK# is an asynchronous signal, but must remain active until
the Embedded Write-Back Enha nced IntelDX4 processor issues the Stop
Gran t bus cycl e. STPCLK# may be de-asserted at any time after the
processor has issued the Stop Grant bus cycle.
BUS ARBITRATION
BREQ OBus Request
signal indicates that the Embedded Write-Back Enhanced IntelDX4
processorh as internally gene rated a bus request. B REQ is generated whether or
not the processor is driving the bus. BREQ is active HIGH and is never floated.
HOLD IBus Hold Request all ows anot her bus master complete control of the Embedd ed
Write-Back Enhanced IntelDX4 processorbus. In response to HOLD going active,
th e p r oc essor f l oats mo st o f it s o ut put an d in pu t/o ut pu t pi ns . HLD A i s a sse rt ed af ter
c ompleting the curr ent bus cycle, burst cy cle or sequence of locked cycles. The
Embedded Write-Back Enhanced In telDX4 processorremains in this s tate until
HOLD is de- asserted. HOLD is active HIGH and is not p rovi ded with an internal
pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper
operation.
HLDA OHold Acknowledge
goes active in response to a hold request presented on the
HOLD pin. HLDA indicates that the Embedded Write-Back Enhanced IntelDX4
processor ha s given the bus to another local bus maste r. HLDA i s dri v en acti ve in
the same clock that the proces sor floats its bu s. HLDA is driven inactive when
leaving bus hold. HLDA is active HIGH and remains driven during bus ho ld.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 4 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
20
BOFF# IBackoff
input forces the Embedded Write-Back Enhanced IntelDX4 pr ocessor to
float its bus in the next clock. The processor floats all pins normally floated during
bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher
priority than RDY# or BRDY#; if both are returned in the same clock, BOFF# takes
effect. The Embedded Write-Back Enhanced IntelDX4 processor remains in bus
hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted
the cycle is restarted. BOFF# is active LOW and must meet setup and hold times
t18 and t19 for proper operation.
CACHE INVALIDATION
AHOLD IAdd res s H old
reque st allows another bus mas ter access to the Emb edded Write-
Back Enhanced IntelDX4 processor’s address bus f or a cache invalidation cycle.
The processor stops driving its address bus in the clock following AHOLD going
active. O nly the address bus is floated du ring address hold, the remainder of the
bus remains activ e. AHOLD is active HIGH and is provided with a small internal
pull-down resistor. Fo r proper operati on, AHOLD must meet s etup and hold times
t18 and t 19.
EADS# IExtern al Address - This signal indicates that a
valid
external address has been
dri ven on to th e Em bedde d Write-Bac k Enha nced I ntelD X4 proc essor addre ss pins .
This address is used to perform an internal cache invalidation cycle. EADS# is
ac tive LOW and is provided with an in ter nal pull-u p resistor. EAD S# must satisfy
setup and hold times t12 and t13 for proper operation.
CACHE CONTROL
KEN# ICache Enable
pin is used to determine whether the current cycle is cacheable.
When the Embed ded Writ e-Back Enhanced IntelDX4 processorgene rates a cycle
that can be cached and KEN# is active one clock before RDY# or BRDY# during
the first transfer of the cycle , the cycle becomes a cache line fill cycle. Returning
KEN# ac tive one clock before RDY# during the last read in the cache line fill
causes the line to be plac ed in the on-c hip cache. KEN# is acti ve LOW and i s
provided with a small internal pull-up resistor. KEN# must satisfy setup and hold
times t14 and t15 for proper operation.
FLUSH# ICache Flush
input forces the Embedded Write-Back Enhance d IntelDX4
processorto flush its entire internal cache. FLUSH# is active LOW and need only
be asser ted for one clock. FLUSH# is asynchro nous but setu p and hold times t20
and t21 must be met for re cogni tio n in any specif ic clock.
PAGE CACHEABILITY
PWT
PCD O
OPage Write-Th roug h
and Page Cache Disable pins reflect the state of the page
attribute bits, PWT and PCD, in the page table entry, page directory entry or
control register 3 (CR3) when paging is enabled. When paging is disabled, the
Embedded Write-Back Enhanced IntelDX4 processorignores the PCD and PWT
bits and assum es they a re zero for the purpose of cachin g and dr iving PCD and
PWT pins. PWT and PCD have the same timing as the cycle definition pins (M/IO#,
D/C#, and W/R#). PWT and PCD are active HIGH and are not driven during bus
hold. PC D is masked by the cache disable bit (CD) in Control Register 0.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 5 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
21
BUS SIZE CONTROL
BS16#
BS8# I
IBus Size 16
and Bus Size 8
pins (bus sizing pins) cause the Embedded Write-
Back Enhanced IntelDX4 processor to run multiple bus cycles to complete a
request from devices that cannot provide or accept 32 bits of data in a single cycle.
The bus sizing pins are sampled every clock. The processor uses the state of
these pins in the clock before Ready to determine bus size. These signals are
active LOW and are provided with internal pull-up resistors. These inputs must
s atisfy setup a nd hol d times t14 an d t15 for proper operation.
ADDRESS MASK
A20M# IAddress Bit 20 Mask pin, when asserted, causes the Embedded Write-Back
Enhanced IntelDX4 processorto mask physical address bit 20 (A20) before
performing a lookup to the internal cache or driving a memory cycle on the bus.
A20M# emulates the address wraparou nd at 1 Mbyte, which occurs on the 8086
processor. A20M# is active LOW and should be asserted only when the
Embedded Write-Back Enhanced IntelDX4 processoris in real mode. This pin is
asyn chr ono us b ut s houl d me et se tu p an d ho ld ti mes t20 and t21 for r ec ogni tion in
any s pecific clock. For proper operation, A20M# should be s ampled HIGH at the
falling edge of RESET.
TEST ACCESS PORT
TCK ITes t Clock, an input to the Embedded Write-Back Enhanced IntelDX4 processor,
provides the clocking function required by the JTAG Boundary scan feature. TCK
is us ed to c lo ck s tat e i nfo r m ati on (v ia TMS ) an d d ata (v ia TD I) in to the c om po ne nt
on the rising edge of TCK. Data is clocked out of the component (via TDO) on the
falling edge of TCK. TCK is prov ided with an internal pull-u p resistor.
TDI ITest Data Input is the serial input used to shift JTAG instructions an d data into the
processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and
SHIFT-DR Test Access Port (T AP) controller states. During all other TAP controll er
states, TDI is a “don’t care.” TDI is provided with an internal pull-up resistor.
TDO O Tes t D a ta Output is the serial output used to shift JTAG instructions and data out
of the co mponent. TDO is driven on the falling edge of TCK during the SHIFT-I R
and SHIFT-DR TAP controller states. At al l other times TDO is driven to the high
impe dance state.
TMS ITest Mode Select is deco ded by th e JT AG TAP to sele ct tes t logi c ope rat i on . TMS
is sampled on the rising edge of TCK. To guarantee deterministic behavior of the
TAP controller, TMS is provided wi th an internal pull-up resistor.
NUMERIC ERROR REPORTI NG
FERR# OThe Floating Point Error pin is driven a ctive when a floating point error o ccurs.
FERR# is similar to the ERROR# pin on the Intel387™ Math CoProcessor. FERR#
is included for compatibility with systems using DOS type floating point error
reporting. FERR# will not go active if FP errors are masked in FPU register.
FERR# is active LO W, an d is not floa ted during b us hold.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 6 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
22
IGNNE# I When the Ignore Numeric Error pin is asserted the processor will ignore a
numeric error and continue executing non-control floating point instructions, but
FERR# will still be activated by the processor. When IGNNE# is de-asserted the
processor will freeze on a non-control floating point instruction, if a previous
floating point instruction caused an error. IGNNE# ha s no effect when the NE bit in
control register 0 is set. IGNNE# is active LOW and is provided with a small
internal pull-up resistor. IGNNE# is asynch ronous but setup and hold times t20 and
t21 must be met to ensure recognition on any specific clock.
WRITE-BACK ENHANCED MODE
CACHE# OThe CACHE# output indicates internal cacheability on read cycles an d burst write-
back on write cycles. CACHE# is asserted for cacheable reads, cacheable code
fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles,
special cycles, and w rite-through c ycles.
FLUSH# ICache FLUSH# is an existing pin that operates differently if the processor is
con f ig ur ed a s En hanced B us mo de (w rite-ba c k). F LU SH # ca us es the pr o ce s so r t o
write back all modified lines and flush (invalidate) the cache. FLUSH# is
as ynchr onous, but must meet setup and hol d times t 20 and t21 for recognition in any
specific clock.
HITM# OThe Hit/Miss to a Modified Line pin is a cache coherency protocol pin that is
dr iven onl y i n E nhan ced Bus mo de. Wh en a sn oop cyc le i s ru n, HIT M# indi cate s
that the processor contains the snooped line and that the line has been modified.
Assertion of HITM# implies that the line will be writte n back in its entirety, unless
the processor is already in the process of doing a replacement write-back of the
sam e li ne .
INV IThe Inv al ida tio n Re qu es t pin is a cache coherency protocol pin that is used only
in the Enhanced Bus mode. It is sampled by the processor on EADS#-driven
snoop cycles. It is necessary to assert this pin to get the effect of the processor
invalidate cycle on write-through-only lines. INV also invalidates the write-back
lines. However, if the snooped line is modified, the line will be written back and
then invalidated. INV must satisfy setup and hold times t12 and t13 for proper
operation.
PLOCK# O In the Enhanced bus mode, Pseudo-Lock Output is always driven inactive. In this
mode, a 64-bit data read (caused by an FP operand access or a segment
descriptor read) is treated as a multiple cycle read request, which may be a burst
or a non-burst access based on whether BRDY# or RDY# is returned by the
system. Because only write-back cycles (caused by snoop write-back or
replacement write-back) are write burstable, a 64-bit write will be driven out as two
non-b urs t bus cycles. BLAST# is asser ted during bot h writes.
SRESET I For the Embedded Write-Back Enhanced IntelDX4 processor, Soft RESET
operates similar to other the Intel486 processors. On SRESET, the internal
SMRAM base register retains its previous value, does not flush, write-back or
disable the internal cache. Because SRESET is treated as an interrupt, it is
possibl e to h ave a b us c ycle whi le SRES ET i s as serte d. S RESET is s erviced onl y
on an instruction boundary. SRESET is asynchronous but must meet setup and
hold times t20 and t21 for recognition in any specific cl ock.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 7 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
23
WB/WT# IThe Write-Back/Write-Through pin enables Enhanced Bus mode (write-back
cache). It also defines a cached line as write-through or write-back. For cache
configu ra tion, WB/ WT# mus t be v a lid du ring RESET an d be activ e for at lea st two
clocks be fore and tw o clocks afte r RESET is de- asserted. To d efine write-ba ck or
write-through configuration of a line, WB/WT# is sampled in the same clock as the
first RDY# or BRDY# is returned duri ng a line fill (allocation) cycle.
CLKMUL, VCC5, AND VOLDET
CLKMUL IThe Clock Multiplier input, defined during device RESET, defines the ratio of
internal core frequency to external bus frequency. If sampled low, the core
frequency operates at twice the external bus frequency (speed doubled mode). If
driven high, speed triple mode is selected. CLKMUL has an internal pull-up speed
to VCC. A 10-KΩ pullup res istor is recommended when the pin is tied high.
VCC5 IThe 5V reference voltage
input is the reference voltage for the 5V-tolerant I/O
buffers. This signal should be connected to +5V ±5% for use with 5V logic. If all
inputs are from 3V logic, this pin should be connected to 3.3V.
VOLDET OA Voltage Detect si gnal a llows exter na l syst em lo gic to dis ti nguis h bet wee n a 5V
Intel486 processor and the 3.3V IntelDX4 processor. This signal is active LOW for
a 3.3V IntelDX4 processor. This pin is available only on the PGA version of the
Embedded Write-Back Enhanced In telDX4 processor.
RESERVED PINS
RESERVED# IReserved is res erv ed fo r fut ure use . Thi s pi n MUS T b e co nnec ted to an e xtern al
pull- up re sist or c ircui t. The rec omm end ed re sist or val ue is 10 k Oh ms. Th e pull -up
resistor must be connected only to the RESERVED# pin. Do not share this
resistor with other pins requiring pull-ups.
Table 8. Embedded Write-Back Enhanced IntelDX4™ Processor Pin Descriptions (Sheet 8 of 8)
Symbol Type Name and Function
Embedded Write-Back Enhanced IntelDX4™ Processor
24
Table 9. Output Pins
Name Active Level Output Signal
Floated During
Add r es s Hold Floated During
Bus Hold During Stop Grant and
S top Cloc k Sta tes
BREQ HIG H Prev i ous State1
HLDA HIGH As pe r HOL D
BE3#-BE0# LOW • Prev i ous State
PWT, PCD HIGH • Pr evious State
W/R#, M/IO#, D/C# HIGH/LOW • Previous State
LOCK# LOW • HIGH (inac tive)
PLOCK# LOW • HI GH (inactiv e)
ADS# LOW • H I GH (inactive)
BLAST# LOW • Prev ious State
PCHK# LOW Prev i ous State
FERR# LOW Prev i ous State
A3-A2 HIGH • • Previous St ate
SMIACT# LOW Previous State
CACHE# LOW • • HIGH2
HITM# LOW • • HIGH2
VOLDET LOW LOW
NOTES:
1. The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the pro-
cessor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
2. For the case of snoop cycles ( via EADS#) during Stop Grant state, CACHE# and HITM# can go ac tive depending on the
snoop hit in the internal cache.
Table 10. Input/Output Pins
Name Active Level
Output Signal
Floated Durin g
Ad dress Hold Floated During
Bus Hold During Stop Grant and
Stop Clock States
D31-D0 HIGH • Floated
DP3–DP0 HIGH • Floated
A31-A4 HIGH • • Previous State
NOTE: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the
processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Embedded Write-Back Enhanced IntelDX4™ Processor
25
Ta ble 11. Test Pins
Name Input or Output Sampled/ Driven On
TCK Input N/A
TDI Input Rising Edge of TCK
TDO Ou tput Failin g Edge of TC K
TMS Input Rising Edge of TCK
Tab le 12 . Input Pins (Sheet 1 of 2)
Name Active Level Synchronous/
Asynchronous In ternal Pul l-Up/
Pull-Down
CLK
RESET HIGH Asynchronous
SRESET HIGH Asynchronous Pull-Down
HOLD HIGH Synchronous
AHOLD HIGH Synchronous Pull-Down
EADS# LOW Synchronous Pull-Up
BOFF# LOW Synchronous Pull-Up
FLUSH# LOW Asynchronous Pull-Up
A20M# LOW Asynchronous Pull-Up
BS 16#, BS8# LOW Synchronous Pull-Up
KEN# LOW Synchronous Pull-Up
RDY# LOW Synchronous
BRDY# LOW Synchronous Pull-Up
INTR HIGH Asynchronous
NMI HIGH Asynchronous
IGNNE# LOW Asynchronous Pull-Up
RESERVED# LOW Asynchronous Pull-Up
SMI# LOW Asynchronous Pull-Up
STPCLK# LOW Asynchronous Pull-Up1
INV HIGH Synchronous Pull-Up
NOTE:
1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-KΩ pull-
up resi stor is needed i f the STPCLK# pin i s unused. CLKMUL must be driven to a valid logic l evel. If tied HIG H, an external
10-KΩ pull-up resistor is recommended.
Embedded Write-Back Enhanced IntelDX4™ Processor
26
WB/WT# HIGH/LOW Synchronous Pull-Down
CLKMUL HIGH Pull-Up1
TCK HIGH Pull-Up
TDI HIGH Pull-Up
TMS HIGH Pull-Up
Table 12. Input Pins (Sheet 2 of 2)
Name Active Level Synchronous/
Asynchronous Internal Pull-Up/
Pull-Down
NOTE:
1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-KΩ pull-
up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level . If ti ed HIGH, an exter nal
10-KΩ pull-up resistor is recommended.
4.0 ARCHITECTURAL AND
FUNCTIONAL OVERVIEW
The Embedded Write-Back Enhanced IntelDX4
processor architecture is essentially the same as the
IntelDX4 processor. Refer to the
Embedded
Intel486™ Processor Family Developer’s Manual
(273021)
The Embedded Write-Back Enhanced IntelDX4
processor has one pin reserved for possible future
us e. This pin, an inp ut signal , is calle d RESERV ED#
and must be connected to a 10-KΩ pull-up resistor.
The pull-up resistor must be connected only to the
RESERVED# pin. Do not sh are this resisto r with
other pins requiring pull-ups.
4.1 CPUID Instruction
The Embedded Write-Back Enhanced IntelDX4
proc es sor supp or ts t he C PUI D i ns tru ct io n (se e Ta bl e
13). Because not all Intel processors support the
CPUID instruction, a simple test can determine if the
instruction is supported. The test involves the
processor’s ID Flag, which is bit 21 of the EFLAGS
register. If software can change the value of this flag,
the CPUID instruction is available. The actual state
of th e ID Flag bit is irrelevant and provides no signifi-
cance to the hardware. This bit is cleared (reset to
zero) upon device reset (RESET or SRESET) for
c ompatibil ity with Intel486 pro cessor design s that do
not su ppor t th e CPU ID instruction.
CPUID-instruction details are provided here for the
Embedded Write-Back Enhanced IntelDX4
processor. Refer to Intel Application Note AP-485
Intel Processor Identification with the CPUID
Instruction
(Or der N o. 24 1618 ) for a descr ipt ion th at
covers al l a s pe cts of t he C PU ID in struct io n an d how
it pertains to other Intel processors.
4.1.1 Operation of the CPUID Instruction
The CPUID instruction requires the software
developer to pass an input parameter to the
processor in the EAX register. The processor
response is returned in registers EAX, EBX, EDX,
and ECX.
Table 13. CPUID Instruction Desc ription
OP CODE Instruction Processor
Core Clocks
Parameter passed in
EAX
(Input Value) Description
0F A2 CPUID 9 0 Vendor (Intel) ID Strin g
14 1 Processor Identification
9 > 1 Undefined (Do Not Use)
Embedded Write-Back Enhanced IntelDX4™ Processor
27
Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon
instruct ion exec ution are show n in the following ta ble.
The v alues in EB X, E DX an d EC X in dic a te an I nte l proces s or. Wh en tak en in th e pr o pe r or d er, they de co de to
the string “GenuineIntel.”
The state of the WB/WT# input pin is sa mpled by the processor on the falling edge of the RESET signal. If
WB /WT# is L OW, the pro cess or is co nfigu re d to opera te in W rite- Thro ugh/ Sta ndard Bu s m ode. If H IGH, it is
configured to operate in Write-Back/Enhanced Bus mode. The value of the “Model” field of the processor
signature register depends on the bus mode for which the processor is configured.
Pro cessor Ide ntifica tion - When the parameter passed to EAX is 1 (one), the register values returned upon
instruct ion exec ution are:
31-------------24 23-----------16 15--------------8 7--------------0
High Value (= 1) EAX 0000 0000 0000 0001
Vendor ID String EBX u (75) n (6E) e (65) G (47)
(ASCII EDX I (49) e (65 ) n (6E) i (69)
Characters) ECX l (6C) e (65) t (74) n (6E)
31---------------------------14 13,12 11----8 7----4 3----0
Processor
Signature for
Write-Through/Stan-
dard Bus mode
EAX (Do Not Use)
Intel Reserved 0 0
Processor
Type
0 1 0 0
Family 1 0 0 0
Model XXXX
Stepping
Processor
Signature for
Write-
Back/Enhanced Bus
mode
(Do Not Use)
Intel Reserved 0 0
Processor
Type
0 1 0 0
Family 1 0 0 1
Model XXXX
Stepping
(Intel releases information about stepping numbers as needed)
31--------------------------------------------------------------------------------------------------0
Intel Reserved EBX Intel Reserved
(Do Not Use) ECX Intel Reserved
31----------------------------------------------------------------------------2 1 0
Feature Flags EDX 0------------------------------------------------------------------------------0 1
VME 0
FPU
Embedded Write-Back Enhanced IntelDX4™ Processor
28
4.2 Identif ication After Reset
P roc es sor Ide nti fica tion - Upon reset, the EDX register contains the processor signature:
4 .3 Bou ndary Sca n (J TA G)
4.3.1 D evice Identi fi cation
Tables 1 4 and 15 show the 32-bit code for the Embedd ed W rite- Back Enh anced IntelDX 4 processor. This code
is loaded into the Device Identification Register.
31---------------------------14 13,12 11----8 7----4 3----0
Processor
Signature for
Write-Through/Stan-
dard Bus mode
EDX (Do Not Use)
Intel Reserv ed 0 0
Processor
Type
0 1 0 0
Family 1 0 0 0
Model XXXX
Stepping
Processor
Signature for
Write-
Back/Enhanced Bus
mode
(Do Not Use)
Intel Reserv ed 0 0
Processor
Type
0 1 0 0
Family 1 0 0 1
Model XXXX
Stepping
(Intel releases information about stepping numbers as needed)
Table 14. Bounda ry Scan Component Identification Code (Write-Through/Standard Bus Mode)
Version Part Number Mfg ID
009H = Intel 1
VCC
1=3.3 V Intel
Architecture
Ty pe
Family
0100 = Intel486
CPU Family
Model
01000 =
Embedded Write-
Back Enhanced
IntelDX4 processor
31----28 27 26-----------21 20----17 16--------12 11------------1 0
XXXX 1 000001 0100 01000 00000001001 1
(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Cod e = x828 8013 (Hex)
Embedded Write-Back Enhanced IntelDX4™ Processor
29
4.3.2 Boundary Scan Register Bits and Bit
Order
The bo undary scan register conta ins a cell for each
pin as well as cells for control of bidirectional and
three-state pins. There are “Reserved” bits which
correspond to no-connect (N/C) signals of the
Embedded Write-Back Enhanced IntelDX4
processor. Control registers WRCTL, ABUSCTL,
BUSCTL, and MISCCTL are used to select the
direction of bidirectional or three-state output signal
pins. A “1” in these cells designates that the
associated bus or bits are floated if the pins are
three-state, or selected as input if they are bidirec-
tional.
• WRCTL controls D31-D0 and DP3–DP0
• ABUSCTL cont rols A31-A2
• BUSCTL controls ADS#, BLAST#, PLOCK#,
LOCK#, W/R#, BE0# , BE1#, BE2#, BE3#, M/IO#,
D/C#, PW T, PCD, and CACHE#
• MISCCTL controls PCHK#, HLDA, BREQ, and
HITM#
The f ollowing is the bit o rde r of the Embedded Writ e-
Back Enhanced IntelDX4 processor boundary scan
register:
Table 15. Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode)
Version Part Number Mfg ID
009H = Intel 1
VCC
1=3.3 V Intel
Architecture
Type
Family
0100 = Intel486
CPU Family
Model
01001 =
Embedded Write-
Back Enhance d
IntelDX4 processor
31----28 27 26-----------21 20----17 16--------12 11------------1 0
XXXX 1 000001 0100 01001 00000001001 1
(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Code = x828 9013 (Hex)
TDO ←A2, A3, A4, A5, RESERVED#, A6,
A7, A8, A9, A10, A11, A12, A13,
A14, A15, A16, A17, A18, A19,
A20, A21, A22, A23, A24, A25,
A26, A27, A28, A29, A30, A31,
DP0, D0, D1, D2, D3, D4, D5, D6,
D7, DP1, D8, D9, D10, D11, D12,
D13, D14, D15, DP2, D16, D17,
D18, D19, D20, D21, D22, D23,
DP3, D24, D25, D26, D27, D28,
D29, D30, D31, STPCLK#,
IGNNE#, INV, CACHE#, FERR#,
SMI#, WB/WT#, HITM#,
SMIACT#, SRESET, NMI, INTR,
FLUSH#, RESET, A20M#,
EADS#, PCD, PWT , D/C#, M/IO#,
BE3#, BE2#, BE1#, BE0#, BREQ,
W/R#, HLDA, CLK, AHOLD,
HOLD, KEN#, RDY#, CLKMUL,
BS8#, BS16#, BOFF#, BRDY#,
PCHK#, LOCK#, PLOCK#,
BLAST#, ADS#, MISCCTL,
BUSCTL, ABUSCTL, WRCTL ← TDI
Embedded Write-Back Enhanced IntelDX4™ Processor
30
5.0 ELECTRICAL SPECIFICATIONS
5.1 Maximum Ratings
Table 16 is a stress rating only. Extended exposure
to the Maximum Ratings may affect device reliability.
Furthermore, although the Embedded Write-Back
Enhanced IntelDX4 processorcontains protective
circuitry to resist damage from electrostatic
discharge, always take precautions to avoid high
static voltag es or electric fields.
Functional operating conditions are given in Section
5.2, DC Specif ications and Se ction 5.3, AC Speci-
fications.
5.2 DC Specifications
The following tables show the operating supply
voltages, DC I/O specifications, and component
power consumption for the Embedded Write-Back
Enha nced IntelDX4 proce s sor.
Table 16. Absolute Maximum Ratings
Case Temperature under
Bias -65 °C to +110 °C
Storage Temperature -65 °C to +150 °C
DC Voltage on Any Pin with
Respect to Ground -0.5 V to VCC5 + 0.5 V
Supply Voltage VCC with
Respect to VSS -0.5 V to +4.6 V
Reference V oltage VCC5 with
Respect to VSS -0.5 V to +6.5 V
Transient Voltage on any
Input The lesser of:
VCC5 +1.6V
or
6.5 V
Current Sink on VCC5 55 mA
Table 17. Operating Supply Voltages
Product VCC
FC80486DX4WB75 3.3 V ± 0.3V
FC80486DX4WB100 3.3 V ± 0.3V
A80486DX4WB100 3.3 V ± 0.3V
Embedded Write-Back Enhanced IntelDX4™ Processor
31
Table 18. DC Specifications
Functional Operating Range: VCC =3.3V±0.3 V; VCC5 =5V±0.25 V (Note 1); TCASE=0 °C to +85 °C
Symbol Parameter Min. Typ. Max. Unit Notes
VIL Input LOW Voltage -0.3 +0.8 V
VIH Input HIGH Voltage 2.0 VCC5 +0.3 V Note 2
VIHC Input HIGH Voltage of CLK VCC5 -0.6 VCC5 +0.3 V
VOL Output LOW Voltage
IOL = 4.0 mA (Address, Data, BE
n
)
IOL = 5.0 mA (Definition, Control)
IOL = 2.0 mA
IOL = 100 µA
0.45
0.45
0.40
0.20
V
V
V
V
VOH Output HIGH Voltage
IOH = -2.0 mA 2.4 V
ICC5 VCC5 Leakage Current 15 300 µA Note 3
ILI Input Leakage Current 15 µA Note 4
IIH Input Leakage Current
SRESET 200
300 µA
µANote 5
Note 5
IIL Input Leakage Current 400 µA Note 6
ILO Output Leakage Current 15 µA
CIN Input Capacitance 10 pF Note 7
COUT I/O or Output Capacitance 14 pF Note 7
CCLK CLK Capacitance 12 pF Note 7
NOTES:
1. VCC5 should be connected to 3.3 V ±0.3 V in 3.3 V-onl y systems.
2. All inputs except CLK.
3. This parameter is for inputs without pull-up or pull-down resistors and 0V ≤ VIN ≤ VCC.
4. This parameter is for VCC5 –V
CC ≤2.25 V. Typical value is not 100% tested.
5. This parameter is for inputs with pull-down resistors and VIH = 2.4V.
6. This parameter is for inputs with pull-up resistors and VIL = 0.4V.
7. FC=1 MHz. Not 100% tested.
Embedded Write-Back Enhanced IntelDX4™ Processor
32
Table 19. ICC Values
Functional Operating Range: VCC = 3.3 V ±0.3 V; VCC5 =5V±0.25 V ( Note 1); TCASE = 0°C to +85°C
Parameter Operating
Frequency Typ. Maximum Notes
ICC Active
(Power Supply) 75 MHz
10 0 MHz 1100 mA
1450 mA Note 2
ICC Active
(Thermal Design) 75 MHz
10 0 MHz 825 mA
1075 mA 9 75 mA
1300 mA No tes 3, 4, 5
ICC Stop Grant 75 MHz
10 0 MHz 20 mA
50 mA 75 mA
100 mA Note 6
ICC Stop Clock 0 MHz 600 µA 2 mA Note 7
NOTES:
1. VCC5 should be connected to 3.3 V ±0.3 V in 3.3 V-only systems.
2. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.
3. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix
at VCC = 3.3V.
4. The typical current column is the typical operating current in a system. This value is measured in a system using a typical
device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle conditi on. This typical value is dependent upon the specific
system configuration.
5. Typical values are not 100% tested.
6. The ICC Stop Grant specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor
enters the Stop Grant or Auto HALT Power Down state.
7. The ICC Stop Clock specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor
enters the Stop Clock state. The VIH and VIL levels mus t be equal to VCC and 0 V, respectively, in order to meet the ICC
Stop Clock specifications.
Embedded Write-Back Enhanced IntelDX4™ Processor
33
5.3 AC Specifications
The AC specific ations for the Embedded Wr ite -Back Enhanced IntelDX4 processor are given in this sect ion.
Table 20. AC Characteristics
VCC = 3.3 V ± 0.3 V; VCC5 =5V±0.25 V (Note 1)
TCASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 1 of 2)
Symbol Parameter
Product
WB75 WB100
Min Max Min Max Unit Figure Notes
CLK Frequency 8 25 8 33 MHz Note 2
t1CLK Period 40 125 30 125 ns 4
t1a CLK Period Stabil ity ±250 ±250 ps 4 Adjacent
clocks
Note 3
t2CLK High Time 14 11 ns 4 at 2V
t3CLK Low Time 14 11 ns 4 at 0.8V
t4CLK Fall Time 4 3 ns 4 2V to 0.8V
t5CLK Rise Time 4 3 ns 4 0.8V to 2V
t6A31–A2, PWT, PCD, BE3–BE0#,
M/IO #, D/C#, W/R#, ADS#, LOCK# ,
FERR#, CACHE#, HITM#, BREQ,
HLDA Va lid Delay
3 19 3 14 ns 8
t7A31–A2, PWT, PCD, BE3–BE0#,
M/IO #, D/C#, W/R#, ADS#, LOCK# ,
CACHE# Float Delay
28 20 ns 9 Note 3
t8PCHK# Valid Delay 3 24 3 14 ns 7
t8a BLAST#, PLOCK#, SMIACT# Vali d
Delay 3 24 3 14 ns 8
t9BLAST#, PLOCK# Float Dela y 28 20 ns 9 Note 3
t10 D31–D0, DP3–DP0 Write Data Valid
Delay 3 20 3 14 ns 8
t11 D31–D0, DP3–DP0 Wr ite Data Float
Delay 28 20 ns 9 Note 3
t12 EADS#, INV Setup Time 8 5 ns 5
t13 EADS#, INV Hold Ti me 3 3 ns 5
t14 KEN#, BS16#, BS8#, WB/WT# Setup
Time 85ns5
t
15 KEN#, BS16#, BS8#, WB/WT# Hold
Time 33ns5
t
16 RDY#, BRDY# Setup Time 8 5 ns 6
t17 RDY#, BRDY# Hold Time 3 3 ns 6
Embedded Write-Back Enhanced IntelDX4™ Processor
34
t18 HOLD, AHOLD Setu p Time 8 6 ns 5
t18a BOFF# Setup Tim e 8 7 ns 5
t19 HOLD, AHOLD, BOFF# Hold T ime 3 3 ns 5
t20 FLUSH#, A20M#, NMI, INTR, SMI#,
STPCL K#, SRESET, RESET,
IGNNE# Setup Time
8 5 ns 5 N o te 4
t21 FLUSH#, A20M#, NMI, INTR, SMI#,
STPCL K#, SRESET, RESET,
IGNNE# Hold Time
3 3 ns 5 N o te 4
t22 D31–D0, DP3–DP0,
A31–A4 Re ad Setup Time 55 ns6
5
t
23 D31–D0, DP3–DP0,
A3 1– A4 R ea d Hold T im e 33 ns6
5
NOTES:
1. VCC5 should be connected to 3.3 V ±0.3 V in 3.3 V-only systems.
2. 0-MHz operation i s guaranteed when the STPCLK# and Stop Grant bus c ycle protocol is used.
3. Not 100% tested, guaranteed by design characterization.
4. A reset pulse width of 15 CLK cycles is required for wa rm resets (RESET or SRESET). Power-up resets (cold resets)
require RESET to be asserted for at least 1 ms after VCC and CLK are stable.
Table 20. AC Characteristics
VCC = 3.3 V ± 0.3 V; VCC5 =5V±0.25 V (Note 1)
TCASE = 0°C to +85°C; CL = 50pF, unless otherwis e specified. (Sheet 2 of 2)
Symbol Parameter
Product
WB75 WB100
Min Max Min Max Unit Figure Notes
Embedded Write-Back Enhanced IntelDX4™ Processor
35
Table 21. AC Specifications for the Test Access Port
VCC = 3.3 V ±0.3 V; VCC5 =5V±0.25 V (Note 1)
TCASE = 0°C to +85 °C; CL = 50 pF
Symbol Parameter Min Max Uni t Figure Notes
t24 T C K Fr eq ue nc y 25 MH z No te 2
t25 TCK Period 40 ns 10
t26 TCK High Time 10 ns 10 @ 2.0V
t27 TCK Low Time 10 ns 10 @ 0.8V
t28 TCK Rise Time 4 ns 10 Note 3
t29 TCK Fall Time 4 ns 10 Note 3
t30 TDI, TMS Setup Time 8 ns 11 Note 4
t31 TDI, TMS Hold Time 7 ns 11 Note 4
t32 TDO Valid Delay 3 25 ns 11 Note 4
t33 TDO Float Delay 30 ns 11 Note 4
t34 All Outputs (except TDO) Valid Delay 3 25 ns 11 Note 4
t35 All Outputs (except TDO) Float Delay 36 ns 11 Note 4
t36 All Inputs (except TDI, TMS, TCK) Setup Time 8 ns 11 Note 4
t37 All Inputs (except TDI, TMS, TCK) Hold Time 7 ns 11 Note 4
NOTES:
1. VCC5 should be connected to 3.3 V ±0.3 V in 3.3 V-only systems. All inputs and outputs are TTL level.
2. TCK period ≤ CLK period.
3. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK
period.
4. Pa rameters t30 – t37 are measured from TCK.
Embedded Write-Back Enhanced IntelDX4™ Processor
36
Figure 4. CLK Waveform
Figure 5. Input Setup and Hold Timing
1.5 V
t1
t5
t2
t4t3
0.8 V
CLK 2.0 V
txty
1.5 V
tx = in put setup ti mes
ty = input hold times, ou tput float , valid and hold times
1.5 V
0.8 V
2.0 V
TxTxTxTx
CLK
INV, EADS#
BS8#, BS1 6#,
BOFF#, AHOLD, HOLD
RESET, FLUSH#,
A31-A4
(READ)
A20M#, INTR, NMI, SMI#,
STPCLK#, SRESET, IGNNE#
t12
t14
t13
t15
t18 t19
t20 t21
t22 t23
KEN#, WB/WT#
Embedded Write-Back Enhanced IntelDX4™ Processor
37
Figure 6. Input Setup and Hold Timing
Figure 7. PCHK# Valid Delay Ti ming
T2Tx
CLK
RDY#, BRDY#
D31-D0, DP3–DP0
Tx
1.5 V
1.5 V
t16 t17
t22 t23
RDY#, BRDY#
D31-D0
DP3-DP0
VALID
MIN MAX
t8
PCHK#
T2TxTxTx
CLK
VALID
Embedded Write-Back Enhanced IntelDX4™ Processor
38
Figure 8. Output Valid De lay Timing
Figure 9. Maximum Float Delay Timing
SMIACT#, BLAST#,
PLOCK#
TxTxTxTx
CLK
A2-A31, PWT, PCD,
D31-D0, DP3–DP0
VALID n+1
MAX
t6
VALID n
t10
t8a
BE0-3#, M/IO#,
D/C#, W/R#, ADS#,
LOCK#, BREQ, HLDA,
VALID n+1
MIN
MAX
VALID n
VALID n+1
MIN
MAX
VALID n
MIN
FERR#, CACHE#, HITM#
TxTxTx
CLK
A2-A31, PWT, PCD,
D31-D0, DP3–DP0
BLAST#,
MIN
t6
VALID
BE0-3#, M/IO#,
D/C#, W/R#, ADS#,
LOCK#, CACHE#
PLOCK#
t7
t10 t11
t8a t9
MIN
VALID
MIN
VALID
Embedded Write-Back Enhanced IntelDX4™ Processor
39
Figure 10. TCK Waveform
Figure 11. Test Signal Timing Diagram
0.8 V
t26
t25
2.0 V
TCK t27
t28 t29
0.8 V
2.0 V
t31
t30
TCK
TMS
TDI
TDO
OUTPUT
INPUT
VALID
t32 t33
VALID
t35
VALIDVALID
VALID
t34
t37
t36
1.5 V
Embedded Write-Back Enhanced IntelDX4™ Processor
40
5.4 Capaci tive Derating Curves
These gr aphs are the capacitive derating cur ves for the Embedded Write-Back Enhanced In telDX4 pro c essor.
Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition
Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition
nom+5
nom+4
nom+3
nom+2
nom+1
nom
nom-1
nom-2
Delay (ns)
Note: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.
Capacitive Load (pF)
25 50 75 100 125 150
nom+7
nom+6
A3238-01
nom+5
nom+4
nom+3
nom+2
nom+1
nom
nom-1
nom-2
Delay (ns)
Note: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.
Capacitive Load (pF)
25 50 75 100 125 150
A3237-01
41
Embedded Write-Back Enhanced IntelDX4™ Processor
In a mixed voltage system (processors at 3 volts,
per i ph erals at 5 v olt s) , the bus is dri ve n to 5 v olts by
the peripheral logic. Therefore, the processor must
discharge the capaci tance on the bus from 5 volt s to
0 volts, which takes more time than the 3 volts to 0
volts transition. Inaccurate capacitive derating
impacts timing margins and may result in system
failures under certain load conditions.
When designing for higher loads in mixed voltage
systems, timing margins should be evaluated based
on the derating curves shown in Figure 14. For more
accurate delay prediction, use I/O buffer models.
Figure 14. Typical Loading Delay versus Load Capacitance in Mixed Voltage System
Embedded Write-Back Enhanced IntelDX4™ Processor
42
6.0 MECHANICAL DATA
This section describes the packaging dimensions and thermal specifications for the Embedded Write-Back
Enhanced IntelDX4 processor.
6.1 Package Dimensions
Figure 15. 208-Lead SQFP Package Dimensions
A3260-01
1.14
(ref)
28.0 ± 0.10
30.6 ± 0.25
25.50 (ref)
21.20 ± 0.10
208 157
156
105
10453
52
NOTE: Length measurements same as width measurements
0.50
0.13 + 0.12-0.08
0˚ Min
7˚ Max
0.60 ± 0.10
3.37 ± 0.08
3.70 Max
0.13 Min
0.25 Max
Metal Heat Spreader
1.76 Max
0.10 Max
Tolerance Window for
Lead Skew from Theoretical
True Position
1.30 Ref
.40 Min
Top View
1
Units: mm
Embedded Write-Back Enhanced IntelDX4™ Processor
43
Figure 16. Principal Dimensions and Data for 168-Pin Grid Array Pa ckage
Table 22. 168-Pin Cer amic PGA Packag e Dimensions
Symbol Millimeters Inches
Min Max Notes Min Max Notes
A 3.56 4.57 0.140 0.180
A10.64 1.14 SOLID LID 0.025 0.045 SOLI D LID
A22.8 3. 5 SOLI D LID 0.110 0.140 SOLI D LID
A31.14 1.40 0.045 0.055
B 0.43 0.51 0.017 0.020
D 44.07 44.83 1.735 1.765
D140.51 40.77 1.595 1.605
e12.29 2.79 0.090 0.110
L 2.54 3.30 0.100 0.130
N168 168
S
1
1.52 2.54 0.060 0.100
Embedded Write-Back Enhanced IntelDX4™ Processor
44
Table 23. Ceramic PGA Package Dimension Symbols
Letter or Symbol Description of Dimens ions
A Distance from seati ng plane to highest point of body
A1Distance between se ati ng plane and base plane (lid)
A2Distance from base pl ane to highest point of body
A3Distance from seating plane to bottom of body
B Diameter of terminal lead pin
D Largest overall package dimension of length
D1A body l ength dimensio n, outer lead center to oute r lea d center
e1Linear spacing between true lead position centerlines
L Distance from seating plane to end of lead
S1Ot her body dimension, outer lead c ente r to edge of body
NOTES:
1. Controlling dimension: millimeter.
2. Dimension “e1” (“e”) is non-cumulative.
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inc h.
4. Dimens io ns “B”, “B1” and “C” are nominal.
5. Details of Pin 1 identifier are optional.
6.2 Package Thermal Specifications
The Embedded Write-Back Enhanced IntelDX4
processoris specified for operation when the case
t emp eratur e (TC) is wi thin th e ra nge o f 0°C to 85 °C.
TC may be measured in any environment to
determine whether the processor is within the
specified operating range.
The ambient temperature (TA) can be calculated
from θJC an d θJA from the fo llowing equati ons:
TJ = TC + P * θJC
TA = T J - P * θJA
TC = TA + P * [θJA - θJC]
TA = TC - P * [θJA - θJC]
Where TJ, TA, TC equals Junction, Ambient and
Case Temperature respectively. θ
JC, θJA equals
Junction-to-Case and Junction-to-Ambient thermal
Resistance, respectively. P is defined as Maximum
Power Consumption.
Values for θJA and θJC are given in the following
tables for each product at its maximum operating
freq ue nc i es . Maxim um TA is shown for each pr oduct
operating at its maximum processor frequency (three
times the CLK frequency). Refer to the
Embedded
Intel486™ Processor Family Developer’s Manual
(273021) for a description of the methods used to
measure thes e characteristics.
Embedded Write-Back Enhanced IntelDX4™ Processor
45
Table 24. Thermal Resistance, θJA (°C/W)
θJA vs. Airflow — ft/min. (m/sec)
Package Heat
Sink 0
(0) 200
(1.01) 400
(2.03) 600
(3.04) 800
(4.06) 1000
(5.07)
168-Pin PGA No 17.515.013.011.510.0 9.5
168-Pin PGA Yes 13.5 8.5 6.5 5.5 4.5 4.25
20 8-L ead SQFP No 12.5 10.0 9.0 8.5
208-Lead SQFP Yes 10.5 6.5 5. 0 4.0
Table 25. Thermal Resistance, θJC (°C/W)
Packag e Heat Sink θJC
168- Pi n P GA N o 2.0
168- Pi n P GA Ye s 2.0
208- L ea d SQ FP No 1.2
208- L ea d SQ FP Ye s 0.8
Table 26. Maximum Tambient, TA max (°C)
Airflow — ft/min. (m/sec)
Package Hea t Sink Freq.
(MHz) 0
(0) 200
(1.01) 400
(2.03) 600
(3.04)
168-Pin PGA No 100 18.5 29.0 37.5 44.0
168-Pin PGA Yes 100 35.5 57.0 65.5 70.0
208-Lead SQFP No 10 0 36.5 46. 0 50.0 52. 5
208-Lead SQFP Yes 100 43.5 60.5 67.0 71.0
208-Lead SQFP No 75
208-Lead SQFP Yes 75
