256-Position SPI-Compatible Digital Potentiometer AD5160 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position End-to-end resistance: 5 k, 10 k, 50 k, 100 k Compact SOT-23-8 (2.9 mm x 3 mm) package SPI-compatible interface Power-on preset to midscale Single supply: 2.7 V to 5.5 V Low temperature coefficient: 45 ppm/C Low power, IDD = 8 A Wide operating temperature: -40C to +125C Evaluation board available VDD A CS SPI INTERFACE SDI W CLK WIPER REGISTER B GND Figure 1. APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Gain control and offset adjustment PIN CONFIGURATION W 1 VDD 2 8 A AD5160 7 B 6 CS TOP VIEW CLK 4 (Not to Scale) 5 SDI GND 3 Figure 2. GENERAL DESCRIPTION The AD5160 provides a compact 2.9 mm x 3 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers1 or variable resistors but with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. 1 The wiper settings are controllable through an SPI-compatible digital interface. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch. Operating from a 2.7 V to 5.5 V power supply and consuming less than 5 A allows for usage in portable battery-operated applications. The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com AD5160 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Test Circuits..................................................................................... 12 Functional Block Diagram .............................................................. 1 SPI Interface .................................................................................... 13 Pin Configuration ............................................................................. 1 Theory of Operation ...................................................................... 14 General Description ......................................................................... 1 Programming the Variable Resistor ......................................... 14 Revision History ............................................................................... 2 Programming the Potentiometer Divider ............................... 15 Specifications..................................................................................... 3 SPI-Compatible 3-Wire Serial Bus........................................... 15 Electrical Characteristics--5 k Version .................................. 3 ESD Protection ........................................................................... 15 10 k, 50 k, 100 k Versions .................................................. 4 Power-Up Sequence ................................................................... 15 Timing Characteristics--All Versions ....................................... 5 Layout and Power Supply Bypassing ....................................... 15 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 16 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 16 Pin Configuration and Function Descriptions ............................. 7 REVISION HISTORY 11/14--Rev. B to Rev. C Changes to Ordering Guide .......................................................... 16 5/09--Rev. A to Rev. B Changes to Ordering Guide .......................................................... 16 1/09--Rev. 0 to Rev. A Deleted Shutdown Supply Current Parameter and Endnote 7, Table 1 ............................................................................ 3 Changes to Resistor Noise Voltage Density Parameter, Table 1 ................................................................................................ 3 Deleted Shutdown Supply Current Parameter and Endnote 7, Table 2 ............................................................................ 4 Changes to Resistor Noise Voltage Density Parameter, Table 2 ................................................................................................ 4 Added Endnote to Table 3 ............................................................... 5 Changes to Table 4 ............................................................................ 6 Changes to the Rheostat Operation Section ............................... 14 Deleted Terminal Voltage Operating Range Section and Figure 41, Renumbered Figures Sequentially ............................. 13 Changes to Figure 40 and Figure 41............................................. 15 Changes to Ordering Guide .......................................................... 16 5/03--Revision 0: Initial Version Rev. C | Page 2 of 16 Data Sheet AD5160 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--5 k VERSION VDD = 5 V 10%, or 3 V 10%; VA = +VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS Rheostat Mode Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance Potentiometer Divider Mode Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance A, Capacitance B6 Capacitance W6 Common-Mode Leakage DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ1 Max Unit R-DNL R-INL RAB RAB/T RW RWB, VA = no connect RWB, VA = no connect TA = 25C VAB = VDD, wiper = no connect -1.5 -4 -20 0.1 0.75 +1.5 +4 +20 LSB LSB % ppm/C 45 50 120 Specifications apply to all VRs N DNL INL VW/T VWFSE VWZSE Code = 0x80 Code = 0xFF Code = 0x00 VA, VB, VW CA,B CW ICM f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = VB = VDD/2 VIH VIL VIH VIL IIL CIL -1.5 -1.5 -6 0 0.1 0.6 15 -2.5 +2 GND 8 +1.5 +1.5 0 +6 VDD 45 60 1 2.4 0.8 VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 2.1 0.6 1 5 VDD RANGE IDD PDISS PSS 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, code = midscale 3 BW_5K THDW tS eN_WB RAB = 5 k, code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, VB = 0 V, 1 LSB error band RWB = 2.5 k 1.2 0.05 1 6 0.02 5.5 8 0.2 0.05 Bits LSB LSB ppm/C LSB LSB V pF pF nA V V V V A pF V A mW %/% MHz % s nV/Hz Typical specifications represent average readings at +25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 1 2 Rev. C | Page 3 of 16 AD5160 Data Sheet 10 k, 50 k, 100 k VERSIONS VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS Rheostat Mode Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance Potentiometer Divider Mode Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance A, Capacitance B6 Capacitance W6 Common-Mode Leakage DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 8 Bandwidth -3 dB Total Harmonic Distortion Symbol Conditions Min Typ1 Max Unit R-DNL R-INL RAB RAB/T RWB, VA = no connect RWB, VA = no connect TA = 25C VAB = VDD, Wiper = no connect VDD = 5 V Specifications apply to all VRs -1 -2 -15 0.1 0.25 +1 +2 +15 LSB LSB % ppm/C 120 8 +1 +1 Bits LSB LSB ppm/C 0 3 LSB LSB VDD 45 V pF 60 pF 1 nA RW N DNL INL VW/T Code = 0x80 VWFSE VWZSE Code = 0xFF Code = 0x00 VA,B,W CA,B CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSS BW THDW VW Settling Time (10 k/50 k/100 k) tS Resistor Noise Voltage Density eN_WB 45 50 -1 -1 0.1 0.3 15 -3 0 -1 1 GND f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = VB = VDD/2 2.4 0.8 VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 2.1 0.6 1 5 2.7 5.5 8 0.2 0.05 V V V V A pF V A mW %/% VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, code = midscale 3 RAB = 10 k/50 k/100 k, Code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VA = 5 V, VB = 0 V, 1 LSB error band RWB = 5 k 600/100/40 0.05 kHz % 2 s 9 nV/Hz 0.02 Typical specifications represent average readings at +25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 1 2 Rev. C | Page 4 of 16 Data Sheet AD5160 TIMING CHARACTERISTICS--ALL VERSIONS VDD = +5V 10%, or +3V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted. Table 3. Parameter SPI INTERFACE TIMING CHARACTERISTICS1, 2 Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CS Setup Time CS High Pulse Width CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time Symbol fCLK tCH, tCL tDS tDH tCSS tCSW tCSH0 tCSH1 Conditions Specifications apply to all parts Min Clock level high or low 20 5 5 15 40 0 0 Typ1 Max Unit 25 MHz ns ns ns ns ns ns ns See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 2 Guaranteed by design and not subject to production test. 1 Rev. C | Page 5 of 16 AD5160 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = +25C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Parameter VDD to GND VA, VB, VW to GND Maximum Current IMAX1 IWB, IWA Pulsed IWB, IWA Continuous 5 k, 10 k 50 k 100 k Digital Inputs and Output Voltage to GND Temperature Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Thermal Resistance (SOT-23 Package)2 JA Thermal Impedance JC Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating -0.3 V to +7 V VDD 20 mA ESD CAUTION 4.7 mA 0.95 mA 0.48 mA 0 V to +7 V -40C to +125C 150C -65C to +150C 206C/W 91C/W 260C 10 sec to 40 sec Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA. 1 Rev. C | Page 6 of 16 Data Sheet AD5160 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W 1 VDD 2 8 A AD5160 7 B 6 CS TOP VIEW CLK 4 (Not to Scale) 5 SDI GND 3 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin 1 2 3 4 5 6 7 8 Mnemonic W VDD GND CLK SDI CS B A Description W Terminal. Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Serial Data Input. Chip Select Input, Active Low. When CS returns high, data loads into the DAC register. B Terminal. A Terminal. Rev. C | Page 7 of 16 AD5160 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 5V 0.8 -40C +25C +85C +125C 0.8 0.6 POTENTIOMETER MODE DNL (LSB) RHEOSTAT MODE INL (LSB) 3V 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 0 32 64 CODE (Decimal) 160 192 224 256 Figure 7. DNL vs. Code, VDD = 5 V 1.0 1.0 0.8 0.8 5V 3V 0.6 POTENTIOMETER MODE INL (LSB) RHEOSTAT MODE DNL (LSB) 128 CODE (Decimal) Figure 4. R-INL vs. Code vs. Supply Voltages 0.4 0.2 0 -0.2 -0.4 -0.6 5V 3V 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 -1.0 0 32 64 96 128 160 192 224 0 256 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 5. R-DNL vs. Code vs. Supply Voltages Figure 8. INL vs. Code vs. Supply Voltages 1.0 1.0 _40C +25C +85C +125C 0.6 5V 0.8 POTENTIOMETER MODE DNL(LSB) 0.8 POTENTIOMETER MODE INL (LSB) 96 0.4 0.2 0 -0.2 -0.4 -0.6 3V 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 -1.0 0 32 64 96 128 160 192 224 256 0 CODE (Decimal) 32 64 96 128 160 192 CODE (Decimal) Figure 6. INL vs. Code, VDD = 5 V Figure 9. DNL vs. Code vs. Supply Voltages Rev. C | Page 8 of 16 224 256 Data Sheet AD5160 1.0 2.5 RHEOSTAT MODE INL (LSB) 0.8 0.6 ZSE, ZERO-SCALE ERROR (A) -40 C +25C +85C +125C 0.4 0.2 0 -0.2 -0.4 -0.6 2.0 VDD = 5.5V 1.5 VDD = 2.7V 1.0 0.5 -0.8 0 -40 -1.0 0 32 64 96 128 192 160 224 256 0 80 120 Figure 13. Zero-Scale Error vs. Temperature Figure 10. R-INL vs. Code, VDD = 5 V 1.0 10 _40C 0.8 +25C +85C +125C 0.6 IDD SUPPLY CURRENT (A) RHEOSTAT MODE DNL (LSB) 40 TEMPERATURE (C) CODE (Decimal) 0.4 0.2 0 -0.2 -0.4 VDD = 5.5V 1 -0.6 VDD = 2.7V -0.8 -1.0 0 32 64 96 128 160 192 224 0.1 -40 256 0 40 80 120 TEMPERATURE (C) CODE (Decimal) Figure 11. R-DNL vs. Code, VDD = 5 V Figure 14. Supply Current vs. Temperature 2.5 70 IA SHUTDOWN CURRENT (nA) FSE, FULL-SCALE ERROR (LSB) 60 2.0 1.5 VDD = 2.7V 1.0 VDD = 5.5V 0.5 50 40 30 VDD = 5V 20 10 0 -40 0 40 80 0 -40 120 TEMPERATURE (C) 0 40 80 TEMPERATURE (C) Figure 15. Shutdown Current vs. Temperature Figure 12. Full-Scale Error vs. Temperature Rev. C | Page 9 of 16 120 RHEOSTAT MODE TEMPCO (ppm/C) AD5160 Data Sheet 200 REF LEVEL 0.000dB 0 150 -6 0x80 -12 0x40 -18 0x20 100 /DIV 6.000dB 0x10 -24 50 MARKER 510 634.725Hz MAG (A/R) -9.049dB 0x08 -30 0x04 -36 0 0x02 0x01 -42 -48 -50 -54 0 32 64 96 128 160 192 224 256 -60 CODE (Decimal) 1k START 1 000.000Hz Figure 16. Rheostat Mode Tempco RWB/T vs. Code 1M 100k STOP 1 000 000.000Hz Figure 19. Gain vs. Frequency vs. Code, RAB = 10 k 160 POTENTIOMETER MODE TEMPCO (ppm/C) 10k 140 REF LEVEL 0.000dB 0 120 -6 /DIV 6.000dB 0x80 0x40 -12 100 0x20 -18 80 0x10 -24 60 0x08 -30 40 0x04 -36 20 MARKER 100 885.289Hz MAG (A/R) -9.014dB 0x02 -42 0x01 0 -48 -20 -54 0 32 64 96 128 160 192 224 256 -60 CODE (Decimal) 1k START 1 000.000Hz Figure 17. Potentiometer Mode Tempco VWB/T vs. Code REF LEVEL 0.000dB 0 /DIV 6.000dB -6 0x80 -12 0x40 -18 0x20 10k Figure 20. Gain vs. Frequency vs. Code, RAB = 50 k MARKER 1 000 000.000Hz MAG (A/R) -8.918dB REF LEVEL 0.000dB 0 /DIV 6.000dB -6 0x80 -12 0x40 -18 0x20 -24 0x10 0x04 -30 0x08 0x02 0x01 -36 0x04 -42 -42 0x02 -48 -48 -54 -54 0x10 -24 100k 1M STOP 1 000 000.000Hz MARKER 54 089.173Hz MAG (A/R) -9.052dB 0x08 -30 -36 -60 0x01 -60 1k START 1 000.000Hz 10k 100k 1M STOP 1 000 000.000Hz 1k START 1 000.000Hz Figure 18. Gain vs. Frequency vs. Code, RAB = 5 k 10k 100k 1M STOP 1 000 000.000Hz Figure 21. Gain vs. Frequency vs. Code, RAB = 100 k Rev. C | Page 10 of 16 Data Sheet REF LEVEL -5.000dB AD5160 /DIV 0.500dB -5.5 5k - 1.026 MHz 10k - 511 MHz 50k - 101 MHz 100k - 54 MHz -6.0 -6.5 -7.0 1 VW -7.5 -8.0 CLK -8.5 R = 50k 2 R = 5k -9.0 R = 10k R = 100k -9.5 Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V -10.0 -10.5 10k 100k 1M START 1 000.000Hz 10M STOP 1 000 000.000Hz Figure 22. -3 dB Bandwidth @ Code = 0x80 Figure 25. Digital Feedthrough 60 CODE = 0x80, VA= VDD, VB = 0V VA = 5V VB = 0V PSRR (dB) 40 1 VW PSRR @ VDD = 3V DC 10% p-p AC CS 20 2 Ch 1 PSRR @ VDD = 5V DC 10% p-p AC 0 100 1k 10k 100k 100mV BW Ch 2 5.00 V BW M 200ns A CH1 152mV 1M FREQUENCY (Hz) Figure 26. Midscale Glitch, Code 0x80 to Code 0x7F Figure 23. PSRR vs. Frequency 900 VDD = 5V 800 VA = 5V VB = 0V 700 IDD (A) 600 500 1 400 CS 300 CODE = 0xFF 2 200 Ch 1 100 0 10k VW CODE = 0x55 100k 1M FREQUENCY (Hz) 5.00V BW Ch 2 5.00 V BW M 200ns A CH1 3.00 V 10M Figure 24. IDD vs. Frequency Figure 27. Large Signal Settling Time, Code 0xFF to Code 0x00 Rev. C | Page 11 of 16 AD5160 Data Sheet TEST CIRCUITS Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables. 5V V+ = VDD 1LSB = V+/2N DUT A OP279 VIN W V+ B OFFSET GND VMS VOUT W A DUT B OFFSET BIAS Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 33. Test Circuit for Noninverting Gain NO CONNECT A +15V DUT A W IW VIN W AD8610 OFFSET GND B 2.5V RSW = DUT DUT VMS2 -15V Figure 34. Test Circuit for Gain vs. Frequency Figure 29. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) W W B 0.1V ISW B VMS1 0.1V ISW CODE = 0x00 I W = VDD /R NOMINAL VW VOUT B VMS A DUT RW = [VMS1 - VMS2]/I W VSS TO VDD Figure 35. Test Circuit for Incremental On Resistance Figure 30. Test Circuit for Wiper Resistance NC VA V+ = VDD 10% VDD PSRR (dB) = 20 LOG A V+ W PSS (%/%) = B V MS% V (V MS ) DD V DD% VDD DUT A VSS GND B VCM A DUT B 5V W OP279 NC = NO CONNECT Figure 36. Test Circuit for Common-Mode Leakage Current Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR) OFFSET GND ICM VMS NC VIN W VOUT OFFSET BIAS Figure 32. Test Circuit for Inverting Gain Rev. C | Page 12 of 16 Data Sheet AD5160 SPI INTERFACE 1 Table 6. Serial Data-Word Format B7 D7 MSB 27 B6 D6 B5 D5 B4 D4 SDI B3 D3 B2 D2 B1 D1 B0 D0 LSB 20 D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 RDAC REGISTER LOAD 1 CS 0 1 VOUT 0 Figure 37. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 tCH 1 tDS tCH tCS1 CLK 0 tCL tCSHO tCSH1 tCSS 1 CS tCSW 0 tS VDD VOUT 1LSB 0 Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. C | Page 13 of 16 AD5160 Data Sheet THEORY OF OPERATION The AD5160 is a 256-position digitally controlled variable resistor (VR) device. The general equation determining the digitally programmed output resistance between W and B is An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 5 k, 10 k, 50 k, and 100 k. The final two or three digits of the model number as listed in the Ordering Guide section determine the nominal resistance value, for example, in model AD5160BRJZ10, the 10 represents 10 k; and in AD5160BRJZ50, the 50 represents 50 k. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 10 k part is used, the first connection of the wiper starts at the B terminal for Data 0x00. Because there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between Terminal W and Terminal B. The second connection is the first tap point, which corresponds to 99 (RWB = RAB/256 + RW = 39 + 60 ) for Data 0x01. The third connection is the next tap point, representing 138 (2 x 39 + 60 ) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 (RAB - 1 LSB + RW). Figure 39 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string is not accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. RWB (D ) D7 D6 D5 D4 D3 D2 D1 D0 (1) where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open circuited, the following output resistance RWB is set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance D (Dec.) 255 128 1 0 RWB () 9961 5060 99 60 Output State Full Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Note that in the zero-scale condition, a finite wiper resistance of 60 is present. Take care to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled complementary resistance (RWA). When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is A RS D R AB R W 256 RWA (D ) 256 D R AB RW 256 (2) For RAB = 10 k and the B terminal is open circuited, the following output resistance RWA is set for the indicated RDAC latch codes. RS RS W RDAC LATCH RS AND DECODER B Figure 39. Equivalent RDAC Circuit Table 8. Codes and Corresponding RWA Resistance D (Dec.) 255 128 1 0 RWA () 99 5060 9961 10,060 Output State Full Scale Midscale 1 LSB Zero Scale Typical device-to-device matching is process lot dependent and may vary by up to 30%. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/C temperature coefficient. Rev. C | Page 14 of 16 Data Sheet AD5160 PROGRAMMING THE POTENTIOMETER DIVIDER ESD PROTECTION Voltage Output Operation All digital inputs are protected with a series input resistor and parallel Zener ESD structures are shown in Figure 40 and Figure 41. This applies to SDI, CLK, and CS, which are the digital input pins. The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D ) D 256 D VA VB 256 256 (3) For a more accurate calculation, which includes the effect of wiper resistance, VW can be found as VW (D ) R (D ) RWB (D ) V A WA VB 256 256 (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors (RWA and RWB) and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/C. SPI-COMPATIBLE 3-WIRE SERIAL BUS The AD5160 contains a 3-wire SPI-compatible digital interface (SDI, CS, and CLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 6. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 37). 340 LOGIC GND Figure 40. ESD Protection of Digital Pins A,B,W GND Figure 41. ESD Protection of Resistor Terminals POWER-UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at the A, B, and W terminals, it is important to power VDD/GND before applying any voltage to the A, B, and W terminals; otherwise, the diode forward biases such that VDD is powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA/B/W. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to employ compact, minimum lead length layout design. Keep the leads to the inputs as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Bypass supply leads to the device with disc or chip ceramic capacitors of 0.01 F to 0.1 F. To minimize any transient disturbance and low frequency ripple, apply low ESR 1 F to 10 F tantalum or electrolytic capacitors at the supplies (see Figure 42). To minimize the ground bounce, join the digital ground remotely to the analog ground at a single point. The data setup and data hold times in the specification table determine the valid timing requirements. The AD5160 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. VDD VDD C1 C3 + 10F 0.1F AD5160 GND Figure 42. Power Supply Bypassing Rev. C | Page 15 of 16 AD5160 Data Sheet OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.22 MAX 0.08 MIN SEATING PLANE 0.38 MAX 0.22 MIN 8 4 0 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-BA 0.60 0.45 0.30 12-16-2008-A 1.30 1.15 0.90 Figure 43. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD5160BRJZ5-R2 AD5160BRJZ5-RL7 AD5160BRJZ10-R2 AD5160BRJZ10-RL7 AD5160BRJZ50-R2 AD5160BRJZ50-RL7 AD5160BRJZ100-R2 AD5160BRJZ100-RL7 EVAL-AD5160DBZ RAB () 5k 5k 10 k 10 k 50 k 50 k 100 k 100 k Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board 1 Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 The AD5160 contains 2532 transistors. Die size: 30.7 mil x 76.8 mil = 2358 sq. mil. Z = RoHS Compliant Part. 3 The EVAL-AD5160DBZ board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options. 2 (c)2003-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03434-0-11/14(C) Rev. C | Page 16 of 16 Branding D6Q D6Q D09 D09 D8J D8J D0B D0B