CY7C1338B
PRELIMINARY
4
Functional Description (continued)
Single Write Accesses Init iated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
count er/con trol logic and deli ver ed t o the RAM cor e. The wri te
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active ( see W rite
Cycle Descr iptions table for appropr iate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 control s DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasser ted and the I/Os must be three-stated pri or to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines ar e three-stated once a write cycle i s detected, re-
gardless of the state of OE .
Single Wri te Accesses Initiated by ADSC
This writ e acc ess is i nitiat ed when the f oll owing c ondit ions ar e
satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BW E, and BW[3:0])
indi cate a write access. ADSC is ignored if ADS P is active LOW.
The addr ess es presen ted are loa ded int o th e address regist er
and the burst counter/cont rol logic and delivered to the RAM
core. The informatio n presented to DQ[31:0] will be written into
the spe cified add ress lo cation. Byte writes are allow ed. During
byte writes, BW0 contr ols DQ[7:0], BW1 control s DQ[15:8], BW2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os a re
thr ee-stat ed when a write i s detec ted, ev en a by te write. Si nce
thi s is a comm on I/O de vice, t he asynchronous OE input signal
mu st be deass erte d and the I /Os mus t be thr ee-st ated prio r to
the p resentation of data to DQ[31:0]. As a safety precaution, the
data lines ar e three-stated once a write cycle i s detected, re-
gardless of the state of OE .
Single Read Accesses
A single read access is initiated whe n the follo wing conditi ons
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the wri te input s must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control lo gic and presented to the m em ory core. If the
OE input is asserted LO W , the request ed data will be av ailabl e
at the data outputs a maximum to tCDV after clock rise. ADSP
is i gnored if CE1 is HIGH .
Burst Se quences
The CY7C1338B provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LO W on MODE wi ll se lect a line ar bu rst se quenc e. A HI GH on
MODE will select an interleaved burst order. Leaving M ODE
unconnected will cause the device to default to a interleaved
burst sequence .
17, 4 0, 67,
90 VSS Ground G round f or the I/O circu it ry of the de vice. Should be connected to gr ound of the sy s-
tem.
5, 10, 14,
21, 2 6, 55,
60, 71, 76
VSSQ Ground G round f or the de vice. Should be connected to gr ound of the sy stem.
4, 11, 20,
27, 5 4, 61,
70, 77
VDDQ I/O Po wer
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
1,16, 30,
50–51, 66,
80
NC -No connects.
38, 3 9, 42,
43 DNU -Do not use pins. Should be left unconnected or tied LOW.
Pin Descriptions (continued)
TQFP Pin
Number Name I/O Description
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1 , Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 2. Counter Implementation for a Linear Seque nce
First
Address Second
Address Third
Address Fourth
Address
AX + 1, AxAX + 1, AxAX + 1, AxAX + 1, A x
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10