Product Specification PE42510A SPDT High Power UltraCMOS(R) Reflective RF Switch 30 - 2000 MHz (R) 50 Watt P1dB compression point 10 Watts <8:1 VSWR (Normal Operation) 29 dB Isolation @ 800 MHz <0.3 dB Insertion Loss at 800 MHz 2fo and 3fo < -84 dBc @ 42.5 dBm ESD rugged to 2.0 kV HBM 32-lead 5x5x0.85 mm QFN package de The PE42510A is manufactured on Peregrine's UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Features No blocking capacitors required gn s The following specification defines an SPDT (single pole double throw) switch for use in cellular and other wireless applications. The PE42510A uses Peregrine's UltraCMOS(R) process and it also features HaRPTM technology enhancements to deliver high linearity and exceptional harmonics performance. HaRPTM technology is an innovative feature of the UltraCMOS(R) process providing upgraded linearity performance. si Product Description Figure 1. Functional Diagram Figure 2. Package Type rn ew 32-lead 5x5x0.85 mm fo 71-0014 Table 1. Electrical Specifications @ 25C, VDD = 3.3V (ZS = ZL = 50 ) unless otherwise noted Parameter Conditions Min Typ Max Units 0.6 0.7 dB dB 30 MHz 1 GHz 1 GHz < 2 GHz 0.4 0.5 0.1 dB Input Compression Point 800 MHz, 50% duty cycle 45.4 dBm Isolation (Supply Biased): RF to RFC 800 MHz 25 29 dB Unbiased Isolation: RF - RFC, VDD, V1=0V 27 dBm, 800 MHz 5 N ot RF Insertion Loss RF (Active Port) Return Loss 15 dB 22 dB 2nd Harmonic 3rd Harmonic 800 MHz @ +42.5 dBm -84 -81 dBc Switching Time 2,3 50% of CTRL to 10/90% of RF 25 31 s Notes: 1. The device was matched with 1.6 nH inductance per RF port 2. For high power applications, harmonics settling needs to be accounted for. Harmonics settling time is defined to be 50% of CTRL to 2fo/3fo within 3 dB of final value 3. For RF input power (50 ) > 31 dBm, and operation above 30 MHz, the switching time and harmonics settling time is 100 s Max Document No. 70-0266-03 www.psemi.com (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE42510A Product Specification GND GND GND GND RFC GND GND GND 32 31 30 29 28 27 26 25 Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Parameter Min Frequency Range 24 GND RF Input Power1 (VSWR 8:1) RF1 2 23 RF2 RF Input Power2 (VSWR 8:1) 22 GND VDD Power Supply Voltage 21 GND 16 GND N/C 17 15 8 GND GND 14 GND GND 18 13 7 CTRL GND 12 GND VDD 19 11 6 N/C GND 10 GND GND 20 9 5 IDD Power Supply Current Control Voltage High GND GND Exposed Ground Paddle Control Voltage Low Operating Temperature Range (Case) Tj Operating Junction Temperature Notes: 1. Supply biased 2. Supply unbiased N V 90 170 A 1.4 V 0.4 V 85 C 140 C -40 Parameter/Conditions The Moisture Sensitivity Level rating for the 5x5x0.85 mm QFN package is MSL3. (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Min Max Units Voltage on Any DC Input -0.3 TST Storage Temperature Range -65 TCASE Maximum Case Temperature VI Tj PIN PD VESD Peak Maximum Junction Temperature (10 seconds max) RF Input Power (VSWR 20:1, 10 seconds) RF Input Power (50 ) RF Input Power, Unbiased (VSWR 20:1) Maximum Power Dissipation Due to RF Insertion Loss ESD Voltage (HBM, MIL_STD 883 Method 3015.7) 4 VDD+ 0.3 150 V C 85 C 200 C 40 dBm 45 dBm 27 dBm 2.2 W 2000 V V Absolute Maximum Ratings Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions (R) When handling this UltraCMOS device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance (R) Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 5. Control Logic Truth Table Moisture Sensitivity Level Page 2 of 7 dBm -0.3 ew Ground RF1 port Ground Ground Ground Ground Ground Ground Ground Ground No Connect Nominal 3.3 V supply connection Control Ground Ground Do Not Connect Ground Ground Ground Ground Ground Ground RF2 port. Ground Ground Ground Ground Common RF port for switch Ground Ground Ground Ground Exposed ground paddle rn GND RF1 GND GND GND GND GND GND GND GND N/C VDD CTRL GND GND N/C GND GND GND GND GND GND RF2 GND GND GND GND RFC GND GND GND GND GND 27 Power Supply Voltage VDD fo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 paddle Symbol Description ot Pin Name dBm Table 4. Absolute Maximum Ratings Table 2. Pin Descriptions Pin No. MHz 40 3.4 si 4 2000 3.3 de GND 3.2 Units gn s 1 3 Max 30 GND GND Typ Path CTRL RFC - RF1 H RFC - RF2 L Document No. 70-0266-03 UltraCMOS(R) RFIC Solutions PE42510A Product Specification Figure 4. Evaluation Board Layouts Evaluation Kit The PE42510A Evaluation Kit board was designed to ease customer evaluation of the PE42510A RF switch. rn si de ew The RF common port (RFC) is connected through a 50 transmission line via the top SMA connector, J1. RF1 and RF2 paths are also connected through 50 transmission lines via SMA connectors. A 50 through transmission line is available via SMA connectors J8 and J9. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. An openended 50 transmission line is also provided at J7 for calibration if needed. gn s DC power is supplied through J10, with VDD on pin 9, and GND on the entire lower row of even numbered pins. To evaluate a switch path, add or remove jumpers on CTRL/V1 (pin 3) using Table 5 (adding a jumper pulls the CMOS control pin low and removing it allows the on-board pull-up resistor to set the CMOS control pin high). J10 pins 1, 11, and 13 are N/C. 101-0314-02 N ot fo Figure 5. Evaluation Board Schematic 102-0383-02 Document No. 70-0266-03 www.psemi.com (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE42510A Product Specification Figure 9. RFC-RF Isolation, +25C Figure 7. RF-RFC Insertion Loss, +25C Figure 10. RF Return Loss, VDD = 3.3V fo rn ew de si gn s Figure 6. RF-RFC Insertion Loss, VDD = 3.3V Figure 11. RF Return Loss, +25C N ot Figure 8. RFC-RF Isolation, VDD = 3.3V (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 Document No. 70-0266-03 UltraCMOS(R) RFIC Solutions PE42510A Product Specification Thermal Data Typ fo 24.0 Max Units C/W GND GND GND RFC GND GND GND 31 30 29 28 27 26 25 RF1 2 23 RF2 GND 3 22 GND 21 GND 20 GND 19 GND 18 GND 17 GND 15 16 N/C 14 GND GND 13 8 CTRL GND 12 7 si GND VDD 6 11 GND N/C 5 10 GND GND 4 E xposed G ro u n d P a d d le 9 GND gn s GND Figure 13. Maximum Junction Temperature Max Junction Temperature (C) Min Theta JC (+85C) rn Table 6. Theta JC Parameter 24 ew Note that both of these charts assume that the case (GND slug) temperature is held at 85C. Special consideration needs to be made in the design of the PCB to properly dissipate the heat away from the part and maintain the 85C maximum case temperature. It is recommended to use best design practices for high power QFN packages: multi-layer PCBs with thermal vias in a thermal pad soldered to the slug of the package. Special care also needs to be made to alleviate solder voiding under the part. 1 GND Figure 13 shows the estimated maximum junction temperature of the part for similar conditions. GND de Figure 12 shows the estimated power dissipation for a given incident RF power level. Multiple curves are presented to show the effect of poor VSWR conditions. VSWR conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. GND Though the insertion loss for this part is very low, when handling high power RF signals, the part can get quite hot. 32 Figure 12. Power Dissipation 145 140 135 1:1 VS WR (50 Ohm Load) 130 2:1 VS WR (25 Ohm Load) 8:1 VS WR (6. 25 Ohm Load) 125 20: 1 VSWR (2.5 Ohm Load) 120 INF:1 V SWR (0 Ohm Load) Reliability Limit 115 110 105 100 95 90 85 30 31 3 2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Note: Case temperature = 85C N ot RF Power (dBm) Document No. 70-0266-03 www.psemi.com (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE42510A Product Specification Figure 14. Package Drawing Note: Not for electrical connection. Corner detail is tied to paddle and should not be isolated on PCB board 19-0146 rn ew de si gn s See Note below = Pin 1 designator 42510A = Six digit part number YYWW = Date Code, last two digits of the year and work week ZZZZZZ = Six digits of the lot number N ot 42510A YYWW ZZZZZZ fo Figure 14. Top Marking Specification 17-0091-01 (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Document No. 70-0266-03 UltraCMOS(R) RFIC Solutions PE42510A Product Specification si gn s Figure 15. Tape and Reel Specs Notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole de Ao = 5.25 0.1 mm Bo = 5.25 0.1 mm Ko = 1.10 0.1 mm rn ew Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Order Code PE42510AMLI Description Package Shipping Method Parts in Tubes or Cut Tape Green 32-lead 5x5mm QFN 73 units/Tube Parts on Tape and Reel Green 32-lead 5x5mm QFN 500 units/T&R Evaluation Kit 1/Box ot PE42510AMLI-X fo Table 7. Ordering Information Evaluation Kit N EK42510-01 Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. Document No. 70-0266-03 www.psemi.com No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2008-2012 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7