LS83A National Semiconductor 54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry General Description These full adders perform the addition of two 4-bit binary numbers. The sum (2) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal took ahead across all four bits. This provides the system designer with partial look- ahead performance at the econemy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accom- plished without the need for logic or level inversion. Features @ Full-carry look-ahead across the four bits m Systems achieve partial look-ahead performance with the economy of ripple carry B Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns @ Typical power dissipation per 4-bit adder 95 mW @ Alternate Military/Aerospace device (54LS83A) is avail- able. Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-in-Line Package B4 r4 sa 16 15 14 co GND BI Al uy L4 C4 co mt 84 a Ad r3 A3 BS Bi Al Ti A2e =2 B2 1 2 3 4 Aa 53 AB B3 5 6 T 8 Veo 2 B2 A2 TL/F/6378-1 Order Number 54LS83ADMGB, 54LS83AFMQGB, DM54LS83AJ, DM54LS83AW, DM74LS83AWM or DM74LS83AN See NS Package Number J16A, M16B, N16E or W16AAbsolute Maximum Ratings ote) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Otfice/Distributors for availability and specitications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range DMS54LS and 54LS 56C to + 125C DM74LS Storage Temperature Range OC to +70C 65C to + 150C Recommended Operating Conditions Note: The Absolute Maximum FAatings are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated ai these limits. The Parametric values defined in the Electrical Characteristics" lable are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Symbol Parameter DMS4LS83A4 DM74LS83A Units Min Nom Max Min Nom Max Voc Supply Voltage 45 5 5.5 4.75 5 5.25 Vv Vin High Level Input Voltage 2 2 Vv Vir Low Level Input Voltage 0.7 0.8 Vv lou High Level Output Current 0.4 -0.4 mA lo. Low Level Output Current 4 8 mA Ta Free Air Operating Temperature 55 125 0 70 C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 1) Vi Input Clamp Voitage Voc = Min, || = 18mA 1.5 Vv Vou High Level Output Voc = Min, low = Max DM54 2.5 3.4 V Voltage Vit = Max, Viq = Min DM74 27 3.4 VoL Low Level Output Voce = Min, Io. = Max DM54 0.25 0.4 Voltage Vit = Max, Viq = Min DM74 0.35 0.5 Vv lon = 4mA, Voc = Min DM74 0.25 0.4 I Input Current @ Max Voc = Max AorB 0.2 mA Input Voltage Vv) = 7V co 04 WH High Level Input Voc = Max AorB 40 A Current Vi = 2.7V co 20 p he Low Level Input Voc = Max AorB -0.8 mA Current Vv, = 0.4V co -0.4 los Short Circuit Voc = Max DM54 20 100 Output Current (Note 2) DM74 30 ~ 400 mA loci Supply Current Voc = Max (Note 3) 19 34 mA Ioce Supply Current Voc = Max (Note 4) 22 39 mA Note 1: All typicals are at Vog = 5V, Ta = 25C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: Icc1 is measured with all ouiputs open, all B inputs low and all other inputs at 4.5V, or all inputs at 4.5V. Note 4: loge is measured with all outputs open and ail inputs grounded. 2-91 vessTLS83A Switching Characteristics at Veo = 5v and T, = 25C (See Section 1 for Test Waveforms and Output Load) RL = 2k9 From (input) _ _ Symbol Parameter To (Output) CL = 15 pF C, = 50 pF Units Min Max Min Max tpLH Propagation Delay Time CO to 24 2B ns Low to High Level Output 21 or 2 tpHL Propagation Delay Time CO to 24 30 ns High to Low Level Output 21 or 22 tpLH Propagation Delay Time C0 to Low to High Level Output =3 24 26 ns {PHL Propagation Delay Time CO to High to Low Level Output =3 24 30 ns tPLH Propagation Delay Time CO to Low to High Level Output =4 24 26 ns teHL Propagation Delay Time CO to High to Low Level Output 24 24 30 ns teLy Propagation Delay Time Aj, By Low to High Level Output to 3; 24 28 ns {PHL Propagation Delay Time Aj, Bj High to Low Level Output to 5; 24 30 ns teLH Propagation Delay Time CO to Low to High Level Output C4 wv 24 ns {PHL Propagation Delay Time CO to 17 25 ns High to Low Level Output C4 tPLH Propagation Delay Time Aj, Bi 17 24 ns Low to High Level Output to C4 tPHE Propagation Delay Time Aj, Bj 17 26 ns High to Low Level Output to C4 Truth Tabie Outputs Inputs When Co = L When CO = H When C2 =L When C2 =H At Bi A2 B2 21 22 c2 z1 =2 C2 AS B3 A4 B4 23 24 c4 =3 =4 C4 L L L L L L L H L L H L L L H L L L H L L H L L H L L L H L H H L L L H L H H L L L H L L H L H H L H L H L H H L L L H L H H L H H L L L H H H H L L L H H L H L L L H L H L H H L H L L H H H L L L H L H L H H H L L L H H H L H L L H H L H L L H H L L H H L H H L H H H L H L H H L H H H H L H L H H H H H H L H H H H H H = High Level, L = Low Level TL/F/6378-3 Note: Inout conditions at A1, B1, A2, 82, and CO are used to determine outputs 1 and 2 and the value of tha internal carry C2. The values at C2, A3, B3, Ad, and 84 are then used to determine outputs 53, 4, and C4. 2-92Logic Diagram Ad 83 A3 B2 A2 (11) B1 (16) 1 (13) co TL/F/6376-2 2-93 VEessT