DS90LV031AQML DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver Literature Number: SNLS204 DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver General Description Features The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV031A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRISTATE(R) function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. High impedance LVDS outputs with power-off Low differential skew Low propagation delay 3.3V power supply design 350 mV differential signaling Low power dissipation Interoperable with existing 5V LVDS devices Compatible with IEEE 1596.3 SCI LVDS standard Compatible with proposed TIA/EIA-644 LVDS standard Pin compatible with DS26C31 Typical Rise/Fall times of 800pS. Typical Tri-State Enable/Disable delays of less than 5nS. Ordering Information NS Part Number SMD Part Number DS90LV031AW-QML 5962-9865101QFA NS Package Number W16A DS90LV031AWGQML 5962-9865101QXA WG16A Package Description 16LD Ceramic Flatpack 16LD Ceramic SOIC DS90LV031AW-MLS W16A DS90LV031AWGMLS WG16A 16LD Ceramic SOIC DS90LV031-MDS (Note 7) BARE DIE Connection Diagram 16LD Ceramic Flatpack Functional Diagram Dual-In-Line Package Pictured 20163801 See NS Package Number WG16A or W16A 20163802 TRI-STATE(R) is a registered trademark of National Semiconductor Corporation. (c) 2011 Texas Instruments Incorporated 201638 www.ti.com DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver November 15, 2011 DS90LV031AQML Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) Input Voltage (DI) Enable Input Voltage (En, En*) Output Voltage (DO+, DO-) Storage Temperature Range -0.3V to +4V -0.3V to (VCC + 0.3V) -0.3V to (VCC + 0.3V) -0.3V to +3.9V -65C TA +150C +260C +150C Lead Temperature Range (Soldering 4 sec.) Maximum Junction Temperature Maximum Power Dissipation @ +25C (Note 2) 16LD Ceramic Flatpack and SOIC Thermal Resistance 845mW JA 16LD Ceramic Flatpack and SOIC 148C/W JC 16LD Ceramic Flatpack and SOIC ESD Rating (Note 3) 22C/W 6KV Recommended Operating Conditions Min +3.0V -55C Supply Voltage (VCC) Operating Free Air Temperature (TA) Typ +3.3V +25C Max +3.6V +125C Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A www.ti.com Subgroup Description 1 Static tests at Temp C +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 2 DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = 3.0/3.6V Symbol Parameter Conditions Notes Min Max Units Subgroups 250 450 mV 1, 2, 3 50 mV 1, 2, 3 V 1, 2, 3 VOD1 Differential Ouput Voltage RL = 100 Fig 1 VOD1 in magnitude of VOD1 for RL = 100 Fig 1 complementary output States VOS Offset Voltage RL = 100 Fig 1 VOS in Magnitude of VOS for RL = 100 Fig 1 50 mV 1, 2, 3 VOH Output Voltage High RL = 100 Fig 1 1.85 V 1, 2, 3 VOL Output Voltage Low RL = 100 Fig 1 V 1, 2, 3 VIH Input Voltage High (Note 4) 2.0 VCC V 1, 2, 3 VIL Input Voltage Low (Note 4) Gnd 0.8 V 1, 2, 3 IIH Input Current VI = VCC or 2.5V, VCC = 3.6V 10 A 1, , 2, 3 IIL Input Current VI = Gnd or 0.4V, VCC = 3.6V 10 A 1, 2, 3 VCl Input Clamp Voltage ICl = -8mA, VCC = 3.0V IOS Output Short Circuit Current Enabled, DI = VCC, DO+ = 0V or DI = Gnd, DO- = 0V IOff Power-off Leakage VO = 0V or 3.6V VCC = 0V or VCC = Open IOZ Output TRI-STATE Current En = 0.8V and En* = 2.0V VO = 0V or VCC, VCC = 3.6V ICC No Load Drivers Enabled Supply DI = VCC or Gnd Current ICCL Loaded Drivers Enabled Supply Current ICCZ Loaded or No Load Drivers Disabled Supply Current 1.125 1.625 Complementary Output States 0.9 -1.5 V 1, 2, 3 mA 1, 2, 3 20 A 1, 2, 3 10 A 1, 2, 3 18 mA 1, 2, 3 RL = 100 All Channels, DI = VCC or Gnd (all inputs) 35 mA 1, 2, 3 DI = VCC or Gnd, En = Gnd, En* = VCC 12 mA 1, 2, 3 -9.0 AC Parameters The following conditions apply, unless otherwise specified. AC: Symbol VCC = 3.0/3.3/3.6V, RL = 100, CL = 20pF. Parameter Conditions Notes Min Max Units Subgroups tPHLD Differential Propagation Delay High to Low Fig 2&3 0.3 3.5 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High Fig 2&3 0.3 3.5 ns 9, 10, 11 tSkD Differential Skew tPHLD - tPLHD 1.5 ns 9, 10, 11 tSk1 Channel to Channel Skew (Note 5) 1.75 ns 9, 10, 11 tSk2 Chip to Chip Skew (Note 6) 3.2 ns 9, 10, 11 3 www.ti.com DS90LV031AQML DS90LV031A Electrical Characteristics DS90LV031AQML Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Derate (W & WG packages) at 6.8mW/C for temperatures above +25C. Note 3: Human body model, 1.5 k in series with 100 pF Note 4: Tested during VOH/VOL tests. Note 5: Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 7: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die Parameter Measurement Information 20163803 FIGURE 1. Driver VOD and VOS Test Circuit 20163804 FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit www.ti.com 4 DS90LV031AQML 20163805 FIGURE 3. Driver Propagation Delay and Transition Time Waveforms Typical Application 20163808 FIGURE 4. Point-to-Point Application 5 www.ti.com DS90LV031AQML parallel with 0.01F, in parallel with 0.001F at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10F (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. Applications Information General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN808, AN1035, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 4. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100. A termination resistor of 100 should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 4. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100 termination resistor which the receiver detects with a 250 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV - 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 5. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz-50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I CC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver and is a step down replacement for the 5V DS90C031 Quad Driver. PC Board considerations: Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Differential Traces: Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is greater with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90 turns (these cause impedance discontinuities). Use arcs or 45 bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. Termination: Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90 and 130. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). Probing LVDS Transmission Lines: Always use high impedance (> 100k), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. Cables and Connectors, General Comments: Power Decoupling Recommendations: Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1F in www.ti.com 6 other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100 termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5k to 15k range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Fail-safe Feature: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any 20163809 FIGURE 5. Driver Output Levels 7 www.ti.com DS90LV031AQML When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M d 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. DS90LV031AQML Pin Descriptions Pin No. Name 1, 7, 9, 15 DI Description 2, 6, 10, 14 DO+ Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DO- Inverting driver output pin, LVDS levels Driver input pin, TTL/CMOS compatible 4 En Active high enable pin, OR-ed with En* 12 En* Active low enable pin, OR-ed with En 16 VCC Power supply pin, +3.3V 0.3V 8 Gnd Ground pin 20163810 20163811 FIGURE 6. Typical DS90LV031, TA = 25C DO (single ended) vs RL FIGURE 7. Typical DS90LV031, DO vs RL, VCC = 3.3V, TA = 25C Truth Table Driver Enables Input En En* DI DO+ L H X Z Z L L H H H L All other combinations of ENABLE inputs www.ti.com Outputs 8 DO- Released 15-NOV-2011 Revision Section Originator Changes A New Release, Corporate format L. Lytle 1 MDS data sheet converted into one Corp. data sheet format. MNDS90LV031A-X Rev 1C0 will be archived. B Order Information, QCI Conf Insp.,DC Parameters, AC Parameters, Application Info. Kirby K. Order Information: Added DS90LV031AWGMLS and DS90LV031AWMLS. Along with DS90LV031-MDS with Note 7 being added. QCI: Added '+' Signs. DC Parameters: Updated sign and added Fig 1 in notes section. Moved Ios limit to Min side. AC Parameters: Added Fig 2 and 3 to Notes section. Applications Info: Changed to reflect commercial data sheet. Rev A will be archived. 9 www.ti.com DS90LV031AQML Revision History DS90LV031AQML Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Cerpack NS Package Number W16A 16-Lead Ceramic SOIC NS Package Number WG16A www.ti.com 10 DS90LV031AQML Notes 11 www.ti.com DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver Notes TI/NATIONAL INTERIM IMPORTANT NOTICE Texas Instruments has purchased National Semiconductor. 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