DM54LS469A/DM74LS469A 8-Bit Up/Down Counter General Description The 'LS469A is an 8-bit synchronous up/down counter with parallel load and hold capability. Three function-select inputs (LD, UD, CBI) provide one of four operations which occur synchronously on the rising edge of the clock (CK). The LOAD operation loads the inputs (D7-D0) into the output register (Q7-Q0). The HOLD operation holds the previous value regardless of clock transitions. The INCREMENT operation adds one to the output register when the carry-in input is TRUE (CBI e LOW), otherwise the operation is a HOLD. The carry-out (CBO) is True (CBO e LOW) when the output register (Q7-Q0) is all HIGHs, otherwise FALSE (CBO e HIGH). The DECREMENT operation subtracts one from the output register when the borrow-in input is TRUE (CBI e LOW), otherwise the operation is a HOLD. The borrow-out (CBO) is true (CBO e LOW) when the output register (Q7 - Q0) is all LOWs, otherwise FALSE (CBO e HIGH). The output register (Q7 - Q0) is enabled when OE is LOW, and disabled (HI - Z) when OE is HIGH. The output drivers will sink the 24 mA required for many bus-interface standards. Two or more 'LS469A octal up/down counters may be cascaded to provide larger counters. Features Y Y Y Y Y Y Octal Register for general purpose interfacing applications 8 bits match byte boundaries Low current PNP inputs reduce loading Bus-structured pinout TRI-STATEE outputs 24-pin SKINNYDIP saves space Connection Diagram Top View TL/L/10223 - 1 Order Number DM54LS469AJ, DM74LS469AJ, DM74LS469AN or DM74LS469AV See NS Package Number J24F, N24C or V28A Function Table OE CK LD UD CBI D7 - D0 H L L L L L X u u u u u X L H H H H X X L L H H X X H L H L X D X X X X Q7 - Q0 Operation Z HI -Z D LOAD Q HOLD Q Plus 1 INCREMENT Q HOLD Q Minus 1 DECREMENT TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/L/10223 RRD-B30M115/Printed in U. S. A. DM54LS469A/DM74LS469A 8-Bit Up/Down Counter July 1989 Absolute Maximum Ratings (Note 1) ESD Tolerance Czap e 100 pF Rzap e 150X Test Method: Human Body Model Test Specification: NSC SOP 5-028 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage Off-State Output Voltage Storage Temperature 7V 5.5V 5.5V b 65 C to a 150 C l 1000V Recommended Operating Conditions Symbol Military Parameter Min VCC Supply Voltage TA Operating Free-Air Temperature TC Operating Case Temperature Commercial Typ Max Min 4.5 5 5.5 b 55 25 Units Typ Max 4.75 5 5.25 V 0 25 75 C 125 C Electrical Characteristics Series 24A Over Recommended Operating Temperature Range Symbol Parameter Test Conditions VIH High Level Input Voltage (Note 2) VIL Low Level Input Voltage (Note 2) VIC Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min VIL e 0.8V VIH e 2V VOL IOZH Low Level Output Voltage VCC e Min VIL e 0.8V VIH e 2V Max MIL IOH e b3.2 mA COM IOL e 12 mA MIL IOL e 24 mA COM 2.4 Units V b 0.8 IOH e b2 mA 0.8 V b 1.5 V 2.9 V VO e 2.4V 100 mA VO e 0.4V b 100 mA 1 mA Maximum Input Current VCC e Max, VI e 5.5V IIH High Level Input Current (Note 3) VCC e Max, VI e 2.4V IIL Low Level Input Current (Note 3) VCC e Max, VI e 0.4V IOS Output Short-Circuit Current VCC e 5V ICC Supply Current VCC e Max VO e 0V (Note 4) 0.3 V 0.5 VCC e Max VIL e 0.8V VIH e 2V II Typ 2 Off-State Output Current (Note 3) IOZL Min b 30 25 mA b 0.04 b 0.25 mA b 70 b 130 mA 135 180 mA Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device maybe operated at these values. Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 3: I/O leakage as the worst case of IOZX or IIX, e.g., IIL and IOZL. Note 4: During IOS measurement, only one output at a time should be grounded. Permanent damage otherwise may result. 2 Switching Characteristics Over Recommended Operating Conditions Symbol Parameter tS Set-Up Time from Input tW Width of Clock Military Test Conditions High Low Min Typ Commercial Max Min Typ Units Max 40 20 30 20 ns 20 7 15 7 ns 35 15 25 15 ns tpd CBI to CBO Delay CL e 50 pF 23 35 23 30 ns tclk Clock to Output CL e 50 pF 10 25 10 15 ns tpzx Output Enable Delay CL e 50 pF 19 35 19 30 ns tpzx Output Disable Delay CL e 5 pF 15 35 15 30 tH Hold Time fmax Maximum Frequency Test Load ns 0 b 15 0 b 15 ns 15.3 32 22.2 32 MHz Schematic of Inputs and Outputs MIL R1 e 390 R2 e 750 COM'L R1 e 200 R2 e 390 TL/L/10223-2 Test Waveforms Set-Up and Hold TL/L/10223 - 3 Pulse Width TL/L/10223 - 4 Propagation Delay TL/L/10223 - 6 Enable and Disable TL/L/10223 - 5 Note A: VT e 1.5V. Note B: CL includes probe and jig capacitance. Note C: In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. TL/L/10223 - 7 3 Logic Diagram 8-Bit Up/Down Counter TL/L/10223 - 8 4 Physical Dimensions inches (millimeters) 24-Pin Narrow Ceramic Dual-In-Line Package (J) Order Number DM54LS469AJ or DM74LS469AJ NS Package Number J24F 24-Pin Narrow Plastic Dual-In-Line Package (N) Order Number DM74LS469AN NS Package Number N24C 5 DM54LS469A/DM74LS469A 8-Bit Up/Down Counter Physical Dimensions inches (millimeters) (Continued) Lit. Y 114386 28-Lead Plastic Chip Carrier (V) Order Number DM74LS469AV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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