TL/L/10223
DM54LS469A/DM74LS469A 8-Bit Up/Down Counter
July 1989
DM54LS469A/DM74LS469A 8-Bit Up/Down Counter
General Description
The ’LS469A is an 8-bit synchronous up/down counter with
parallel load and hold capability. Three function-select in-
puts (LD,UD, CBI) provide one of four operations which
occur synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (D7–D0) into the out-
put register (Q7–Q0). The HOLD operation holds the previ-
ous value regardless of clock transitions. The INCREMENT
operation adds one to the output register when the carry-in
input is TRUE (CBI eLOW), otherwise the operation is a
HOLD. The carry-out (CBO) is True (CBO eLOW) when
the output register (Q7–Q0) is all HIGHs, otherwise FALSE
(CBO eHIGH). The DECREMENT operation subtracts one
from the output register when the borrow-in input is TRUE
(CBI eLOW), otherwise the operation is a HOLD. The bor-
row-out (CBO) is true (CBO eLOW) when the output regis-
ter (Q7–Q0) is all LOWs, otherwise FALSE (CBO eHIGH).
The output register (Q7–Q0) is enabled when OE is LOW,
and disabled (HI–Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus-interface stan-
dards. Two or more ’LS469A octal up/down counters may
be cascaded to provide larger counters.
Features
YOctal Register for general purpose interfacing
applications
Y8 bits match byte boundaries
YLow current PNP inputs reduce loading
YBus-structured pinout
YTRI-STATEÉoutputs
Y24-pin SKINNYDIP saves space
Connection Diagram
Top View
TL/L/10223–1
Order Number DM54LS469AJ, DM74LS469AJ, DM74LS469AN or DM74LS469AV
See NS Package Number J24F, N24C or V28A
Function Table
OE CK LD UD CBI D7–D0 Q7–Q0 Operation
HXXX X X Z HI–Z
L
u
L X X D D LOAD
L
u
H L H X Q HOLD
L
u
H L L X Q Plus 1 INCREMENT
L
u
H H H X Q HOLD
L
u
H H L X Q Minus 1 DECREMENT
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.