1
FEATURES APPLICATIONS
DESCRIPTION
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007www.ti.com
6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERSAND 4 LOW-INPUT VOLTAGE LDOs
•Cell Phones, Smart-Phones2
•Up To 95% Efficiency
•WLAN•Output Current for DC/DC Converters:
•PDAs, Pocket PCs– TPS65050: 2 x 0.6 A
•OMAP™ and Low-Power TMS320™ DSP– TPS65051: DCDC1 = 1 A; DCDC2 = 0.6 A
Supply– TPS65052: DCDC1 = 1 A; DCDC2 = 0.6 A
•Samsung S3C24xx application processor– TPS65054: 2 x 0.6 A
Supply– TPS65056: DCDC1 = 1 A; DCDC2 = 0.6 A
•Portable Media Players•Output Voltages for DC/DC Converters– TPS65050: Externally Adjustable
The TPS6505x are integrated Power Management– TPS65051: Externally Adjustable
ICs for applications powered by one Li-Ion or– TPS65052: DCDC1 = Fixed at 3.3 V;
Li-Polymer cell, which require multiple power rails.DCDC2 = 1 V / 1.3 V for Samsung
The TPS6505x provides two efficient, 2.25-MHzApplication Processors
step-down converters targeted at providing the core– TPS65054: DCDC1 = Externally Adjustable;
voltage and I/O voltage in a processor based system.DCDC2 = 1.3 V / 1.05 V for OMAP™1710
Both step-down converters enter a low power modeat light load for maximum efficiency across the widestProcessor
possible range of load currents.– TPS65056: DCDC1 = Fixed at 3.3 V;DCDC2 = 1 V / 1.3 V for Samsung
For low noise applications, the devices can be forcedApplication Processors
into fixed frequency PWM mode by pulling the MODEpin high. In the shutdown mode, the current•V
I
Range for DC/DC Converters
consumption is reduced to less than 1 μA. TheFrom 2.5 V to 6 V
devices allow the use of small inductors and•2.25-MHz Fixed Frequency Operation
capacitors to achieve a small solution size. TPS6505x•Power Save Mode at Light Load Current provides an output current of up to 1 A on eachDC/DC converter. The TPS6505x also integrate two•180 °Out-of-Phase Operation
400-mA LDO and two 200-mA LDO voltage•Output Voltage Accuracy in PWM mode ± 1%
regulators, which can be turned on/off using separate•Low Ripple PFM Mode
enable pins on each LDO. Each LDO operates withan input voltage range between 1.5 V and 6.5 V•Total Typical 32- μA Quiescent Current for Both
allowing them to be supplied from one of theDC/DC Converters
step-down converters or directly from the main•100% Duty Cycle for Lowest Dropout
battery.•Two General-Purpose 400-mA, High PSRR
Four digital input pins are used to set the outputLDOs
voltage of the LDOs from a set of 16 different•Two General-Purpose 200-mA, High PSRR
combinations for LDO1 to LDO4 on TPS65050 andLDOs
TPS65052. In TPS65051, TPS65054 and TPS65056,the LDO voltages are adjustable using external•V
I
range for LDOs from 1.5 V to 6.5 V
resistor dividers.•Digital Voltage Selection for the LDOs
The TPS6505x come in a small 32-pin leadless•Available in a 4 mm x 4 mm 32-Pin QFN
package (4 mm x 4 mm QFN) with a 0.4 mm pitch.Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2OMAP, TMS320, PowerPAD are trademarks of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2007, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATIONPART OUTPUT CURRENT QFN
(1)
PACKAGET
A
OPTIONNUMBER for DC/DC CONVERTERS PACKAGE
(2)
MARKING
LDO voltages according to Table 1TPS65050 2 x 600 mA 65050DC/DC converters externally adjustable
LDO voltages externally adjustable DCDC1 = 1 ATPS65051 65051DC/DC converters externally adjustable DCDC2 = 600 mA
LDO voltages according to Table 1 DCDC1 = 1 ATPS65052 65052DCDC1 = 3.3 V; DCDC2 = 1 V / 1.3 V DCDC2 = 600 mA-40 °C to 85 °C RSMLDO voltages externally adjustableTPS65054 DCDC1 = externally adjustable 2 x 600 mA 65054DCDC2 = 1.3 V / 1.05 V
LDO voltages externally adjustable
DCDC1 = 1ATPS65056 DCDC1 = 3.3 V 65056DCDC2 = 600 mADCDC2 = 1.0 V / 1.3 V
(1) The RSM package is available in tape and reel. Add the R suffix (TPS65050RSMR) to order quantities of 3000 parts per reel. Add the Tsuffix (TPS65050RSMT) to order quantities of 250 parts per reel.(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
(1)
UNITS
Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with
– 0.3 V to 7 Vrespect to AGNDV
I
Input voltage range on EN_LDO1 pins with respect to AGND – 0.3 V to V
CC
+ 0.5 VCurrent at VINDCDC1/2, L1, PGND1, L2, PGND2 1800 mAI
I
Current at all other pins 1000 mAV
O
Output voltage range for LDO1, LDO2, LDO3, and LDO4 – 0.3 V to 4.0 VContinuous total power dissipation See the dissipation rating tableT
A
Operating free-air temperature – 40 °C to 85 °CT
J
Maximum junction temperature 125 °CT
stg
Storage temperature range – 65 °C to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POWER RATING DERATING FACTOR POWER RATING POWER RATINGPACKAGE R
θJA
(1)
T
A
≤25 °C ABOVE T
A
= 25 °C T
A
= 70 °C T
A
= 85 °C
RSM 58 K/W 1.7 W 17 mW/K 0.95 W 0.68 W
(1) The thermal resistance junction to case of the RSM package is 4 K/W measured on a high K board
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
I
Input voltage range for step-down converters, VINDCDC1/2 2.5 6 VOutput voltage range for step-down converter, VDCDC1 0.6 VINDCDC1/2 VV
O
Output voltage range for step-down converter, VDCDC2 0.6 VINDCDC1/2 VV
I
Input voltage range for LDOs, VINLDO1, VINLDO2, VINLDO3/4 1.5 6.5 V
2Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
ELECTRICAL CHARACTERISTICS
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
RECOMMENDED OPERATING CONDITIONS (continued)over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Output voltage range for LDO1 and LDO2 1 3.6 VV
O
Output voltage range for LDO3 and LDO4 1 3.6 VOutput current at L1 (DCDC1) for TPS65051, TPS65052 1000 mAOutput current at L1 (DCDC1) for TPS65050, TPS65054 600 mAI
O
Output current at L1 (DCDC2) 600 mAOutput current at VLDO1, VLDO2 400 mAOutput current at VLDO3, VLDO4 200 mAInductor at L1, L2
(1)
1.5 2.2 μHOutput capacitor at VDCDC1, VDCDC2
(1)
10 22 μFC
O
Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4
(1)
2.2 μFInput capacitor at VCC
(1)
1μFC
I
Input capacitor at VINLDO1/2
(1)
2.2 μFInput capacitor at VINLDO3/4
(1)
2.2 μFT
A
Operating ambient temperature range -40 85 °CT
J
Operating junction temperature range -40 125 °CResistor from battery voltage to V
CC
used for filtering
(2)
1 10 Ω
(1) See the Application Information section of this data sheet for more details.(2) Up to 2 mA can flow into V
CC
when both converters are running in PWM, this resistor causes the UVLO threshold to be shiftedaccordingly.
V
CC
= VINDCDC1/2 = 3.6 V, EN = V
CC
, MODE = GND, L = 2.2 μH, C
O
= 10 μF. T
A
= -40 °C to 85 °C, typical values are atT
A
= 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
I
Input voltage range at VINDCDC1/2 2.5 6 V
One converter, I
O
= 0 mA.PFM mode enabled (Mode = GND) device not
20 30 μAswitching, EN_DCDC1 = V
I
OR EN_DCDC2 = V
I
;EN_LDO1= EN_LDO2 = EN_LDO3/4 = GND
Two converters, I
O
= 0 mAOperating quiescent current PFM mode enabled (Mode = 0) device not switching,
32 40 μAI
Q
Total current into V
CC
, VINDCDC1/2, EN_DCDC1 = V
I
AND EN_DCDC2 = V
I
; EN_LDO1 =VINLDO1, VINLDO2, VINLDO3/4 EN_LDO2 = EN_LDO3/4 = GND
One converter, I
O
= 0 mA.PFM mode enabled (Mode = GND) device notswitching, EN_DCDC1 = V
I
OR EN_DCDC2 = V
I
; 180 250 μAEN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 =V
I
One converter, I
O
= 0 mA.Switching with no load (Mode = V
I
), PWM operation
0.85 mAEN_DCDC1 = V
I
OR EN_DCDC2 = V
I
; EN_LDO1 =EN_LDO2 = EN_LDO3/4 = GNDI
Q
Operating quiescent current into V
CC
Two converters, I
O
= 0 mASwitching with no load (Mode = V
I
), PWM operation
1.25 mAEN_DCDC1 = V
I
AND EN_DCDC2 = V
I
; EN_LDO1 =EN_LDO2 = EN_LDO3/4 = GND
EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 =I
(SD)
Shutdown current 9 12 μAEN_LDO2 = EN_LDO3 = EN_LDO4 = GND
Undervoltage lockout threshold forV
(UVLO)
Voltage at V
CC
1.8 2 VDCDC converters and LDOs
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
MODE/DATA, EN_DCDC1, EN_DCDC2,DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3,V
IH
High-level input voltage 1.2 V
CC
VDEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,EN_LDO4
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS (continued)V
CC
= VINDCDC1/2 = 3.6 V, EN = V
CC
, MODE = GND, L = 2.2 μH, C
O
= 10 μF. T
A
= -40 °C to 85 °C, typical values are atT
A
= 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MODE/DATA, EN_DCDC1, EN_DCDC2, DEFLDO1,V
IL
Low-level input voltage DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, 0 0.4 VEN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2
MODE/DATA = GND or V
IMODE/DATA, EN_DCDC1, EN_DCDC2,DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, 0.01 1 μADEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3,I
lB
Input bias current
EN_LDO4
TPS65051 and TPS65052 onlyV_FB_LDOx = 1 V 100 nAFB_LDO1, FB_LDO2, FB_LDO3, FB_LDO4
POWER SWITCH
VINDCDC1/2 = 3.6 V 280 630DCDC1
VINDCDC1/2 = 2.5 V 400r
DS(on)
P-channel MOSFET on resistance m ΩVINDCDC1/2 = 3.6 V 280 630DCDC2
VINDCDC1/2 = 2.5 V 400
I
lkg
P-channel leakage current VDCDCx = V
(DS)
= 6 V 1 μA
VINDCDC1/2 = 3.6 V 220 450DCDC1
VINDCDC1/2 = 2.5 V 320r
DS(on)
N-channel MOSFET on resistance m ΩVINDCDC1/2 = 3.6 V 220 450DCDC2
VINDCDC1/2 = 2.5 V 320
I
lkg
N-channel leakage current VDCDCx = V
(DS)
= 6 V 7 10 μA
TPS65050
0.85 1 1.15TPS65054
2.5 V ≤VINDCDC1/2 ≤6DCDC1: AForward Current Limit
VTPS65051, TPS65052,I
(LIMF)
PMOS (High-Side) 1.19 1.4 1.65TPS65056and NMOS (Low side)
2.5 V ≤VINDCDC1/2 ≤6DCDC2: TPS65050 - TPS65056 0.85 1 1.15 AV
Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
OSCILLATOR
f
SW
Oscillator frequency 2.025 2.25 2.475 MHz
4Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS (continued)V
CC
= VINDCDC1/2 = 3.6 V, EN = V
CC
, MODE = GND, L = 2.2 μH, C
O
= 10 μF. T
A
= -40 °C to 85 °C, typical values are atT
A
= 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
Output voltage range for DCDC1, externally adjustable VINDCDCV
O
0.6 VDCDC2 versions 1/2
externally adjustableV
ref
Reference voltage 600 mVversions
VINDCDC1/2 = 2.5 V to 6 V0 mA < I
O
=<I
O
(max) -2% 0 2%Mode = GND, PFM operationDC output voltage DCDC1,V
O
accuracy DCDC2
(1)
VINDCDC1/2 = 2.5 V to 6 V0 mA < I
O
=<I
O
(max) -1% 0 1%Mode = V
I
, PWM operation
I
O
= 1 mA, Mode = GND, V
O
= 1.3 V,ΔV
O
Power save mode ripple voltage
(2)
25 mV
PPBandwith = 20 MHz
t
Start
Start-up time time from active EN to Start switching 170 μs
t
Ramp
VOUT Ramp up Time time to ramp from 5% to 95% of V
O
750 μs
RESET delay time Input voltage at threshold pin rising 80 100 120 ms
PB-ONOFF debounce time 26 32 38 ms
V
OL
RESET, PB_OUT output low voltage I
OL
= 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V 0.2 V
I
OL
RESET, PB_OUT sink current 1 mA
RESET, PB_OUT output leakage After PB_IN has been pulled high once; Vthreshold >
10 nAcurrent 1 V and Vhysteresis > 1 V, V
OH
= 6 V
V
th
Vthreshold, Vhysteresis threshold 0.98 1 1.02 V
VLDO1, VLDO2, VLDO3 and VLDO4 Low Dropout Regulators
Input voltage range for LDO1, LDO2,V
I
1.5 6.5 VLDO3, LDO4
V
O
LDO1 output voltage range TPS65050, TPS65052 only 1.2 3.3 V
LDO2 output voltage range TPS65050, TPS65052 only 1.8 3.3 V
LDO3 output voltage range TPS65050, TPS65052 only 1.1 3.3 V
LDO4 output voltage range TPS65050, TPS65052 only 1.2 2.85 V
Feedback voltage for FB_LDO1,V
(FB)
TPS65051, TPS65054 and TPS65056 only 1 VFB_LDO2, FB_LDO3, and FB_LDO4
Maximum output current for LDO1,I
O
400 mALDO2
Maximum output current for LDO3,
200 mALDO4
I
(SC)
LDO1 short-circuit current limit VLDO1 = GND 750 mA
LDO2 short-circuit current limit VLDO2 = GND 850 mA
LDO3 and LDO4 short-circuit current
VLDO3 = GND, VLDO4 = GND 420 mAlimit
Dropout voltage at LDO1 I
O
= 400 mA, VINLDO = 3.4 V 400 mV
Dropout voltage at LDO2 I
O
= 400 mA, VINLDO = 1.8 V 280 mV
Dropout voltage at LDO3, LDO4 I
O
= 200 mA, VINLDO = 1.8 V 280 mV
Leakage current from VinLDOx to LDO enabled, VINLDO = 6.5 V, V
O
= 1 V,I
lkg
3μAVLDOx at T
A
= 140 °C
Output voltage accuracy for LDO1,V
O
I
O
= 10 mA -2% 1%LDO2, LDO3, LDO4
VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5V,Line regulation for LDO1, LDO2,
VINLDO3,4 = VLDO3,4 + 0.5 V (min. 2.5 V) to 6.5V, -1% 1%LDO3, LDO4
I
O
= 10 mA
Load regulation for LDO1, LDO2, I
O
= 0 mA to 400 mA for LDO1, LDO2
-1% 1%LDO3, LDO4 I
O
= 0 mA to 200 mA for LDO3, LDO4
Regulation time for LDO1, LDO2,
Load change from 10% to 90% 10 μsLDO3, LDO4
PSRR Power supply rejection ratio f = 10 kHz; I
O
= 50 mA; V
I
= V
O
+ 1 V 70 dB
(1) Output voltage specification does not include tolerance of external voltage programming resistors.(2) In Power Save Mode, operation is typically entered at I
PSM
= V
I
/ 32 Ω.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS (continued)V
CC
= VINDCDC1/2 = 3.6 V, EN = V
CC
, MODE = GND, L = 2.2 μH, C
O
= 10 μF. T
A
= -40 °C to 85 °C, typical values are atT
A
= 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal discharge resistor at VLDO1,R
(DIS)
active when LDO is disabled 350 RVLDO2, VLDO3, VLDO4
Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
6Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
PIN ASSIGNMENTS
DEFLDO3
EN_LDO4
TPS65052 EN_LDO3
RESET
DEFLDO4
VLDO4
VINLDO3/4
VLDO3
HYSTERESIS
BP
AGND
VCC
VINLDO2
VLDO2
DEFLDO2
THRESHOLD
MODE
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
VLDO1
DEFLDO1
DEFDCDC2
FB_DCDC1
PGND1
L1
VINDCDC1/2
L2
PGND2
VDCDC2
DEFLDO3
EN_LDO4
TPS65050 EN_LDO3
PB_OUT
DEFLDO4
VLDO4
VINLDO3/4
VLDO3
GND
BP
AGND
VCC
VINLDO2
VLDO2
DEFLDO2
PB_IN
MODE
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
VLDO1
DEFLDO1
DEFDCDC2
FB_DCDC1
PGND1
L1
VINDCDC1/2
L2
PGND2
VDCDC2
FB3
EN_LDO4
TPS65051
TPS65054
TPS65056
EN_LDO3
RESET
FB4
VLDO4
VINLDO3/4
VLDO3
HYSTERESIS
BP
AGND
VCC
VINLDO2
VLDO2
FB2
THRESHOLD
MODE
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
VLDO1
FB1
DEFDCDC2
FB_DCDC1
PGND1
L1
VINDCDC1/2
L2
PGND2
VDCDC2
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
RSM PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONSTERMINAL
I/O DESCRIPTIONNAME TPS65050 TPS65051 TPS65052 TPS65054 TPS65056
Power supply for digital and analog circuitry of DCDC1, DCDC2V
CC
3 3 3 3 3 I and LDOs. This pin must be connected to the same voltage supplyas VINDCDC1/2.
Input to adjust output voltage of converter 1 between 0.6 V and V
I
.FB_DCDC1 24 24 24 24 24 I Connect external resistor divider between VOUT1, this pin, andGND.
Select between Power Safe Mode and forced PWM Mode forDCDC1 and DCDC2. In Power Safe Mode, PFM is used at lightMODE 32 32 32 32 32 I loads, PWM for higher loads. If PIN is set to high level, forcedPWM Mode is selected. If Pin has low level, then the deviceoperates in Power Safe Mode.
Input voltage for VDCDC1 and VDCDC2 step-down converter. ThisVINDCDC1/2 21 21 21 21 21 I
must be connected to the same voltage supply as V
CC
.
Feedback voltage sense input, connect directly to the output ofVDCDC2 18 18 18 18 18 I
converter 2.
TPS65050 and TPS65051: Feedback pin for converter 2. ConnectDEFDCDC2 to the center of the external resistor divider.TPS65052 and TPS65056: Select pin of converter 2 outputDEFDCDC2 17 17 17 17 17 I voltage.
High = 1.3 V, Low = 1 VTPS65054: Select pin of converter 2 output voltage.High = 1.05 V, Low = 1.3 V
L1 22 22 22 22 22 O Switch pin of converter 1. Connected to Inductor .
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
TERMINAL FUNCTIONS (continued)TERMINAL
I/O DESCRIPTIONNAME TPS65050 TPS65051 TPS65052 TPS65054 TPS65056
PGND1 23 23 23 23 23 I GND for converter 1
PGND2 19 19 19 19 19 I GND for converter 2
AGND 2 2 2 2 2 I Analog GND, connect to PGND and PowerPad™
L2 20 20 20 20 20 O Switch Pin of converter 2. Connected to Inductor.
EN_DCDC1 25 25 25 25 25 I Enable Input for converter 1, active high
EN_DCDC2 26 26 26 26 26 I Enable Input for converter 2, active high
VINLDO1 29 29 29 29 29 I Input voltage for LDO1
VINLDO2 4 4 4 4 4 I Input voltage for LDO2
VINLDO3/4 11 11 11 11 11 I Input voltage for LDO3 and LDO4
VLDO1 30 30 30 30 30 O Output voltage of LDO1
VLDO2 5 5 5 5 5 O Output voltage of LDO2
VLDO3 10 10 10 10 10 O Output voltage of LDO3
VLDO4 12 12 12 12 12 O Output voltage of LDO4
Digital input, used to set the default output voltage of LDO1 toDEFLDO1 31 -- 31 -- -- I
LDO4; LSB
FB1 -- 31 -- 31 31 I Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 toDEFLDO2 6 -- 6 -- -- I
LDO4.
FB2 -- 6 -- 6 6 I Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 toDEFLDO3 9 -- 9 -- -- I
LDO4.
FB3 -- 9 -- 9 9 I Feedback input for the external voltage divider.
Digital input, used to set the default output voltage of LDO1 toDEFLDO4 13 -- 13 -- -- I
LDO4; MSB
FB4 -- 13 -- 13 13 I Feedback input for the external voltage divider.
Enable input for LDO1. Logic high enables the LDO, logic lowEN_LDO1 27 27 27 27 27 I
disables the LDO.
Enable input for LDO2. Logic high enables the LDO, logic lowEN_LDO2 28 28 28 28 28 I
disables the LDO.
Enable input for LDO3. Logic high enables the LDO, logic lowEN_LDO3 15 15 15 15 15 I
disables the LDO.
Enable input for LDO4. Logic high enables the LDO, logic lowEN_LDO4 16 16 16 16 16 I
disables the LDO.
THRESHOLD -- 7 7 7 7 I Reset input
PB_IN 7 -- -- -- -- I Input for the pushbutton ON-OFF function
HYSTERESIS -- 8 8 8 8 I Input for hysteresis on reset threshold
GND 8 -- -- -- -- - Connect to GND
RESET -- 14 14 14 14 O Open drain active low reset output, 100 ms reset delay time.
Open drain output. Active low after the supply voltage (V
CC
)PB_OUT 14 -- -- -- -- O exceeded the undervoltage lockout threshold. The pin can betoggled pulling PB_IN high.
BP 1 1 1 1 1 I Input for bypass capacitor for internal reference.
PowerPAD™ -- -- -- -- -- Connect to GND
8Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
L2
DEFDCDC2
EN_DCDC1
ENABLE
VCC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO2
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
VLDO1
VLDO4
200-mA LDO
VIN VIN_LDO1
VIN_LDO3/4
ENABLE
VIN
MODE
Interface
2.2 Hm
2.2 Hm
1 Fm
1W
10 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65050
ENABLE EN_LDO2
EN_LDO3
ENABLE EN_LDO4
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
0.1 Fm
BP
VIN VIN_LDO2
Vbat
PB_OUT
AGND
PB_IN
Vbat
Flipflopwith
32-msdebounce
default
turnedon
R2
R1
R3
R4
Cff
I/Ovoltage
R19
STEP-DOWN
CONVERTER
600mA
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
L2
DEFDCDC2
EN_DCDC1
ENABLE
VCC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO1
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
FB4
VLDO4
200-mA LDO
VIN VIN_LDO1
VIN_LDO3/4
ENABLE
VIN
MODE
2.2 Hm
2.2 Hm
1 Fm
1W
22 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65051
ENABLE EN_LDO2
EN_LDO3
ENABLE EN_LDO4
0.1 Fm
BP
VIN VIN_LDO2
Vbat
RESET
AGND
THRESHOLD
HYSTERESIS
RESET
R2
R1
R11
R12
Cff
I/Ovoltage
R19
STEP-DOWN
CONVERTER
1 A
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
R5
R3
R6
R4
R7
R8
R9
R10
FB1
FB2
FB3
VLDO2
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
L2
EN_DCDC1
ENABLE
VCC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO2
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
VLDO1
VLDO4
200-mA LDO
1V/1.3V DEFDCDC2
VIN_LDO3/4
ENABLE
VIN
MODE
Interface
2.2 Hm
3.3 Hm
1 Fm
1W
10 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65052
ENABLE EN_LDO2
EN_LDO3
ENABLE EN_LDO4
DEFLDO1
DEFLDO2
DEFLDO3
DEFLDO4
0.1 Fm
BP
VIN VIN_LDO2
Vbat
STEP-DOWN
CONVERTER
1 A
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
VIN VIN_LDO1
RESET
AGND
THRESHOLD
HYSTERESIS
RESET
I/Ovoltage
R19
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
L2
EN_DCDC1
ENABLE
VCC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO1
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
FB4
VLDO4
200-mA LDO
1.3V/1.05V DEFDCDC2
VIN_LDO3/4
ENABLE
VIN
MODE
2.2 Hm
2.2 Hm
1 Fm
1W
22 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65054
ENABLE EN_LDO2
EN_LDO3
ENABLE EN_LDO4
0.1 Fm
BP
VIN VIN_LDO2
Vbat
RESET
AGND
THRESHOLD
HYSTERESIS
RESET
R2
R1
R11
R12
Cff
I/Ovoltage
R19
STEP-DOWN
CONVERTER
600mA
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
R5
R6
R7
R8
R9
R10
FB1
FB2
FB3
VIN VIN_LDO1
VLDO2
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
L2
DEFDCDC2
EN_DCDC1
ENABLE
VCC
VDCDC2
PGND2
EN_LDO1
ENABLE
EN_DCDC2
ENABLE
VLDO2
VLDO3
200-mA LDO
VLDO3
VLDO1
VLDO4
DCDC1(I/O)
VINDCDC1/2
L1
FB_DCDC1
PGND1
DCDC2(core)
VLDO1
400-mA LDO
FB4
VLDO4
200-mA LDO
VIN VIN_LDO1
VIN_LDO3/4
ENABLE
VIN
MODE
2.2 Hm
3.3 Hm
1 Fm
1W
22 Fm
10 Fm
10 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65056
ENABLE EN_LDO2
EN_LDO3
ENABLE EN_LDO4
0.1 Fm
BP
VIN VIN_LDO2
Vbat
RESET
AGND
THRESHOLD
HYSTERESIS
RESET
R11
R12 I/Ovoltage
R19
STEP-DOWN
CONVERTER
1 A
STEP-DOWN
CONVERTER
600mA
400-mA LDO
4.7 Fm
R5
R6
R7
R8
R9
R10
FB1
FB2
FB3
VLDO2
1V/1.3V
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 1 10
Efficiency − %
I − OutputCurrent
O− A
0.1
3.4V
5V
4.2V
3.8V
V =3.3V
T =25 C
PWM/PFMMode
O
A
o
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 1 10
Efficiency − %
I − OutputCurrent
O− A
0.1
V =3.3V
T =25 C
PWMMode
O
A
o
3.8V
3.4V
5V
4.2V
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
FIGURE
Efficiency converter 1 vs Output current Figure 1Efficiency converter 2 vs Output current Figure 2Efficiency converter 1 vs Output current Figure 3Efficiency converter 2 vs Output current Figure 4Output voltage ripple PWM/PFM mode = low Figure 5Output voltage ripple PWM mode = high Figure 6DCDC1 startup timing Figure 7LDO1 to LDO4 startup timing Figure 8DCDC1 load transient response PWM mode = high Figure 9DCDC1 load transient response PFM mode = low Figure 10DCDC2 load transient response PWM mode = high Figure 11DCDC2 load transient response PFM mode = low Figure 12DCDC1 line transient response Figure 13DCDC2 line transient response Figure 14LDO1 load transient response Figure 15LDO4 load transient response Figure 16LDO1 line transient response Figure 17Power supply rejection ratio vs Frequency Figure 18
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 1
Efficiency − %
I − OutputCurrent
O− A
0.1
V =1.3V
T =25 C
PFMMode
O
A
o
3.3V
5V
4.2V
3.8V
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 1
Efficiency − %
I − OutputCurrent
O− A
0.1
V =1.3V
T =25 C
PWMMode
O
A
o
3.8V
3.3V
5V
4.2V
t − Time=500ns/div
100 mA/div
20 mV/div
V =4.2V, =25 C
I
o
TA
100mA/div
CH4(ILDCDC1=600mA)
CH3(ILDCDC2=600mA)
CH1(VDCDC1=3.3V)
CH1(VDCDC2=1.5V)
20 mV/div
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 3. Figure 4.
OUTPUT VOLTAGE RIPPLE OUTPUT VOLTAGE RIPPLEPWM/PFM MODE = LOW PWM MODE = HIGH
Figure 5. Figure 6.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
t − Time=200 s/divm
5V/div
1V/div
V =3.6V
T =25 C
I
A
o
Mode=Low
Load DCDC1=600mA
LoadDCDC2=600mA
CH3
(VDCDC2=1.5V)
CH4(VLDO1)
CH1(EN)
CH2
(VDCDC1=3.3V)
1V/div
1V/div
t − Time=20 s/divm
V =3.6V
T =25 C
ILDO1/2/3/4
I
A
o
=100mA
Mode=Low
CH3(VLDO3)
CH4(VLDO4)
CH1(VLDO1)
EN
CH2(VLDO2)
5V/div
1V/div
1V/div
1V/div
1V/div
t − Time=100 s/divm
50mV/div
200mA/div
VDCDC1=3.3V
ENDCDC1=High
ENDCDC2=Low
LoadCurrent=60mA to540mA
CH1(VDCDC1)
CH2
I(DCDC1)
V =4.2V
T =25 C
I
A
o
Mode=High
t − Time=100 s/divm
VDCDC1=3.3V
ENDCDC1=High
ENDCDC2=Low
LoadCurrent=60mA to540mA
V =4.2V
T =25 C
I
A
o
Mode=Low
50mV/div
200mA/div
CH1(VDCDC1)
CH2
I(DCDC1)
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
DCDC1 STARTUP TIMING LDO1 TO LDO4 STARTUP TIMING
Figure 7. Figure 8.
DCDC1 LOAD TRANSIENT RESPONSE DCDC1 LOAD TRANSIENT RESPONSE
Figure 9. Figure 10.
16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
t − Time=100 s/divm
VDCDC2=1.5V
ENDCDC1=Low
ENDCDC2=High
LoadCurrent=60mA to540mA
V =3.6V
T =25 C
I
A
o
Mode=Low
50mV/div
200mA/div
CH1(VDCDC2)
CH2
I(DCDC2)
t − Time=100 s/divm
VDCDC2=1.5V
ENDCDC1=Low
ENDCDC2=High
LoadCurrent=60mA to540mA
V =3.6V
T =25 C
I
A
o
Mode=High
50mV/div
200mA/div
CH1(VDCDC2)
CH2
I(DCDC2)
t − Time=100 s/divm
VDCDC1=3.3V
ENDCDC1=High
ENDCDC2=Low
LoadCurrent=600mA
V =3.6Vto4.5Vto3.6V
T =25 C
I
A
o
Mode=High
500mV/div
20mV/div
CH1
VIN(VDCDC1)
CH2(VDCDC1)
t − Time=100 s/divm
VDCDC2=1.5V
ENDCDC1=Low
ENDCDC2=High
LoadCurrent=600mA
V =3.4Vto4.4Vto3.4V
T =25 C
I
A
o
Mode=High
500mV/div
20mV/div
CH1
VIN(VDCDC2)
CH2(VDCDC2)
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
DCDC2 LOAD TRANSIENT RESPONSE DCDC2 LOAD TRANSIENT RESPONSE
Figure 11. Figure 12.
DCDC1 LINE TRANSIENT RESPONSE DCDC2 LINE TRANSIENT RESPONSE
Figure 13. Figure 14.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
t − Time=100 s/divm
V =3.6V
T =25 C
VLDO1=3.3V
VLDO1=40mA to360mA
I
A
o
50mV/div
200mA/div
CH1(VLDO1)
CH2
I(LDO1)
t − Time=100 s/divm
V =3.6V
VLDO4=1.3V
T =25 C
I
A
VLDO4=20mA to180mA
o
50mV/div
200mA/div
CH1(VLDO4)
CH2
I(LDO4)
t − Time=100 s/divm
V =3.6Vto4.2Vto3.6V
T =25 C
VLDO1=100mA
Mode=High
I
A
o
VLDO1=3.3V
500mV/div
20mV/div
CH1
VIN(LDO1)
CH2(VLDO1)
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 1M 10M
RejectionRatio − dB
f − Frequency − Hz
100k
10k
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
LDO1 LOAD TRANSIENT RESPONSE LDO4 LOAD TRANSIENT RESPONSE
Figure 15. Figure 16.
POWER SUPPLY REJECTION RATIOvsLDO1 LINE TRANSIENT RESPONSE FREQUENCY
Figure 17. Figure 18.
18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
DETAILED DESCRIPTION
Operation
DCDC1 Converter
DCDC2 Converter
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The TPS6505x include each two synchronous step-down converters. The converters operate with 2.25-MHz(typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light loadcurrents, the converters automatically enter Power Save Mode and operate with PFM (Pulse FrequencyModulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with inputvoltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and outputcapacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch isturned on, and the inductor current ramps up until the current comparator trips, and the control logic turns off theswitch. The current limit comparator turns off the switch if the current limit of the P-channel switch is exceeded.After the adaptive dead time, which prevents shoot through current, the N-channel MOSFET rectifier is turnedon, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channelrectifier, and turning on the on the P-channel switch.
The two DC/DC converters operate synchronized to each other, with converter 1 as the master. A 180 °phaseshift between converter 1 and converter 2 decreases the input RMS current. Therefore, smaller input capacitorscan be used.
The converter 1 output voltage is set by an external resistor divider connected to FB_DCDC1 pin for TPS65050,TPS65051 and TPS65054. For TPS65052, the output voltage is fixed to 3.3 V and this pin needs to be directlyconnected to the output. See the Application Information section for more details. The maximum output currenton DCDC1 is 600 mA for TPS65050 and TPS65054. For TPS65051, TPS65052 and TPS65056, the maximumoutput current is 1 A.
The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converteroutput voltage is selected via the DEFDCDC2 pin.
TPS65050 and TPS65051: The output voltage is set with an external resistor divider. Connect the DEFDCDC2pin to the external resistor divider.
TPS65052, TPS65054 and TPS65056: The DEFDCDC2 pin can either be connected to GND, or to V
CC
. Theconverter 2 output voltage defaults to:Device DEFDCDC2 = low DEFDCDC2 = high
TPS65052 , TPS65056 1 V 1.3 VTPS65054 1.3 V 1.05 V
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Power-Save Mode
32 W
VINDCDC
I =
(PFM_enter)
(1)
24 W
VINDCDC
I =
(PSMDCDC_leave)
(2)
Dynamic Voltage Positioning
FastLoad Transient
PFMMode
LightLoad
PFMMode
Medium/HeavyLoad
COMP_LOW Threshold
PFMMode
LightLoad
-1%
Smooth
IncreasedLoad
PFMMode
Medium/HeavyLoad
+1%
VOUT_NOM
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The Power Save Mode is enabled with the Mode pin set to 0. If the load current decreases, the converters entersPower Save Mode operation automatically. During Power Save Mode, the converters operate with reducedswitching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency. Theconverter positions the output voltage 1% above the nominal output voltage. This voltage positioning featureminimizes voltage drops caused by a sudden load step.
To optimize the converter efficiency at light load, the average current is monitored. If in PWM mode, the inductorcurrent remains below a certain threshold, then Power Save Mode is entered. The typical threshold is calculatedaccording to Equation 1 :
A. Average output current threshold to enter PFM mode.
A. Average output current threshold to leave PFM mode.
During the Power Save Mode, the output voltage is monitored with a comparator. As the output voltage fallsbelow the skip comparator threshold (skip comp), the P-channel switch turns on, and the converter effectivelydelivers a constant current. If the load is below the delivered current, the output voltage rises until the skip compthreshold is crossed again, then all switching activity ceases, reducing the quiescent current to a minimum untilthe output voltage has dropped below the threshold. If the load current is greater than the delivered current, theoutput voltage falls until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominalV
O
, then Power Save Mode is exited, and the converter returns to PWM mode
These control methods reduce the quiescent current to 12 μA per converter, and the switching frequency to aminimum achieving the highest converter efficiency. The PFM mode operates with low output voltage ripple. Theripple depends on the comparator delay, and the size of the output capacitor; increasing capacitor valuesdecreases the output ripple voltage.
The Power Save Mode can be disabled by driving the MODE pin high. In forced PWM mode, both convertersoperate with fixed frequency PWM mode regardless of the load.
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It isactivated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom forboth, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transientbehavior.
At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higherthan the nominal value. In the event of a load transient from light load to heavy load, the output voltage dropsuntil it reaches the skip comparator low threshold set to -1% below the nominal value and enters PWM mode.During a release from heavy load to light load, the voltage overshoot is also minimized due to active regulationturning on the N-channel switch.
Figure 19. Dynamic Voltage Positioning
20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Soft Start
95%
EN
5%
VOUT
tStart tRAMP
100% Duty Cycle Low Dropout Operation
V (min)=
IV (max)+I (max)x(r (max)+R )
O O DS(on) L
(3)
Undervoltage Lockout
Mode Selection
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The two converters have an internal soft start circuit that limits the inrush current during start-up. During softstart, the output voltage ramp up is controlled as shown in Figure 20 .
Figure 20. Soft Start
The converters offer a low input to output voltage difference while still maintaining operation with the use of the100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is useful inbattery-powered applications to achieve longest operation time by taking full advantage of the whole batteryvoltage range. (i.e. The minimum input voltage to maintain regulation depends on the load current and outputvoltage) and can be calculated as:
with:
•I
O
max = maximum output current plus inductor ripple current•r
DS(on)
max = maximum P-channel switch r
DS(on)
.•R
L
= DC resistance of the inductor•V
O
(max) = nominal output voltage plus maximum output voltage tolerance
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and fromexcessive discharge of the battery and disables all internal circuitry. The undervoltage lockout threshold, sensedat the V
CC
pin is typically 1.8 V, max 2 V.
The MODE pin allows mode selection between forced PWM Mode and power Safe Mode for both converters.Connecting this pin to GND enables the automatic PWM and power save mode operation. The convertersoperates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,maintaining high efficiency over a wide load current range.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Enable
RESET
+
-
HYSTERESIS
THRESHOLD
tNRESET
THRESHOLD-HYSTERESIS
Comparator
Output(Internal)
Vbat
Vbat
100ms
Delay
V =1V
ref
RESET
THRESHOLD RESET
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light loadcurrents. The advantage is the converters operate with a fixed frequency that allows simple filtering of theswitching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the powersave mode during light loads. For additional flexibility, it is possible to switch from power save mode to forcedPWM mode during operation. This allows efficient power management by adjusting the operation of the converterto the specific system requirements.
To start up each converter independently, the device has a separate enable pin for each DC/DC converter andfor each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 are set to high, thecorresponding converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in theelectrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internalcontrol circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350 Ωresistors,actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must notbe left unconnected.
The TPS65051, TPS65052, TPS65054 and TPS65056 contain circuitry that can generate a reset pulse for aprocessor with a 100 ms delay time. The input voltage at a comparator is sensed at an input called threshold.When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. A hysteresis can bedefined with an external resistor connected to the hysteresis input. This circuitry is functional as soon as thesupply voltage at V
CC
exceeds the undervoltage lockout threshold. Therefore, the TPS6505x has a shutdowncurrent (all DCDC converters and LDOs are off) of 9 μA in order to supply bandgap and comparator.
Figure 21. RESET Pulse Circuit
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Push-Button ON-OFF (PB-ON-OFF)
PB_IN
PB_IN
PB_OUT
Debounce
32ms
MinPulse
Width32ms
32ms
JK-
Flipflop
Default
Low
Vbat
RESPWRON
Short-Circuit Protection
Thermal Shutdown
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The TPS65050 provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold andhysteresis inputs. The output at PB_OUT is held low after voltage is applied at V
CC
. Only after the input at PB-INis pulled high once, the output driver at PB_OUT goes to its inactive state, driven high with its external pullupresistor. Further low-high pulses at PB-IN toggles the status of the PB_OUT output, and can be used toshutdown and start the converter with a single push on a button by connecting the PB_OUT output to the enableinput of the converters.
Figure 22. Push-Button Circuit
All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.
As soon as the junction temperature, T
J
, exceeds 150 °C (typically) for the DC/DC converters, the device goesinto thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues itsoperation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdownfor one of the DC/DC converters disables both converters simultaneously.
The thermal shutdown temperature for the LDOs are set to typically 140 °C. Therefore, a LDO which may beused to power an external voltage never heats up the chip high enough to turn off the DC/DC converters. If oneLDO exceeds the thermal shutdown temperature, all LDOs turns off simultaneously.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Low Dropout Voltage Regulators
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The low dropout voltage regulators are designed to operate well with small ceramic input and output capacitors.They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at ratedoutput current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2,EN_LDO3 and EN_LDO4 pin. In TPS65050 and TPS65052, the output voltage of the LDOs is set using 4 pins.The DEFLDO1 to DEFLDO4 pins can either be connected to GND or Vbat (V
CC
) to define a set of outputvoltages for LDO1 to LDO4 according to table 1. Connecting the DEFLDOx pins to a voltage different from GNDor V
CC
causes increased leakage current into V
CC
. In TPS65051 and TPS65054, the output voltage of the LDOsis set using external resistor dividers.
TPS65050 and TPS65052 default voltage options adjustable with DEFLDO4 … DEFLDO1 according to Table 1 .
Table 1. Default Options
DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 VLDO1 VLDO2 VLDO3 VLDO4
400 mA LDO 400 mA LDO 200 mA LDO 200 mA LDO1.8 V - 5.5 V 1.8 V - 5.5 V 1.5 V - 5.5 V 1.5 V - 5.5 VInput Input Input Input0 0 0 0 3.3 V 3.3 V 1.85 V 1.85 V0 0 0 1 3.3 V 3.3 V 1.5 V 1.5 V0 0 1 0 3.3 V 2.85 V 2.85 V 2.7 V0 0 1 1 3.3 V 2.85 V 2.85 V 2.5 V0 1 0 0 3.3 V 2.85 V 2.85 V 1.85 V0 1 0 1 3.3 V 2.85 V 1.85 V 1.85 V0 1 1 0 3.3 V 2.85 V 1.5 V 1.5 V0 1 1 1 3.3 V 2.85 V 1.5 V 1.3 V1 0 0 0 3.3 V 2.85 V 1.1 V 1.3 V1 0 0 1 2.85 V 2.85 V 1.85 V 1.85 V1 0 1 0 2.7 V 3.3 V 1.2 V 1.2 V1 0 1 1 2.5 V 3.3 V 1.5 V 1.5 V1 1 0 0 2.5 V 3.3 V 1.5 V 1.3 V1 1 0 1 1.85 V 1.85 V 1.35 V 1.35 V1 1 1 0 1.8 V 2.5 V 3.3 V 2.85 V1 1 1 1 1.2 V 1.8 V 1.1 V 1.3 V
24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
APPLICATION INFORMATION
Output Voltage Setting
Converter 1 (DCDC1)
R2
R1
V =
OV x1+
ref ()
(4)
Converter 2 (DCDC2)
VINDCDC1/2
ENDCDC2
PGND
VDCDC2
L2
Vbat
1W
1 Fm
CICO
VO
L
R3
R4
VCC
DEFDCDC2
AGND
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The output voltage of converter 1 can be set by an external resistor network. The output voltage can becalculated using Equation 4 .
with an internal reference voltage V
ref
, 0.6 V .
Setting the total resistance of R1 + R2 to less than 1 M Ωis recommended. The resistor network connects to theinput of the feedback amplifier, therefore, requiring a small feedforward capacitor in parallel to R1. A typical valueof 47 pF is sufficient.
The output voltage of converter 2 can be selected as following:•Adjustable output voltage defined with external resistor network on pin DEFDCDC2. This option is availablefor TPS65050 and TPS65051.•Two default fixed output voltages selectable by pin DEFDCDC2, see Table 2 . This option is available forTPS65052 and TPS65054.
Table 2. Default Fixed Output Voltages
Converter 2 DEFDCDC2 = low DEFDCDC2 = high
TPS65050 -- --TPS65051 -- --TPS65052 1 V 1.3 VTPS65054 1.3 V 1.05 VTPS65056 1 V 1.3 V
The adjustable output voltage can be calculated similar to the DCDC1 converter. Setting the total resistance ofR3 + R4 to less than 1 M Ωis recommended. Route the DEFDCDC2 line separate from noise sources, such asthe inductor or the L2 line. The VDCDC2 line needs to be directly connected to the output capacitor. As theVDCDC2 line is the feedback to the internal amplifier, no feedforward capacitor at R3 is needed.
Using an external resistor divider at DEFDCDC2:
Figure 23. External Resistor Divider
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
V(DEFDCDC2)
VO
R3 =R4 x -R4
()
R4
R3+R4
V =V
O (DEFDCDC2) x
(5)
Output Filter Design (Inductor and Output Capacitor)
Inductor Selection
L x ¦
1- VI
2
I (max)=I (max)+
L O
DI =V x
L O
VO
DIL
(6)
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
V
(DEFDCDC2)
= 0.6 V
See Table 3 for typical resistor values:
Table 3. Typical Resistor Values
OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE Typical CFF
3.3 V 680 k Ω150 k Ω3.32 V 47 pF3 V 510 k Ω130 k Ω2.95 V 47 pF2.85 V 560 k Ω150 k Ω2.84 V 47 pF2.5 V 510 k Ω160 k Ω2.51 V 47 pF1.8 V 300 k Ω150 k Ω1.8 v 47 pF1.6 V 200 k Ω120 k Ω1.6 V 47 pF1.5 V 300 k Ω200 k Ω1.5 V 47 pF1.2 V 330 k Ω330 k Ω1.2 V 47 pF
The two converters operate with 2.2- μH output inductor. Larger or smaller inductor values can be used tooptimize the performance of the device for specific operation conditions. The selected inductor has to be rated forits dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency ofthe converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. Theminimum inductor value is 1.5 μH, but an output capacitor of 22 μF minimum is needed in this case. For anoutput voltage above 2.8 V, an inductor value of 3.3 μH minimum is recommended. Lower values result in anincreased output voltage ripple in PFM mode.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of theinductor should be rated higher than the maximum inductor current as calculated with Equation 6 . This isrecommended because during heavy load transient the inductor current rises above the calculated value.
with:
•f = Switching Frequency (2.25-MHz typical)•L = Inductor Value•ΔI
L
= Peak-to-peak inductor ripple current•I
L
max = Maximum Inductor current
The highest inductor current occurs at maximum V
I
. Open core inductors have a soft saturation characteristic,and they can normally handle higher inductor currents versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of thecorresponding converter. Consideration must be given to the difference in the core material from inductor toinductor which has an impact on the efficiency especially at high switching frequencies. See Table 4 and thetypical applications for possible inductors.
26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Output Capacitor Selection
L x ¦
1-
x
VI
2x 3Ö
I =V x
(RMSCout) O
VO
1
(7)
L x ¦
1-
+ESR
()
VI
8xC x
O¦
DV =V x
O O
VO
1
x
(8)
Input Capacitor Selection
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Table 4. Tested Inductors
Inductor Type Inductor Value Supplier
LPS3010 2.2 μH CoilcraftLPS3015 3.3 μH CoilcraftLPS4012 2.2 μH CoilcraftVLF4012 2.2 μH TDK
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramiccapacitors with a value of 22- μF (typical), without having large output voltage undershoots and overshoots duringheavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple, and arerecommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the applicationrequirements. For completeness, the RMS ripple current is calculated as:
At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple isthe sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging anddischarging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage V
I
.
At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent onthe output capacitor value. The output voltage ripple is set by the internal comparator delay and the externalcapacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor isrequired for best input voltage filtering and minimizing the interference with other circuits caused by high inputvoltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increasedwithout any limit for better input voltage filtering.
Table 5. Possible Capacitors
Capacitor Value Size Supplier Type
2.2 μF 0805 TDK C2012X5R0J226MT Ceramic2.2 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic10 μF 0805 TDK C2012X5R0J106M Ceramic10 μF 0603 Taiyo Yuden JMK107BJ106MA Ceramic
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Low Drop Out Voltage Regulators (LDOs)
R6
R5
V =
OV x1+
ref ()
(9)
V(FB_LDOs)
VO
R5 =R6 x -R6
()
R6
R5+R6
V =V
O (FB_LDOs) x
(10)
LAYOUT CONSIDERATIONS
Application Circuits
PB-ONOFF and Sequencing
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
The output voltage of all 4 LDOs in TPS65051, TPS65054 and TPS65056 are set by an external resistornetwork. The output voltage is calculated using Equation 9 :
with an internal reference voltage, V
ref
, 1 V (typical)
Setting the total resistance of R5 + R6 to less than 1 M Ωis recommended. Typically, there is no feedforwardcapacitor needed at the voltage dividers for the LDOs.
Typical resistor values:
Table 6. Typical Resistor Values
OUTPUT VOLTAGE R5 R6 NOMINAL VOLTAGE
3.3 V 300 k Ω130 k Ω3.31 V3 V 300 k Ω150 k Ω3 V2.85 V 240 k Ω130 k Ω2.85 V2.8 V 360 k Ω200 k Ω2.8 V2.5 V 300 k Ω200 k Ω2.5 V1.8 V 240 k Ω300 k Ω1.8 v1.5 V 150 k Ω300 k Ω1.5 V1.3 V 36 k Ω120 k Ω1.3 V1.2 V 100 k Ω510 k Ω1.19 V1.1 V 33 k Ω330 k Ω1.1 V
The PB-ONOFF output can be used to enable one or several converters. After power up, the PB_OUT pin is low,and pulls down the enable pins connected to PB_OUT; EN_DCDC1, and EN_LDO1 in Figure 24 . When PB_IN ispulled to V
CC
for longer than 32 ms, the PB_OUT pin is turned off, hence the enable pins pulled high using apull-up resistor to V
CC
. This enables the DCDC1 converter and LDO1. The output voltage of DCDC1 (V
OUT
1) isused as the enable signal for DCDC2 and LDO2 to LDO4. LDO1 with its output voltage of 3.3 V and LDO2 for anoutput voltage of 2.5 V are powered from the battery (V
(bat)
) directly. To save power, the input voltage for thelower voltage rails at LDO3 and LDO4 are derived from the output of the step-down converters, keeping thevoltage drop at the LDOs low to increase efficiency. As LDO3 and LDO4 are powered from the output of DCDC1,the total output current on V
OUT
1, LDO3 and LDO4 must not exceed the maximum rating of DCDC1.
Figure 25 shows the power up timing for this application.
28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
L2
DEFDCDC2
PB_OUT
PB_IN
EN_DCDC1
VDCDC2
PGND2
AGND
EN_LDO1
EN_DCDC2
VLDO3
VINDCDC1/2
L1
FB_DCDC1
PGND1
VLDO1
VIN_LDO2
VIN_LDO3/4
EN_LDO2
EN_LDO3
EN_LDO4
BP
Vout2=1.575V
Vout1=2.85V
VDCDC1
VLDO2
VLDO1=3.3V
VLDO2=2.5V
VLDO3=1.5V
VLDO4 VLDO4=1.3V
Vout1
Cff
R1
R2
R3
R4
VCC
GND
MODE
1 Fm
1W
TPS65050
Vbat
DEFLDO3
DEFLDO1
DEFLDO4
DEFLDO2
Vbat
GND
GND
Vbat
Vbat
Vbat
Vbat
Vbat VIN_LDO1
2.2 Hm
10 Fm
10 Fm
10 Fm
0.1 Fm
Vbat
2.2 Hm
4.7 Fm
4.7 Fm
2.2 Fm
2.2 Fm
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Figure 24. PB_ON/OFF Circuit
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
1.2V
32ms
170 sm
170 sm
32ms
PB_IN
EN_DCDC1
EN_LDO1
EN_DCDC2
EN_LDO3
EN_LDO4
EN_LDO2
Vout1
Vout2
VLDO1
VLDO4
VLDO2
VLDO3
Vbat
RESET
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Figure 25. Power Up Timing
TPS65051, TPS65052, TPS65054 and TPS65056 contain a comparator that are used to supervise a voltageconnected to an external voltage divider, and generate a reset signal if the voltage is lower than the threshold.The rising edge is delayed by 100 ms at the open drain RESET output. The values for the external resistors R3to R5 are calculated as follows:
V
L
= lower voltage threshold
V
H
= higher voltage threshold
V
REF
= reference voltage (1 V)
Example:
•V
L
= 3.3 V•V
H
= 3.4 VSet R5 = 100 k Ω
→R3 + R4 = 240 k Ω
→R4 = 3.03 k Ω
→R3 = 237 k Ω
30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
Vref
VL
VH
VH-VL
R3+R4=R5 x -1
R4=R5 x
()
(11)
BP
FB1
Cff
R2
R1
R5
R6
FB2 R7
R8
FB4 R11
R12
R3
R4
R9
R10
FB3
Vout1
THRESHOLD
HYSTERESIS
RESET
Vout1
1MW
R3
R4
R5
Vout1=2.85V
L2
DEFDCDC2
EN_DCDC1
VDCDC2
PGND2
AGND
EN_LDO1
EN_DCDC2
VLDO3
VINDCDC1/2
L1
FB_DCDC1
PGND1
VLDO1
VIN_LDO2
VIN_LDO3/4
EN_LDO2
EN_LDO3
EN_LDO4
Vout2=1.575V
VLDO2
VLDO1=3.3V
VLDO2=1.8V
VLDO3=1.2V
VLDO4
VLDO4=1.3V
VCC
MODE
1 Fm
1W
TPS65051
VIN_LDO1
10 Fm
10 Fm
0.1 Fm
Vbat
2.2 Hm
2.2 Hm
4.7 Fm
4.7 Fm
2.2 Fm
2.2 Fm
Vbat
Vbat
Vbat
Vbat
Vbat
2.2 Hm
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Figure 26. RESET Circuit
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
www.ti.com
TPS65050, TPS65051, TPS65052TPS65054, TPS65056
SLVS710A – JANUARY 2007 – REVISED AUGUST 2007
Revision History
Changes from Original (January 2007) to Revision A .................................................................................................... Page
•Added quantities of 3000 parts to ordering information note ................................................................................................ 2•Added Output voltage range to absolute maximum ratings table .......................................................................................... 2•Changed LDO1/2 Output voltage range maximum value to 3.6 V ........................................................................................ 3•Changed LDO3/4 Output voltage range maximum value to 3.6 V ........................................................................................ 3•Changed Output voltage 2.8-V R5 resistor value to 360 k Ωin typical resistor values table ............................................... 28
32 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65050, TPS65051, TPS65052 TPS65054, TPS65056
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS65050RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65050RSMRG4 ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65050RSMT ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65050RSMTG4 ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65051RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65051RSMRG4 ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65051RSMT ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65051RSMTG4 ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65052RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65052RSMRG4 ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65052RSMT ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65052RSMTG4 ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65054RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65054RSMRG4 ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65054RSMT ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65054RSMTG4 ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65056RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65056RSMRG4 ACTIVE VQFN RSM 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65056RSMT ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS65056RSMTG4 ACTIVE VQFN RSM 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Feb-2010
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Feb-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS65050RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65050RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65051RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65051RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65051RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65051RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65052RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65052RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65054RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65054RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65056RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65056RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65050RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65050RSMT VQFN RSM 32 250 210.0 185.0 35.0
TPS65051RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65051RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65051RSMT VQFN RSM 32 250 210.0 185.0 35.0
TPS65051RSMT VQFN RSM 32 250 210.0 185.0 35.0
TPS65052RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65052RSMT VQFN RSM 32 250 210.0 185.0 35.0
TPS65054RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65054RSMT VQFN RSM 32 250 210.0 185.0 35.0
TPS65056RSMR VQFN RSM 32 3000 367.0 367.0 35.0
TPS65056RSMT VQFN RSM 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated