ee coe <p Pp IMi bense-pac Microsystems, Inc. e) PRELIMINARY DESCRIPTION: The DPZ256X8A3 DENSE-STACK module is a revolutionary new memory subsystem using Dense-Pac Microsystems ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 2 Megabits of FLASH EEPROM ina single package envelope of 990" x .540 x .205", The DPZ256X8A3 is built with one SLCC package containing two 128K x 8 FLASH memory devices. Each SLCC is hermetically sealed making the module suitable for commercial, industrial and military applications. By using SLCCs, the Dense-Stack family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or most hybrid techniques. FEATURES: * Organization: 256K x8 * Fast Access Times: DPZ256X8A3 256K X 8 FLASH EEPROM DENSE-STACK MODULE 120*, 150, 170, 200, 250ns (max.) FUNCTIONAL BLOCK DIAGRAM * Fully Static Operation - No clock or refresh required * TTL Compatible Inputs and Outputs CE1 | MO =z * Common Data Inputs and Outputs CEQ = * Automatic Erase Function VPP @ pt | /OZ1/07 - Reduces CPU overhead OE r x * 10,000 Erase/Program Cycles (min.) WE 8 * 50- Pin PGA DENSE-STACK AS~A16 - Package * Available in commercial only. PIN-OUT DIAGRAM PIN NAMES A 8 c D E (TOP VIEW) A0-A16 Address Inputs 1 (CE N.C. JN.C. TNC. [NC. ABCODE 1/00 - 1/07 Data Input/Output 2[vss_ [Nc [N.C Fvep_ [vob 1HOO0O0 - 3[N.c. |Ai6 | We [N.C JA15 21090000] | CO, CEI Chip Enables 4[ai4_ | A12_[A7 [AB | A13 iboooe WE Write Enable 5 LAS AS__}OE | ati_ [ag 5I0OQ0000 OE Output Enable 644 AS Ag CEO | Ale 6j00000 Programming Voltage 7A) AG N.C, N.C. N.C. 7ICO000 Vpp 8 8 8 8 (N.C. N.C. N.C. N.C. N.C. BIOOOCOO (+12.5V) a9fvss_ |[1/or {1/03 [1/05 | vop 9100000 Vop Power (+5V) 18 {1/08 {1/02 4t/O4 41/06 41/07 1G@lOOO00O0 Vss Ground 30A073-03 REV. ADPZ256X8A3 Dense-Pac Microsystems, Inc. PRELIMINARY DEVICE OPERATION: The FLASH devices are electrically erasable and program- mable memories that function similarly to an EPROM device, but can be erased without being removed from the system and exposed to ultraviolet light Each 128K x 8 device can be erased individually eliminating the need to re-program the entire module when partial code changes are required. READ: With Vpp = OV to Voo (Verio), the devices are read-only memories and can be read like a standard EPROM. By selecting the device to be read (see Truth Table and Functional Block Diagram), the data programmed into the device will appear on the appropriate I/O pins. When Vpp = +12.5V + 0.5V (Vppr), reads can be accomplished in the same manner as described above but must be preceded by writing OOH to the command register prior to reading the device. When Vpp is raised to VepHi the contents of the command register default to OOH and remain that way until the command register is altered. STANDBY: When the appropriate CEs are raised to a logic-high level, the standby operation disables the FLASH devices reducing the power consumption substantially. The outputs are placed in a high- impedance state, independent of the OF input. If the module is deselected during programming, erasure, or auloerase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. PROGRAM: The programming and erasing functions are accessed via the command register when high voltage is applied to Vep. The contents of the command register control the functions of the memory device (see Command Definition Table). The command register is not an addressable memory location. The register stores the address, data, and command informa- tion required to execute the command. When Vpp = Verio the command register is reset to OOH returning the device to the read-only mode. The command register is written by enabling the device upon which that the operation is to be performed (see Functional Block Diagram). While the device is enabled bring WE to a logic-low (Vit). The address is latched on the falling edge of WE and data is latched on the rising edge of WE. Programming is initiated by writing 40H (program setup command) to the command register. On the next falling edge of WE the address to be programmed will be latched, followed by the data being latched on the rising edge of WE (see AC Operating and Characteristics Table). PROGRAM VERIFY: > The FLASH devices. are programmed one location at a time. Each location may be programmed sequentially or at random. Following each programming operation, the data written must be verified. To initiate the program-verify mode, COH must be written to the command register of the device just programmed. The programming operation is terminated on the rising edge of The program-verify command is then written to the command register. After the program-verify command is written to the command register, the memory device applies an internally generated margin voltage to the location just written. After waiting 6ps the data written can be verified by doing a read. If true data is read from the device, the location write was successful and the next location may be programmed. If the device fails to verify, the program/verify operation is repeated up to 20 times. ERASE: The erase function is a command-only operation and can only be executed while Vpp = Vepri. To setup the chip-erase, 20H must be written to the command register. The chip-erase is then executed by once again writing 20H to the command register (see AC Operating and Charac- terstics Table). To ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data OOH) prior to starting the erase operation. With the algorithm provided, this operation should take approximately 8 seconds (typ.). ERASE VERIFY: The erase operation erases all locations in the device selected in parallel. Upon completion of the erase operation, each location must be verified. This operation is initiated by writing AOH to the command register. The address to be verified must be supplied in order to be latched on the falling edge of WE. The memory device internally generates a margin voltage and applies it to the addressed location. If FFH is read from the device, it indicates the location is erased. The erase/verify command is issued prior to each location verification to latch the address of the location to be verified. This continues until FFH is not read from the device or the last address for the device being erased is read. If FFH is not read from the location being verified, an addition- al erase operation is performed. Verification then resumes from the last location verified. Once all locations in the device being erased are verified, the erase operation is complete. The verify opertation should now be terminated by writing a valid command such as program set-up to the command register. 30A073-03 REV.ADense-Pac Microsystems, Inc. DPZ256X8A3 PRELIMINARY AUTOMATIC ERASE: An automatic erase function is also available eliminating the need to program all locations to OOH or do an erase verify. The automatic erase will program all locations to OOH and do a continuous erase/verify until all locations in the device are erased. To setup the chip-erase, 30H must be written to the command register. The chip-erase is then executed by once again writing 30H to the command register (see AC Operating Charac- teristics Table). To determine if the automatic erase cycle is complete, the most-significant I/O pin for the device being erased (1/O7) is read. If the data on this bit = 0 the cycle is not complete. The erase cycle is complete when the data = 1 on 1/07 for the device being erased. DESIGN CONSIDERATIONS: Vep traces should use trace widths and layout considerations comparable to that of the Voo power bus. The Vpp supply traces should also be decoupled to help decrease voltage spikes. Power-up sequencing should be such that Vpp doesnt go above Vop + 2.0V before Vpop reaches a steady state voltage, while on power-down Vpp should be below Vpp + 2.0V before Vop is lowered. Itis recommended that a 4.7pF to 10yF electrolytic capacitor be placed near the memory module connected across Voo and Vss for bulk storage. Decoupling capacitors should also be placed near the module, connected across Vpp and Vss. COMMAND DEFINITION TABLE Bus First Bus Cycle Second Bus Cycle COMMAND Cycles Req'd Operation Address Data Operation Address Data Read Memory 1 Write x OOH . : : Setup Erase / Erase 2 Write x 20H Write x 20H Erase Verify 2 Write EA AOH Read x EVD Setup Autoerase / Autoerase 2 Write x 30H Write x 30H Setup Program / Program 2 Write xX 40H Write PA PD Program Verify 2 Write xX COH Read xX PvD Reset 2 Write x FFH Write x FFH EA = Address to Verify PA = Address to Program EVD = Data Read from Location EA PD = Data to be Programmed at Location PA PVA= Data to be Read from Location PA at Program Verify TRUTH TABLE DESCRIPTION Not Selected Disable Read Not Selected Disable Read Write WE COMMAND PROGRAM Current Active OE x H L x H L H 30A073-03 REV.ADPZ256X8A3 Dense-Pac Microsystems, Inc, PRELIMINARY RECOMMENDED OPERATING RANGE! CAPACITANCE ?: Ta = F = 1.0MHz Symbol Characteristic Min. | Typ.| Max. | Unit Parameter Max.| Unit Vop {| Supply Voltage 45,50! 5.5 Vv Capr 20 Ver | Programming Voltage? | 12.0]12.5/ 13.0 | V Cce 10 Vit__| Input LOW Voltage __|-0.33 08 {Vv Gwe_| Write 20 | pF | Vi =0Vv Vin Input HIGH Voltage 2.2 Voot1.0] V Coe 20 Ta _| Operating Temp. 55 | +25] +125 | C Data 25 ABSOLUTE MAXIMUM RATINGS 4 Symbol Parameter Value Unit Tstc | Storage Temperature 65 to +150 C Tatas | Temperature Under Bias 55 to +125 Cc Vio _| Input/Output Voltage 0.6to+t702 | V DC OUTPUT CHARACTERISTICS Vep Supply Voltage | Parameter Max. Vee During Erase/Program 0.6 to+14.0 | Vv ~400pA - Vop | Supply Voltage ! -0.6 to +7.0 Vv =2.1mA DC OPERATING CHARACTERISTICS: Over operating ranges Limits Symbol Characteristics Test Conditions us Min. Max. Unit lin Input Leakage Current Vin = OV to Voo . 4 +14 pA lout Output Vyo = OV to Voo, . Leakage Current ce or OF = Vin, or WE = Vin 4 +14 HA lec Active CE = Vin, Vin = Vic of Ving Supply Current lout = OmA, f = OMHz ? 16 mA tec2 Operating CE = Viz, Vin = Vis or Ving Supply Current lout = OmA, f = 8MHz 25 50 mA loca Voo Programming Current Programming in Progress 3 20 mA lees Voo Erase Current Erasure in Progress 11 40 mA Isar Standby Current (TTt) CE = Vin 2 mA 1562 Full Standby Supply Current (CMOS) | CE = Vpp 0.2V 400 pA bps Vep Leakage Current Vee Verio 40 pA lepy Vere Read Current Vee = Veprt 3 mA Ipp2 Ver Programming Current Vee = Veera, Programming in Progress 4.2 30 mA Spps Vep Erase Current Vep = Vera, Erasure in Progress 35S 80 mA * Typical measurements made at +25C, Cycle = min, Voo = S.OV. 4 3007303 REV.ADense-Pac Microsystems, Inc. D PZ2 5 6X8A3 PRELIMINARY AC TEST CONDITIONS input Pulse Levels OV to 3.0V Figure 1. Output Load Input Pulse Rise and Fall Times 5ns * Including Probe and Jig Capacitance. Input and Output Timing Reference Levels 1.5V +3V Output Timing Reference Levels Durring Verify 0.8 and 2.4V 1.8KQ Dout OUTPUT LOAD Cc 13Ka Load CL Parameters Measured T 1 100 pF] except tor = > 2 30 pF{ tor AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No.| Symbol Parameter 1 20 1 50 au 70 - -200 2 50 | Unit Min, | Maic| Min, | Max,| Min, | Max,| Min.| Max.| Min.| Max, 1 tce Chip Enable Access Time 120 150 170 200 250| ns 2 tacc Address Access Time 420 150 170 200 250) ns 3 toe Output Enabe Access Time 60 70 75 80 90} ns 4 tor Output Disable to Output in HIGH-Z 5. 6 0 | 40| 0 | 50; 0 | 55 60 70 | __ns 5 ton Output Hold from Address Change 5 5 5 5 5 ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges -120 -150 170 -200 | -250 ; No.| Symbol Parameter Min. |Max.! Min. | Max.| Min.| Max.| Min.| Max.| Min,| Max. Unit 6 tewc Write Cycle Time 120 150 170 200 250 ns 7 tas Address Selup Time 0 0 0 0 0 ns 8 taH Address Hold Time 60 60 60 60 60 ns 9 tos Data Setup Time 50 50 50 50 50 ns 10 tou Data Hold Time 10 10 10 10 10 ns a tces Chip Enable Setup Time 0 0 0 0 0 ns 12 tcrH Chip Enable Hold Time 15 15 15 15 15 ns 13 tves Vpp Setup Time 7:8 100 100 100 100 100 ns 14} tver Ver Hold Time 7. 8 100 100 100 100 100 ns 15 twee Write Enable Pulse Width 70 70 80 80 90 ns 16 tWEH Write Enable Pulse Width HIGH Time 20 20 20 20 20 ns Output Enable Setup Time before . 17 | lorws | Command Programming 0 o 0 0 o ns 18 | toers {| Output Enable Setup Time before Verify 6 6 6 6 6 ps 19 tva Verify Access Time 120 150 170 200 250| ns 20 | _toeps Output Enable Setup Time before Status Polling | 20 20 20 20 20 ns 21 ispa Status Polling Access Time 120 150 170 200 250} ns 22 tppw Standby Time before Programming 25 25 25 25 25 ps 23 ter Standby Time in frase 11 11 1 11 WW ms 24 tarT Total Erase Time in Autoerase 9 0.5 | 30105} 30/05] 30|05; 30 |0.5| 30 S 30A073.03 5 REV.AD PZ2 5 6X8A3 Dense-Pac Microsystems, Inc. PRELIMINARY READ CYCLE TRC ADDRESS ADDRESS VALID TCE CEo, CE1 OE WE DATA OUT OUTPUT VALID PROGRAMMING CYCLE nm SETUP PROGRAM tet Pali PROGRAM VERIFY t Vop (5.0V) TVPH TVPS 12.5V Vep 5.0V KXKKKRERRREYD ADDRESS RRR RRR TAShae- TCEH -o Tan TCER __ y- CEo, CE1 K \. / we TCEH TCES =| e- he TcES eo coe of \ 4 TCWC ~one) TPPW on toers-e| TOEWS TWEH TWEP TWEP WE Y y \ y \ y KA a, LY TVA TOF ,_10s | ToH Ts | TH tos | 1DH avo} DATA 1/0 wcn-z f commano DATA we comaana X ois 6 30A073-03DPZ256X8A3 Dense-Pac Microsystems, Inc. PRELIMINARY AUTOMATIC ERASE CYCLE patti SETUP AUTO ERASE tepe_- AUTO ERASE & STATUS PQLUNG ~m] Vop (5.0V) TVPH VPS 12.5V pp 5.0V ADDRESS XRAY RXRYD | TCEH _ TCEH CE0, CEt K TCES me TCES a TCES a OE f x TCwec. paa-TOEPS TOE WS TWEH TACT TWEP TWEP \ y \ y WE NSA LSA TOF TDS | TOH WS | Tor TSPA . Lato O07 HGH-Z COMMAND mene 1 x - pet STATUS POLLING = ~my 1/00 - 1/06 HIGH-z cownne cow NOTES: 1. 2. OPN All voltages are with respect to Vss. When operating device at temperatures less than 0C (-55C to 0C) (Vpp must be at 7.4 Vdc above Vop durring Program/Erase functions. -2.0V min. for pulse width less than 20ns (Vit min. = -0.6V at DC level). . Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This parameter is guaranteed and not 100% tested. Transition is measured at the point of t500mvV from steady state voltage. Vcc must be applied before Vpp and removed after Ver. Ver must not exceed 14V, including overshoot. . The total erase times shown are for one (1) 128Kx8 device, to erase the entire module would be 2x the times shown. 8 30A073-03 REV.ADense-Pac Microsystems, Inc. DP 2256X8A3 PRELIMINARY WRITE ALGORITHM START PROGRAMMING VPP = 12.5V WRITE SETUP PROGRAM COMMAND i WRITE VALID DATA TIME OUT 25 ys WRITE PROGRAM VERIFY COMMAND TIME OUT 6 us READ DATA FROM DEVICE YES YES SET VPP = LAST ev TO VOD +2.eV NEXT ADDRESS ADORESS YES PROGRAM ERROR WRITE READ COMMAND 1 SET VPP = QV TO VOD +2.8V PROGRAMMING COMPLETED 30A073.03 9 REV.ADPZ256X8A3 Dense-Pac Microsystems, Inc. PRELIMINARY ERASE ALGORITHM NO PROGRAM ALL LOCATIONS TO 88H ADDRESS = ADDRESS MIN. COUNT = @ WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND TIME OUT 18ms WRITE ERASE VERIFY COMMAND READ DATA FROM DEVICE INCREMENT ADORESS yes SET VPP = @v TO VOD +2.av SET VPP QV TO VOO +2.8V ERASURE COMPLETED 10 30A073-03 REV.ADense-Pac Microsystems, Inc. DP 2Z256X8A3 PRELIMINARY AUTOMATIC ERASE START AUTOMATIC ERASURE VPP = 12.5V WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND STATUS POLLING ON 1/07 38 SECONDS LATER ? 1 READ COMMAND SET VPP = BV TO VOD +2.8V ERASURE COMPLETED 30A073-03 REV. A 1DPZ256X8A3 Dense-Pac Microsystems, Inc. PRELIMINARY ORDERING INFORMATION DP_ Z256X8 A3 XX xX PREFIX DEVICE TYPE PACKAGE SPEED GRADE C COMMERCIAL OC to +70 | INDUSTRIAL -48C to +85'C M MILITARY -55'C to +125C B MIL-PROCESSED -55C to +125 DENSE-PAT 12 12@ns (COMMERCIAL ONLY) 15 15@ns 17 178ns 28 280ns 25 258ns rrr 53 PIN GRID ARRAY (PGA)/(3-D) DENSE~STACK 256K x 8 FLASH EEPROM a MECHANICAL DRAWING fb -998+.018 | TOP vViEW ND PIN AI VEW INDEX 540+.006 [ -205 MAX. LOTTO, 058 TYP. LUTTE C 1 [ = SIDE 7 | | vie iil | | 7-180 REF. | I us UJ U Ly fo .0580 DIA. +.085 .- O45 REF. .188 TYP. a es DIA. +.282 198 TYP. 408.005 .900+,005 Dense-Pac Microsystems, Inc. 7321 Lincoln Way @ Garden Grove, California 92641-1428 (714) 898-0007 @ (800) 642-4477 (Outside CA) @ FAX: (714) 897-1772 12 30A073-03 REV.A