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LM108AJAN Operational Amplifiers
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1FEATURES DESCRIPTION
The LM108 is a precision operational amplifier having
2• Maximum Input Bias Current of 3.0 nA over specifications a factor of ten better than FET
Temperature amplifiers over a −55°C to +125°C temperature
• Offset Current less than 400 pA over range.
Temperature The devices operate with supply voltages from ±2V to
• Supply Current of only 300 μA, even in ±20V and have sufficient supply rejection to use
Saturation unregulated supplies. Although the circuit is
• Ensured Drift Characteristics interchangeable with, and uses the same
compensation as the LM101A, an alternate
compensation scheme can be used to make it
particularly insensitive to power supply noise and to
make supply bypass capacitors unnecessary.
The low current error of the LM108 makes possible
many designs that are not practical with conventional
amplifiers. In fact, it operates from 10 MΩsource
resistances, introducing less error than devices such
as the 709 with 10 kΩsources. Integrators with drifts
less than 500 μV/sec and analog time delays in
excess of one hour can be made using capacitors no
larger than 1 μF.
Connection Diagrams
*Package is connected to Pin 4 (V−)
**Unused pin (no internal connection) to allow for input anti-leakage
guard ring on printed circuit board layout.
Figure 1. Metal Can Package - TO-99 Figure 2. Dual-In-Line Package (Top View)
Package Number LMC CDIP - Package Number NAB
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Compensation Circuits
Standard Compensation Circuit Alternate Frequency Compensation
**Bandwidth and slew rate are proportional to 1/CS
Improves rejection of power supply noise by a factor of ten.
CO= 30 pF
**Bandwidth and slew rate are proportional to 1/CfFeedforward Compensation
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Supply Voltage ±22V
TO-99 Metal Can 8LD 330mW @ +125°C
CDIP 14LD 400mW @ +125°C
Power Dissipation(2) CDIP 8LD 400mW @ +125°C
CLGA 10LD 330mW @ +125°C
Ceramic SOIC 10LD 330mW @ +125°C
Differential Input Current(3) ±10 mA
Differential Input Voltage(4) ±30V
Input Voltage(5) ±20V
Output Short-Circuit Duration Continuous
Operating Temperature Range −55°C ≤TA≤+125°C
Storage Temperature Range −65°C ≤TA≤+150°C
TO-99 Metal Can 8LD Still Air 150°C/W
500LF / Min Air Flow 86°C/W
CDIP 14LD Still Air 94°C/W
500LF / Min Air Flow 55°C/W
CDIP 8LD Still Air 120°C/W
θJA 500LF / Min Air Flow 68°C/W
CPACK 10LD Still Air 225°C/W
500LF / Min Air Flow 142°C/W
Thermal Resistance Ceramic SOIC 10LD Still Air 225°C/W
500LF / Min Air Flow 142°C/W
TO-99 Metal Can 8LD 38°C/W
CDIP 14LD 13°C/W
θJC CDIP 8LD 17°C/W
CLGA 10LD 21°C/W
Ceramic SOIC 10LD 21°C/W
TO-99 Metal Can 8LD 990mg
CDIP 14LD 2,180mg
Package Weight (typical) CDIP 8LD 1,090mg
CLGA 10LD 225mg
Ceramic SOIC 10LD 210mg
Maximum Junction Teperature 175°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD Tolerance(6) 2000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA) /θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(3) The inputs are shunted with back-to-back diodes for over voltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some limiting resistance is used.
(4) This rating is ±1.0V unless resistances of 2KΩor greater are inserted in series with the inputs to limit current in the input shunt diodes to
the maximum allowable value.
(5) For supply voltages less than ±20V, the absolute maximum input voltage is equal to the supply voltage.
(6) Human body model, 1.5 kΩin series with 100 pF.
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Table 1. Quality Conformance InspectionMil-Std-883, Method 5005 - Group A
Subgroup Description Temp (°C)
1 Static tests at +25°C
2 Static tests at +125°C
3 Static tests at −55°C
4 Dynamic tests at +25°C
5 Dynamic tests at +125°C
6 Dynamic tests at −55°C
7 Functional tests at +25°C
8A Functional tests at +125°C
8B Functional tests at −55°C
9 Switching tests at +25°C
10 Switching tests at +125°C
11 Switching tests at −55°C
LM108A Electrical Characteristics DC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
DC: +VCC = +20V, −VCC =−20V, VCM = 0V, RS= 50Ω
Sub-
Symbol Parameter Conditions Notes Min Max Units groups
VIO -0.5 0.5 mV 1
+VCC = 35V, -VCC = -5V,
VCM = -15V -1 1 mV 2, 3
-0.5 0.5 mV 1
+VCC = 5V, -VCC = -35V,
VCM = 15V -1 1 mV 2, 3
Input Offset Voltage -0.5 0.5 mV 1
-1 1 mV 2, 3
-0.5 0.5 mV 1
+VCC = +5V, -VCC = -5V -1 1 mV 2, 3
Delta VIO / 25°C ≤TA≤+125°C See(1) -5 5 µV/°C 2
Temperature Coeffient of Input
Delta T Offset Voltage 25°C ≤TA≤-55°C See(1) -5 5 µV/°C 3
IIO -0.2 0.2 nA 1
+VCC = 35V, -VCC = -5V,
VCM = -15V -0.4 0.4 nA 2, 3
-0.2 0.2 nA 1
+VCC = 5V, -VCC = -35V,
VCM = 15V -0.4 0.4 nA 2, 3
Input Offset Current -0.2 0.2 nA 1
-0.4 0.4 nA 2, 3
-0.2 0.2 nA 1
+VCC = +5V, -VCC = -5V -0.4 0.4 nA 2, 3
Delta IIO / 25°C ≤TA≤+125°C See(1) -2.5 2.5 pA/°C 2
Temperature Coeffient of Input
Delta T Offset Current 25°C ≤TA≤-55°C See(1) -2.5 2.5 pA/°C 3
(1) Calculated parameter
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LM108A Electrical Characteristics DC Parameters (continued)
The following conditions apply to all the following parameters, unless otherwise specified.
DC: +VCC = +20V, −VCC =−20V, VCM = 0V, RS= 50Ω
Sub-
Symbol Parameter Conditions Notes Min Max Units groups
±IIB -0.1 2 nA 1
+VCC = 35V, -VCC = -5V, -1 2 nA 2
VCM = -15V -0.1 3 nA 3
-0.1 2 nA 1
+VCC = 5V, -VCC = -35V, -1 2 nA 2
VCM = 15V -0.1 3 nA 3
Input Bias Current -0.1 2 nA 1
-1 2 nA 2
-0.1 3 nA 3
-0.1 2 nA 1
+VCC = +5V, -VCC = -5V -1 2 nA 2
-0.1 3 nA 3
+PSRR Power Supply Rejection Ratio +VCC = 10V, -VCC = -20V -16 16 µV/V 1, 2, 3
-PSRR Power Supply Rejection Ratio +VCC = 20V, -VCC = -10V -16 16 µV/V 1, 2, 3
CMRR Common Mode Rejection Ratio VCM = ±15V 96 dB 1, 2, 3
+IOS +VCC = +15V, -VCC = -15V,
Short Circuit Current -20 mA 1, 2, 3
t≤25mS
−IOS +VCC = +15V, -VCC = -15V,
Short Circuit Current 20 mA 1, 2, 3
t≤25mS
ICC 0.6 mA 1, 2
Power Supply Current +VCC = +15V, -VCC = -15V 0.8 mA 3
+VOP Output Voltage Swing RL= 10KΩ16 V 4, 5, 6
−VOP Output Voltage Swing RL= 10KΩ-16 V 4, 5, 6
+AVS See(2) 80 V/mV 4
Open Loop Voltage Gain RL= 10KΩ, VO= +15V See(2) 40 V/mV 5, 6
−AVS See(2) 80 V/mV 4
Open Loop Voltage Gain RL= 10KΩ, VO= -15V See(2) 40 V/mV 5, 6
AVS Open Loop Voltage Gain +VCC = ±5V, RL= 10KΩ, VO= ±2V See(2) 20 V/mV 4, 5, 6
(2) Datalog reading in K = V/mV
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LM108A Electrical Characteristics AC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
AC +VCC = +20V, −VCC =−20V, VCM = 0V, RS= 50Ω
Sub-
Symbol Parameter Conditions Notes Min Max Units groups
TRTR RL= 10KΩ, CL= 100pF,
Transient Response Rise Time 1000 nS 7, 8A, 8B
f < 1KHz, VI= +50mV
TROS RL= 10KΩ, CL= 100pF,
Transient Response Overshoot 50 % 7, 8A, 8B
f < 1KHz, VI= +50mV
+SR Slew Rate AV= 1, VI= -5V to +5V 0.05 V/µS 7, 8A, 8B
−SR Slew Rate AV= 1, VI= +5V to -5V 0.05 V/µS 7, 8A, 8B
NIBB Noise Broadband BW = 10Hz to 5KHz, RS= 0Ω15 µVrms 7
NIPC Noise Popcorn BW = 10Hz to 5KHz, RS= 100KΩ40 µVpk 7
LM108A Electrical Characteristics DC Parameters Drift Values
The following conditions apply to all the following parameters, unless otherwise specified.
DC +VCC = +20V, −VCC =−20V, VCM = 0V, RS= 50Ω
Delta calculations performed on JAN S devices at group B, Subgroup 5 only. Sub-
Symbol Parameter Conditions Notes Min Max Units groups
VIO Input Offset Voltage -0.25 0.25 mV 1
±IIB Input Bias Current -0.5 0.5 nA 1
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Typical Performance Characteristics
Input Currents Offset Error
Figure 5. Figure 6.
Drift Error Input Noise Voltage
Figure 7. Figure 8.
Closed Loop
Power Supply Rejection Output Impedance
Figure 9. Figure 10.
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Typical Performance Characteristics (continued)
Voltage Gain Output Swing
Figure 11. Figure 12.
Open Loop
Supply Current Frequency Response
Figure 13. Figure 14.
Large Signal Voltage Follower
Frequency Response Pulse Response
Figure 15. Figure 16.
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Typical Applications
†Teflon polyethylene or polycarbonate dielectric capacitor
Worst case drift less than 2.5 mV/sec
Figure 17. Sample and Hold
Figure 18. High Speed Amplifier with Low Drift and Low Input Current
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*In addition to increasing speed, the LM101A raises high and low frequency gain, increases output drive capability
and eliminates thermal feedback.
Power Bandwidth: 250 KHzSmall Signal Bandwidth: 3.5 MHzSlew Rate: 10V/μS
Figure 19. Fast Summing Amplifier
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REVISION HISTORY
Date Released Revision Section Changes
1 MDS data sheets converted into one Corp.
02/25/05 A New release, corporate format datasheet format. MJLM108A-X Rev 2A0. MDS will
be archived.
All temps. +Ios from -15 mA Min to -20 mA Min and -
01/05/06 B DC Electrical's Ios from +15 mA Max to +20 mA Max
Revision C, End of Life on Product/NSID Dec.
09/24/10 C Obsolete Data Sheet 2008/09 Obsolete Data Sheet
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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