1. General description
The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The
device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial
output (Q7). When th e parallel ena ble input (PE) is LOW, the dat a from D0 to D7 is loaded
into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When
PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of
CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH
transitions of CP. A HIGH on CE disables the CP input. Input s include clamp diodes which
enable the use of current limiting resistors to interface input s to volt ages in excess of VCC.
2. Features and benefits
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standard no. 7A
Input levels:
For 74HC166: CMOS level
For 74HCT166: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A ex ce ed s 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Rev. 4 — 28 December 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC166D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT166D
74HC166DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width
5.3 mm SOT338-1
74HCT166DB
74HC166PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body
width 4.4 mm SOT403-1
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 2 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
DDD
4


'
3( '6
&3 &(
'
'
'
'
'
'
'




05
DDD

'
'

65*
5
0
&



 
'
Fig 3. Functional di agram
DDD
%,73$5$//(/6(5,$/,1
6(5,$/2876+,)75(*,67(5
'6

4
'

'
'
'

'

'

'

'
05
&3
&(
3(
© Nexperia B.V. 2017. All rights reserved
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 3 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 4. Logic diag ram
DDD
05
' ' ' ' ' ' ' '
4
&(
&3
'6
3(
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 4 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO16 and (T)SSOP16
+&
+&7
'
6
9&&
'
3(
'
'
'
4
'
'
&
(
'
&
3
'
*1' 05
DDD







Table 2. Pin description
Symbol Pin Description
DS 1 serial data input
D0 to D7 2, 3, 4, 5, 10, 11, 12, 14 parallel data inputs
CE 6 clock enable input (active LOW)
CP 7 clock input (LOW-to-HIGH edge-triggered)
GND 8 ground (0 V)
MR 9 asynchronous master reset (active LOW)
Q7 13 serial output from the last stage
PE 15 parallel enable input (active LOW)
VCC 16 positive supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 5 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]
Operating modes Inputs Qn registers Output
PE CE CP DS D0 to D7 Q0 Q1 to Q6 Q7
parallel load I I X I L L to L L
IIX h H H to H H
serial shift h I l X L q0 to q5 q6
hI h X H q0 to q5 q6
holddo nothingXHXXXq0q1 to q6q7
Fig 6. Typical clear, shift, load, inhibit, and shift sequences
+
/
+
/
+
/
+
+
ORDG DDDFOHDU
&3
05
'6
VKLIW
ORDG
'
'
'
'
'
'
'
'
4
&(
PRGH
FRQWURO
LQSXWV
SDUDOOHO
LQSXWV
RXWSXW
LQKLELW
VHULDOVKLIWVHULDOVKLIW
++ /+++
//
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 6 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 package [2] -500mW
(T)SSOP16 package [3] -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC166 74HCT166 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 7 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC166
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0 .26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0 .26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- - - - -pF
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 8 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
74HCT166
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 4.5 V - 0.16 0 .26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =4.5V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =4.5V - - 8.0 - 80 - 160 A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs - 35 126 - 157.5 - 171.5 A
CP and CE inputs - 80 288 - 360 - 39 2 A
MR input - 40 144 - 180 - 196 A
PE input - 60 216 - 270 - 294 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 9 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +1 25 CUnit
Min Typ Max Min Max Min Max
74HC166
tpd propagation
delay CP to Q7; see Figure 7 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC = 5.0 V; CL=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
MR to Q7; see Figure 8
VCC = 2.0 V - 47 160 - 200 - 240 ns
VCC = 4.5 V - 17 32 - 40 - 48 ns
VCC = 5.0 V; CL=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 27 - 34 - 41 ns
tttransition
time output; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
MR input LOW; see Figure 8
VCC = 2.0 V 100 25 - 125 - 150 - ns
VCC = 4.5 V 20 9 - 25 - 30 - ns
VCC = 6.0 V 17 7 - 21 - 26 - ns
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 0 19 - 0 - 0 - ns
VCC = 4.5 V 0 7- 0 - 0 - ns
VCC = 6.0 V 0 6- 0 - 0 - ns
tsu set-up time Dn, CE to CP; see Figure 9
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
PE to CP; see Figure 9
VCC = 2.0 V 100 33 - 125 - 150 - ns
VCC = 4.5 V 20 12 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 10 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
thhold time Dn, CE to CP; see Figure 9
VCC = 2.0 V 2 8- 2 - 2 - ns
VCC = 4.5 V 2 3- 2 - 2 - ns
VCC = 6.0 V 2 2- 2 - 2 - ns
PE to CP; see Figure 9
VCC = 2.0 V 0 28 - 0 - 0 - ns
VCC = 4.5 V 0 10 - 0 - 0 - ns
VCC = 6.0 V 0 8- 0 - 0 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 6 19 - 4.8 - 4 - MHz
VCC = 4.5 V 30 57 - 24 - 20 - MHz
VCC = 5.0 V; CL=15pF - 63 - - - - - MHz
VCC = 6.0 V 35 68 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -41- - - - - pF
74HCT166
tpd propagation
delay CP to Q7; see Figure 7 [1]
VCC = 4.5 V - 23 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
MR to Q7; see Figure 8
VCC = 4.5 V - 22 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 19 - - - - - ns
tttransition
time output; see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 4.5 V 20 9 - 25 - 30 - ns
MR input LOW; see Figure 8
VCC = 4.5 V 25 11 - 31 - 38 - ns
trec recovery time MR to CP; see Figure 8
VCC = 4.5 V 0 7- 0 - 0 - ns
tsu set-up time Dn, CE to CP; see Figure 9
VCC = 4.5 V 16 8 - 20 - 24 - ns
PE to CP; see Figure 9
VCC = 4.5 V 30 15 - 38 - 45 - ns
thhold time Dn, CE to CP; see Figure 9
VCC = 4.5 V 0 3- 0 - 0 - ns
PE to CP; see Figure 9
VCC = 4.5 V 0 13 - 0 - 0 - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +1 25 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 11 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 25 45 - 20 - 17 - MHz
VCC = 5.0 V; CL=15pF - 50 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -41- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +1 25 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
DDD
&3LQSXW
4RXWSXW

 

*1'
90
9,
92+
92/
90
W:
W3+/ W3/+
W7/+
W7+/
IPD[
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 12 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Master rese t (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
DDD
4RXWSXW
90
W3+/
90
05LQSXW
90
W:
9
,
*1'
WUHF
9,
92+
92/
*1'
&
3LQSXW
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
DDD
90
9,
*1'
9,
*1'
9,
*1'
9,
*1'
9,
*1'
90
VHHQRWH
&(LQSXW
3(LQSXW
'QLQSXW
90
90
'6LQSXW
VWDEOH
90
&3
LQSXW
FRQGLWLRQ05 +,*+
VWDEOH
WK
WK
WK
WVX WVX WVX
WK
WK
WVX
WK
WVX
WKW:
WVX
WVX
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 13 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Table 8. Measurement points
Type Input Output
VIVMVM
74HC166 VCC 0.5VCC 0.5VCC
74HCT166 3 V 1.3 V 1.3 V
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 10. Test circuit for measuring switching times
9
0
9
0
W
:
W
:


9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0


W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC166 VCC 6ns 15pF, 50 pF 1kopen
74HCT166 3V 6ns 15pF, 50 pF 1kopen
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 14 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
12. Package outline
Fig 11. Package outline SOT109-1 (SO16)
;
Z 0
ș
$
$

$

E
S
'
+
(
/
S
4
GHWDLO;
(
=
H
F
/
Y 0 $
$

$




\
SLQLQGH[
81,7 $
PD[ $
 $
 $
 E
S F '
 (
 
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
LQFKHV
 


  






  




 

R
R
 
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627 

( 06
 


  






 










 


  PP
VFDOH
62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 15 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 12. Package outline SOT338-1 (SSOP16)
81,7 $
 $
 $
 E
S F '
 ( H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 


  






  










R
R
 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
627 


Z 0
E
S
'
+
(
(
=
H
F
Y 0 $
;
$
\
 
 
ș
$
$

$

/
S
4
GHWDLO;
/
$

02
SLQLQGH[
  PP
VFDOH
6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
$
PD[

© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 16 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 13. Package outline SOT403-1 (TSSOP16)
81,7 $
 $
 $
 E
S F ' ( 
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 










  







R
R
 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627 02 

Z 0
E
S
'
=
H

 
 
ș
$
$

$

/
S
4
GHWDLO;
/
$

+
(
(
F
Y 0 $
;
$
\
  PP
VFDOH
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
$
PD[

SLQLQGH[
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 17 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
13. Abbreviations
14. Revision history
Table 10. Ab breviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT166 v.4 20151228 Product data sheet - 74HC_HCT166 v.3
Modifications: Type numbers 74HC 166N and 74HCT166N (SOT38-4) removed.
74HC_HCT166 v.3 20130911 Product data sheet - 74HC_HCT166_CNV v.2
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Family data added, see Section 9 “S tatic characteristics
74HC_HCT166_CNV v.2 December 1990 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 18 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descri bed in this d ocument may have change d since this d ocument was p ublished and may dif fer in case of multiple devices. The latest product st atus
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full dat a sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the shor t data sheet, the
full data sheet shall pre va il.
Product specificatio n The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in app lications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings onl y and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT166 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 28 December 2015 19 of 20
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such au tomotive applicat ions, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
28 December 2015