ICs for Communications ISAC-SX TE ISDN Subscriber Access Controller for Terminals PSB 3186 Version 1.1 Product Overview 09.99 DS 1 PSB 3186 Revision History: Current Version: 09.99 Previous Version: Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com A BM (R) , A O P(R) , A RCOFI (R) , ARC OFI (R)-BA , A RCOFI (R) -S P, Dig iTa pe(R) , E PIC (R) -1 , EP IC(R) - S, E LIC (R) , FAL C (R) 54 , FAL C(R) 56, FA LC (R) -E 1, FAL C (R)-LH, IDEC (R) , IO M (R) , IO M (R)-1, IOM (R) -2 , IP AT (R) -2 , ISA C (R) -P , ISA C (R)-S, ISA C (R)-S TE , ISA C (R)-P TE , ITA C(R) , IWE(R) , MUSA C (R) -A , O CTAT (R) -P , Q UA T(R) - S, SICAT (R) , SICO FI(R) , SICO FI(R) -2 , S ICOFI (R)-4, SICO FI (R) - 4C , S LICO FI(R) ar e re gistere d trad em arks of In fi ne on Te ch no log ies A G. A CETM, AS M TM , AS PTM, P O TSWIRE TM , Qu ad FAL CTM , SCO UT TM, SIUC TM are trad ema rks of Infin eo n Tech nol ogi es AG . Edition 09.9 9 Published by Infineon Tec hnologie s AG , TR, Balans trae 7 3, 81 541 Munche n (c) In fine on Te chno log ies A G 19 99 . All Rig hts Rese rved . Atte ntion plea se ! As far as pa tents or o th er r igh ts of th ird par ti es are co nce rne d, liab ility is o nly a ssu med fo r comp one nts, n ot fo r ap plica ti ons, pro cesses a nd circu its im ple men te d withi n comp on ents or a sse mbl ies. The in forma tion d escrib es the type o f co mpo ne nt a nd sh all n ot be co nsid ere d as assu red ch ara cteristics. Terms o f de live ry a nd r igh ts to cha ng e de sign r eser ved. Due to tech nica l req uir eme nts co mpo ne nts m ay co ntai n da ng ero us sub sta nces. For in fo rma ti on o n the type s in qu estion p lea se con ta ct yo ur ne ar est Infin eo n Tech nol ogi es Office. In fine on Te chno log ies A G is an a pp rove d CEC C ma nu fa cture r. Pa ck ing Ple ase u se the re cycl ing o pe rato rs kn own to yo u. We can a lso h elp yo u - ge t in to uch wi th yo ur n ear est sa les office. B y ag ree men t we wi ll ta ke pa cking ma teria l ba ck, if it is sor te d. Yo u must bea r the co sts of tr an sp or t. For packin g m ateri al tha t is re tu rn ed to us u nso rted or w hich we a re not o bli ged to a ccept, we shal l ha ve to invoice yo u fo r an y costs incu rre d. Compone nts us ed in life- support dev ic es or sy ste m s mus t be ex press ly authorized for suc h purpose ! Critical com pon en ts 1 o f the Infin eo n Techn olo gi es AG , may on ly b e used in li fe -sup po rt d evices or syste ms 2 with th e exp ress written a pp ro va l of th e Infine on Te chn olo gie s A G . 1 A critical co mpo nen t i s a co mpo nen t u sed in a life-su pp ort de vice or system who se failu re ca n rea son abl y b e expe cte d to ca use th e fa ilu re of tha t life- supp or t de vi ce o r system, o r to a ffect i ts sa fety or e ffective ness of tha t devi ce or syste m. 2 Life sup po rt d evice s o r syste ms a re in tend ed ( a) to be impl ante d in the h uma n bo dy, or (b ) to supp or t an d/or main ta in a nd su sta in hu man life. If th ey fail, it is r easo na ble to a ssume tha t the he alth of the u ser ma y b e en dan ge red . PSB 3186 Table of Contents Page 1 1.1 1.2 1.3 Overview . . . . . . . . Features . . . . . . . . . Logic Symbol . . . . . Typical Applications 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Functional B lock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 Comparison between ISAC-S TE and ISAC-SX TE . . . . . . . . . . . . . . . . . 16 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 .5 .6 .7 09.99 PSB 3186 1 Overview The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a Dchannel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN. It is the successor of the ISAC -S TE PSB 2186 in 3.3 V technology. The system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. They include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. The ISAC-SX TE also provides a serial control interface (SCI). The FIFO size of the cyclic D-channel buffer is 64 bytes per direction with programmable block size (threshold). The S-transceiver supports terminals mode (TE), activation / deactivation, timing recovery and D -channel access control and priority control. One LED output which is capable to indicate the activation status of the S-interface automatically or can be programmed by the host. The ISAC -SX TE is produced in advanced C MOS technology. Product Overview 4 09.99 PSB 3186 1.1 Features * Full duplex 2B + D S/T interface transceiver according to ITU-T I.430 * Successor of ISAC-S TE PSB 2186 in 3.3V technology * 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus type multiplexed or non-multiplexed, P-MQFP-64 direct-/indirect register addressing * Serial control interface (SCI) * Microcontroller access to all IOM-2 timeslots * Various types of protocol support (Non-auto mode, transparent mode, extended transparent mode) * D-channel HDLC controller with 2 x 64 byte FIFOs * IOM-2 interface in TE mode, single/double clocks P-TQFP-64-1 * One serial data strobe signal (SDS) * Monitor channel handler (master/slave) P-TQFP-64 * IOM-2 MONITOR and C/I-channel protocol to control peripheral devices * Conversion of the frame structure between the S/T-interface and IOM-2 * Receive timing recovery * D-channel access control * Activation and deactivation procedures with automatic activation from power down state * Access to S and Q bits of S/T-interface * Adaptively switched receive thresholds * Two programmable timers * Watchdog timer * Software R eset * One LED pin automatically indicating layer 1 activated state * Test loops * Sophisticated power management for restricted pow er mode * Power supply 3.3 V * 3.3 V output drivers, inputs are 5 V safe * Advanced CMOS technology Type Package PSB 3186 P-MQFP-64 P-TQFP-64 Product Overview 5 09.99 PSB 3186 1.2 Logic Symbol The logic symbol gives an overview of the ISAC-SX TE functions. IOM-2 Interface +3.3V 0V DD DU FSC DCL BCL SDS 0V VDD VSS T P VDDA VSSA RD / DS C768 WR / R/W 7.68 MHz output ALE A0...7 XTAL2 AD0...4 XTAL1 7.68 MHz 100ppm AD5 / SCL Host Interface AD6 / SDR SR1 AD7 / SDX SR2 S Interface CS SX1 INT SX2 RES RST O Figure 1 ACL AMODE EAW LED Output Address Mode Setting External Awake 3186_17 Logic Symbol of the ISAC-SX TE Product Overview 6 09.99 PSB 3186 1.3 Typical Applications The ISAC-SX TE is designed for the user area of the ISDN basic access, especially for subscriber terminal equipment with S interface. Figure Chapter 2 illustrates the general application fields of the ISAC-SX TE. PBX (NT2) TE(1) TE(8) S CP SN TE(1) U T LT-S LT-T NT1 LT-S CP = Central Processor Line Card TE(1) TE(8) R = ISAC -SSX TETE SN = Switching Network Direct Subscriber Access (point-to-point, short and extended passive Bus) U S NT1 ITS05407 Figure 2 Applications of the ISAC-SX TE Product Overview 7 09.99 PSB 3186 2 Pin Configuration VSS VDD XTAL1 AMODE VSS XTAL2 RD / DS WR / R/W n.c. ALE SX2 SX1 VDDA VSSA SR2 SR1 P-MQFP-64 P-TQFP-64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BCL DU 49 50 32 31 DD FSC 51 30 res_c res_c 52 53 29 28 SDS res. 54 55 27 26 C768 A7 25 A6 24 23 22 A5 60 61 62 21 20 19 A2 A1 63 18 A0 VDD 64 17 VSS DCL VSS VSS VDD res_l EAW ACL res_c res_c res_c res_c res_c ISAC-SX TE PSB 3186 56 57 58 59 res_c A4 A3 Figure 3 SDR / AD6 SDX / AD7 SCL / AD5 AD4 AD3 AD1 AD2 AD0 VSS VDD R ES RSTO CS TP INT n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3186_ 22 Pin C onfiguration of the ISAC-SX TE Product Overview 8 09.99 PSB 3186 Table 1 ISAC-SX TE Pin Definitions and Functions Pin No. Symbol MQ FP -64 TQ FP- 64 Input (I) Output (O) Open Drain (OD) Function Host Interface 19 20 21 22 23 24 25 26 A0 A1 A2 A3 A4 A5 A6 A7 I I I I I I I I * Non-Multiplexed Bus Mode: Address Bus Address bus transfers addresses from the microcontroller to the ISAC-SX TE. For indirect address mode only A0 is valid (A1-A7 to be connected to VDD ). * Multiplexed Bus Mode: Not used in multiplexed bus mode. In this case A0A7 should directly be connected to VDD. 9 10 11 12 13 AD0 AD1 AD2 AD3 AD4 I/O I/O I/O I/O I/O * Multiplexed Bus Mode: Address/data bus Transfers addresses from the microcontroller to the ISAC-SX TE and data between the microcontroller and the ISAC-SX TE. * Non-Multiplexed Bus Mode: Data bus. Transfers data between the microcontroller and the ISAC-SX TE. 14 AD5 I/O * Multiplexed Bus Mode: Address/data bus Address/data line AD5 if the parallel interface is selected. * Non-Multiplexed Bus Mode: Data bus Data line D5 if the parallel interface is selected. SCL I SCI - Serial Clock Clock signal of the SCI interface if a serial interface is selected. Product Overview 9 09.99 PSB 3186 Table 1 ISAC-SX TE Pin Definitions and Functions (Continued) Pin No. Sym bol Input (I) Output (O) Open Drain (OD) Function AD6 I/O * Multiplexed Bus Mode: Address/data bus Address/data line AD6 if the parallel interface is selected. * Non-Multiplexed B us Mode: Data bus Data line D6 if the parallel interface is selected. SDR I SC I - Serial Data Receive Receive data line of the SC I interface if a serial interface is selected. AD7 I/O * Multiplexed Bus Mode: Address/data bus Address/data line AD7 if the parallel interface is selected. * Non-Multiplexed B us Mode: Data bus Data line D7 if the parallel interface is selected. SDX OD SC I - Serial Data Transmit Transmit data line of the SCI interface if a serial interface is selected. RD I DS I Read Indicates a read access to the registers (Siemens/ Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). WR I R/W I MQ FP- 64 TQ FP-6 4 15 16 39 40 Product Overview Write Indicates a w rite access to the registers (Siemens/ Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). 10 09.99 PSB 3186 Table 1 ISAC-SX TE Pin Definitions and Functions (Continued) Pin No. Symbol MQ FP -64 TQ FP- 64 Input (I) Output (O) Open Drain (OD) Function 41 ALE I Address Latch Enable A HIGH on this line indicates an address on the external address/data bus (multiplexed bus type only). ALE also selects the microcontroller interface bus type (multiplexed or non multiplexed). 3 CS I Chip Select A low level indicates a microcontroller access to the ISAC-SX TE. 1 INT OD (O) Interrupt Request INT becomes active low (open drain) if the ISACSX TE requests an interrupt. The polarity can be reprogrammed to high active with push-pull characteristic. 5 RES I Reset A LOW on this input forces the ISAC-SX TE into a reset state. AMODE I Address Mode Selects between direct (0) and indirect (1) register access mode. 38 IOM-2 Interface 52 FSC O Frame Sync 8-kHz frame synchronization signal. 53 DCL O Data Clock IOM-2 interface data clock signal 1.536 MHz (double bit clock). 49 BCL O Bit Clock IOM-2 interface bit clock signal 768 kHz (single bit clock). 51 DD O (OD) Data Downstream IOM-2 data signal in dow nstream direction. Product Overview 11 09.99 PSB 3186 Table 1 ISAC-SX TE Pin Definitions and Functions (Continued) Pin No. Sym bol MQ FP- 64 TQ FP-6 4 Input (I) Output (O) Open Drain (OD) Function 50 DU I Data Upstream IOM-2 data signal in upstream direction. 29 SDS I Serial Data Strobe Programmable strobe signal for time slot and/or Dchannel indication on IOM-2. Miscellaneous 43 44 SX1 SX2 O O S-Bus Transmitter Output (positive ) S-Bus Transmitter Output (negative ) 47 48 SR1 SR2 I I S-Bus Receiver Input S-Bus Receiver Input 35 XTAL1 I 36 XTAL2 O Crystal 1 Connection for a crystal or used as external clock input. 7.68 MHz clock or crystal required. Crystal 2 Connection for a crystal. Not connected if an external clock is supplied to XTAL1. 58 EAW I External Awake If a falling edge on this input is detected, the ISACSX TE generates an interrupt and, if enabled, a reset pulse. 59 ACL O Activation LED This pin can either function as a programmable output or it can automatically indicate the activated state of the S interface by a logic '0'. An LED with pre-resistance may directly be connected to ACL . 27 C768 O Clock Output A 7.68 MHz clock is output to support other devices. This clock is not synchronous to the S interface. 6 RSTO OD Reset Output Low active reset output, either from a watchdog timeout or programmed by the host. Product Overview 12 09.99 PSB 3186 Table 1 ISAC-SX TE Pin Definitions and Functions (Continued) Pin No. Sym bol MQ FP- 64 TQ FP-6 4 Input (I) Output (O) Open Drain (OD) Function 4 TP I Test Pin Must be connected to VSS. 2, 42 n.c. I not connected 28, 29 res. 57 reserved These pins are reserved and should be left not connected. res_l I reserved, connect LOW This pin is reserved and must be connected to VSS. 30, 31, res_c 32, 60, 61, 62, 63, 64 I reserved, connect HIGH or LOW These pins are reserved and must be connected either to VS S or V D D. - Digital Power Supply Voltage (3.3 V 5 %) - Analog Power Supply Voltage (3.3 V 5 %) - Digital ground (0 V) - Analog ground (0 V) Power Supply 8, 18, VD D 33, 56 46 VD DA 7, 17, VSS 34, 37, 54, 55 45 VSS A Product Overview 13 09.99 PSB 3186 3 Functional Block Diagram Figure Figure 4 shows the architecture of the ISAC-SX TE containing the following functions: * S/T-interface transceiver supporting TE mode * Different host interface modes: - Parallel microcontroller interface (Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes) - Serial Control Interface (SC I) * Optional indirect register address mode reduces number of registers to be accessed to tw o locations * One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable FIFO block size (threshold) of 4, 8, 16 or 32 byte (receive) and 16 or 32 byte (transmit). * IOM-2 interface for terminal mode (TE) * One serial data strobe signals (SDS) * IOM handler with controller data access registers (CDA) allows flexible access to IOM timeslots for reading/writing, looping and shifting data * Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots * MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange * C/I-channel handler and TIC bus access controller * D-channel access mechanism * LED connected to pin AC L indicates S-interface activation status automatically or can be controlled by the host * Level detect circuit on the S interface reduces power consumption in power down mode * Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s) * Clock and timing generation * Digital PLL to synchronize the transceiver to the S/T interface * Buffered 7.68 MHz oscillator clock output allow s connection of further devices and saves another crystal on the system board * Reset generation (watchdog timer) Product Overview 14 09.99 PSB 3186 Peripheral Devices IOM-2 Interface IOM-2 Handler S Transceiver D-channel HDLC MON Handler TIC C/I RX/TX FIFOs DPLL Host Interface 8-bit parallel Reset Interrupt -generation SCI OSC 3186_18 Host Figure 4 Functional B lock Diagram of the ISAC-SX TE Product Overview 15 09.99 PSB 3186 4 Comparison between ISAC-S TE and ISAC-SX TE The following table provides an overview on the differences between the previous ISAC-S TE PSB 2186 and the new ISAC-SX TE PSB 3186. Table 2 Comparison of the ISA C-SX TE with the previous version ISAC-S TE: ISA C-SX TE PSB 3186 ISAC-S TE PSB 2186 Operating modes TE TE Supply voltage 3.3V 5 % 5V 5 % Technology CMOS CMOS Package P-MQFP-64 / P-TQFP-64 P-MQFP-64 / P-LCC-44 / P-DIP-40 Transceiver Transformer ratio for the transmitter receiver 1:1 1:1 2:1 2:1 Test Functions - Dig. loop via Layer 2 (TLP) - D ig. loop via Layer 2(TLP) - Layer 1 disable (DIS_TR) - Layer 1 disable (DIS_TR) - Analog loop (LP_A- bit - Analog loop (ARL) EXLP- bit, ARL) Microcontroller Interface Serial interface (SCI) Not provided 8-bit parallel interface: Motorola Mux Siemens/Intel Mux Siemens/Intel Non-Mux direct/ indirect Addressing 8-bit parallel interface: Motorola Mux Siemens/Intel Mux Siemens/Intel Non-Mux Command structure of the register access (SCI) Header/address/data Address/data Crystal 7.68 MHz 7.68 MH z Buffered 7.68 MHz output Provided Not provided Controller data access to IOM-2 timeslots All timeslots; various possibilities of data access Restricted access to B- and IC-channel Product Overview 16 09.99 PSB 3186 ISA C-SX TE PSB 3186 ISAC-S TE PSB 2186 Various possibilities of data control and data manipulation (enable/ disable, shifting, looping, switching) B- and IC-channel looping IOM-2 Interface Double clock (DCL), bit clock pin (BCL), serial data strobe (SDS) Double clock (DCL), bit clock (BCL), serial data strobe (SDS) Monitor channel programming Provided (MON0, 1, 2, ..., 7) Provided (MON 0 or 1) C/I channels CI0 (4bit), CI1 (4/6bit) CI0 (4bit), CI1 (6bit) Layer 1 state machine With changes for correspondence with the actual ITU specification Layer 1 state machine in software Not possible Not possible HDLC support D- and B-channel timeslots; non-auto mode, transparent mode 1-3, extended transparent mode D-channel timeslot; auto mode, non-auto mode, transparent mode 1-3 D-channel FIFO size 64 bytes cyclic buffer per direction with programmable FIFO thresholds 2x32 bytes buffer per direction Reset Signals RES input signal RSTO output signal RST input/output signal Data control and manipulation IOM-2 Product Overview 17 09.99 PSB 3186 ISA C-SX TE PSB 3186 ISAC-S TE PSB 2186 Reset Sources RES Input Watchdog C/I Code Change EAW Pin Software Reset RST Input Watchdog C/I Code Change EAW Pin Interrupt Output Signals INT low active (open drain) by default, reprogrammable to high active (push-pull) Low active INT Product Overview 18 09.99