ICs for Communications
ISAC-SX TE
ISDN Su bsc ribe r Ac ces s Con troller for T erm in als
PSB 3186 Ver sion 1.1
Product O ve rv iew 09. 99 DS 1
For questions on technol ogy, delivery and pric es please contact the Infineon Technologies Offices
in Germany or the Infi neon Technologies Companies and Representatives worldwide:
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PSB 3186
Revision History: Current Version: 09.99
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Edition 09.9 9
Published by Infineon Tec hnologie s AG ,
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81541 M ü n ch en
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PSB 3186
Table of Contents Page
Product Overview 3 09.99
1 O vervi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1 .1 Fe a tu re s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Logic Sy mbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1 .3 Ty p i ca l A p p l i ca ti o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2 Pin Configura tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3 Functional Bl ock Diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4
4 C om pa r ison be twe e n ISAC -S TE a nd ISA C -S X TE . . . . . . . . . . . . . . . . .16
PSB 3186
Product Overview 4 09.99
1 Overview
The ISDN Subscriber Access Controller for Terminals ISAC-SX TE integrates a D-
channel HDLC controller and a four wire S/ T interface used to link voice/data terminals
to t he ISDN. It is the succes sor of the ISA C- S T E PS B 2186 in 3. 3 V t ec hnology .
The system integration is simplified by several configurations of the parallel
microcontroller interface selected via pin strapping. They include multiplexed and
demultiplexed interface selection as well as the optional indirect register access
m echanis m whic h r educes the number of nec essar y r egis ters in the address spac e to 2
locations . The IS AC-S X TE also provides a s erial control inter face (S CI).
The FIFO size of the cy c lic D- channel buffer is 64 bytes per dir ect ion with pr ogr amm able
block size (threshold). The S-transceiver supports terminals mode (TE), activation /
deac tiv ation, timing r ecover y and D-c hannel acces s c ontr ol and pr ior ity c ontr ol.
One LED output which is capable to indicate the activation status of the S-interface
autom atic ally or can be program med by the hos t.
The IS A C- S X TE is pr oduced in advanc ed CMOS technology.
Product Overview 5 09.99
Type Package
PS B 3186 P-MQFP-64
P-TQFP-64
P-MQFP-64
P-TQFP-64-1
P-TQFP-64
PSB 3186
1.1 Features
• Full duplex 2B + D S/T interface transceiver
acc or ding to ITU- T I.430
• S ucces sor of ISA C-S T E PSB 2186 in
3.3V tec hnology
• 8-bit par allel micr oc ontroller interface,
M otor ola and S iem ens/Intel bus ty pe
multiplex ed or non- mult iplex ed,
direc t-/indir ect register addres sing
• Serial c ontr ol interface ( SCI )
• M icrocontroller ac cess to all IOM -2 times lot s
• V arious types of protocol s upport ( Non-auto mode,
tr ans par ent mode, ex tended trans par ent mode)
• D-c hannel HDLC c ontr oller with 2 x 64 byte FIFOs
• IOM-2 interface in TE mode, single/double clocks
• One serial data st robe signal (S DS)
• M onitor channel handler (mas ter/slave)
• IOM-2 MONITOR and C/I-channel protocol to
c ontrol peripheral devices
• Conver s ion of the fr ame s truc ture between the S /T-interface and IOM-2
• Receiv e timing recov er y
• D-c hannel ac cess c ontrol
• Activation and deactivation procedures with automatic activation from power down
state
• Ac c ess to S and Q bits of S/T-inter fac e
• Adapt iv ely s witc hed receiv e thres holds
• Two programm able timers
• Watc hdog timer
• Softwar e Reset
• One LED pin autom atically indic ating lay er 1 activ ated state
• Tes t loops
• Sophis tic ated power managem ent for r est r ic ted power mode
• Power supply 3.3 V
• 3.3 V output dr iv er s , inputs ar e 5 V s afe
• A dvanced CMOS technology
PSB 3186
Product Overview 6 09.99
1.2 Logic Symbol
The logic s y mbol gives an over v iew of the IS AC- S X TE f unct ions .
Figure 1 Logic Sym bol of the ISA C -SX TE
AD0...4
A0...7
CS
RD / DS
WR / R/W
ALE
RES
INT
DU
AD5 / SCL
AD6 / SDR
AD7 / SDX
RSTO
XTAL2
XTAL1
7.68 MHz output
7.68 MHz ± 100ppm
SR1
SR2
SX1
SX2
S Interface
AMODE
C768
DD FSC DCL BCL VSS
VSSA
VDD
VDDA
+3.3V 0V
IOM-2 Interface
Host
Interface
3186_17
TP
0V
ACL
LED Output Address
Mode
Setting
External
Awake
EAW
SDS
PSB 3186
Product Overview 7 09.99
1.3 Typ ical App lications
The I SA C-SX T E is designed for the user area of the IS DN bas ic ac cess , especially for
subs criber term inal equipment with S interface.
Figure Chapter 2 illustrates the general application fields of the IS A C-SX TE .
Figure 2 Applications of the ISAC-S X TE
ITS05407
LT-S
LT-S LT-T
SN
CP
Line
Card
TE(8)
TE(1)
TE(1) S
CP
SN
=
=Switching
Network
Central
Processor
PBX (NT2)
NT1
TU
=
TE(1)
TE(8)
U
S
NT1
Direct Subscriber Access
(point-to-point, short and extended
passive Bus)
-S TEISAC R
SX T E
PSB 3186
Product Overview 8 09.99
2 Pin Configuration
Figure 3 Pin Configur a tion of the ISA C - SX TE
P-MQFP-64
P-TQFP-64
SR2
I S AC- S X TE
PSB 31 86
12345678910111213141516
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
31
32
28
29
30
25
26
27
22
23
24
19
20
21
17
18
50
49
53
52
51
56
55
54
59
58
57
62
61
60
64
63
SR1
VDDA
VSSA
SX2
SX1
n.c.
ALE
WR / R/ W
RD / DS
XTAL2
XTAL1
VSS
VDD
A1
AMODE
VSS
INT
n.c.
CS
TP
RES
RSTO
VSS
BCL
DU
DD
FSC
DCL
VSS
VSS
VDD
res_l
EAW
ACL
res_c
res_c
res_c
res_c
res_c
3186_22
VDD
AD0
AD1
AD2
AD3
AD4
S CL / AD5
SDR / AD6
S DX / AD7
A0
VDD
VSS
A5
A4
A3
A2
res.
C768
A7
A6
res_c
res_c
res_c
SDS
PSB 3186
Product Overview 9 09.99
Table 1 IS AC-SX TE Pin Definitions and Funct ions
Pin No.
MQFP-64
TQFP-64
Sy mb ol In p ut (I )
Out put (O)
Open Drain
(OD)
Function
Host In terface
19
20
21
22
23
24
25
26
A0
A1
A2
A3
A4
A5
A6
A7
I
I
I
I
I
I
I
I
• Non-M ul tip lexed Bus M od e:
Address Bus
Addr es s bus trans fers addr ess es from the
mic r oc ontroller to the IS AC- S X TE . For indirect
addr ess mode only A 0 is valid (A 1-A7 to be
c onnected to VDD).
• Mul t ip lexed Bus Mod e:
Not us ed in multiplexed bus m ode. In this cas e A0-
A7 should dir ec tly be c onnec ted to VDD.
9
10
11
12
13
AD0
AD1
AD2
AD3
AD4
I/O
I/O
I/O
I/O
I/O
• Mul t ip lexed Bus Mod e:
Address/data bu s
Transfers addresses from the mi crocontroll er to the
IS AC-S X TE and data between the micr oc ontroller
and the IS AC-S X TE .
• Non-M ul tip lexed Bus M od e:
D a ta bus .
Tr ansf er s dat a between t he mic roc ontroller and the
I SAC -SX TE.
14 AD5
SCL
I/O
I
• Mul t ip lexed Bus Mod e:
Address/data bu s
A ddress /data line A D5 if the parallel interface is
selected.
• Non-M ul tip lexed Bus M od e:
D a ta bus
Data line D5 if the parallel interface is s elec ted.
SC I - Se r ia l C loc k
Clock s ignal of t he SCI inter fac e if a ser ial interface
is selected.
PSB 3186
Product Overview 10 09.99
15 AD6
SDR
I/O
I
• M ul tip lexed Bus M ode:
Address/dat a bus
Addr ess/data line AD6 if the parallel int erface is
selected.
• Non- M ul ti pl exed Bus M ode:
Data bus
Data line D6 if the parallel interface is selected.
S CI - Seri al Data Receive
Rec eive data line of the S CI inter face if a s er ial
inter face is s elec ted.
16 AD7
SDX
I/O
OD
• M ul tip lexed Bus M ode:
Address/dat a bus
Addr ess/data line AD7 if the parallel int erface is
selected.
• Non- M ul ti pl exed Bus M ode:
Data bus
Data line D7 if the parallel interface is selected.
S CI - Seri al Data Transmit
Transm it data line of the SCI interface if a ser ial
inter face is s elec ted.
39 RD
DS
I
I
Read
Indic ates a r ead acc ess to the register s ( Siemens /
Intel bus mode).
Data Strobe
The r ising edge mar k s the end of a valid read or
wr ite oper ation ( Mot or ola bus mode) .
40 WR
R/W
I
I
Write
Indicates a wr ite acc es s to the r egisters ( S iemens/
Intel bus mode).
Read/Write
A HIGH identifies a valid host acc ess as a read
oper ation and a LOW identifies a v alid host acc es s
as a write operation (M otorola bus m ode) .
Ta ble 1 ISAC -S X TE Pin De finit ions a nd Functions (Continued)
Pin No.
MQFP-64
TQFP-64
Sym bol Input (I)
Outpu t (O)
Open Drain
(OD)
Function
PSB 3186
Product Overview 11 09.99
41 ALE I Address Latch Enable
A HI GH on this line indic ates an address on the
ex ternal address/ data bus (multiplex ed bus ty pe
only).
A LE als o s elec ts the micr ocontr oller interface bus
type (multiplex ed or non m ult iplexed).
3CS IChip Select
A low lev el indic ates a mic r oc ontr oller ac c ess to the
I SAC -SX TE.
1INT OD (O) Interrup t Request
INT becom es activ e low ( open drain) if the ISA C-
SX TE r equest s an inter r upt.
The polar ity can be reprogram med to high active
with push-pull char act er is tic.
5RES IReset
A LO W on this input forc es the ISA C-S X T E into a
re set st ate.
38 AMODE I Address Mode
Selec ts between direc t (0) and indirect (1) r egis ter
acc es s mode.
I O M-2 In terfa ce
52 FSC O Frame Sync
8-k Hz frame sy nc hr onizat ion signal.
53 DCL O Data Clo ck
IOM-2 interface data clock signal 1. 536 M Hz
( double bit clock) .
49 BCL O Bit Clock
IOM-2 interface bit c loc k signal 768 k Hz
( single bit clock) .
51 DD O (OD) Data Downstream
IOM-2 data signal in downstr eam direc tion.
Table 1 IS AC-SX TE Pin Definitions and Funct ions (Continued)
Pin No.
MQFP-64
TQFP-64
Sy mb ol In p ut (I )
Out put (O)
Open Drain
(OD)
Function
PSB 3186
Product Overview 12 09.99
50 DU I Data Up stream
IOM -2 data signal in upstream direct ion.
29 SDS I Seri a l Data Stro be
P rogr am mable strobe s ignal f or time slot and/or D-
channel indic ation on IO M -2.
Miscellaneous
43
44 SX1
SX2 O
OS- Bus Transmitter Output (positive)
S- Bus Transmitter Output (negative)
47
48 SR1
SR2 I
IS- Bus Receiver In put
S- Bus Receiver In put
35
36
XTAL1
XTAL2
I
O
Crystal 1
Connec tion for a c r ys tal or used as ex ternal clock
input. 7.68 M Hz clock or crys tal r equired.
Crystal 2
Connec tion for a c r ys tal. Not connected if an
ex ter nal clock is supplied to XTAL1.
58 EAW IE xternal Awake
If a falling edge on this input is detected, the IS A C-
SX TE generates an interr upt and, if enabled, a
reset pulse.
59 ACL OAc tiv a tion LED
This pin c an either func tion as a pr ogrammable
output or it can automatically indic ate the activated
st ate of the S interface by a logic ’0’.
An LED with pre-res is tanc e may direc tly be
connec ted to ACL .
27 C768 O Clock Output
A 7.68 MHz c loc k is output to suppor t other devices .
This clock is not s ync hr onous to the S int er face.
6RSTO OD Reset O utput
Low active r es et output , either fr om a watchdog
timeout or pr ogr ammed by the host.
Ta ble 1 ISAC -S X TE Pin De finit ions a nd Functions (Continued)
Pin No.
MQFP-64
TQFP-64
Sym bol Input (I)
Outpu t (O)
Open Drain
(OD)
Function
PSB 3186
Product Overview 13 09.99
4TP I Test Pi n
M ust be c onnected to VSS.
2, 42 n.c. I not conn ect ed
28, 29 res. reserved
These pins are reserv ed and should be left not
connected.
57 res_l I reserved, conn ect L OW
This pin is res erved and must be c onnected to VSS.
30, 31,
32, 60,
61, 62,
63, 64
res_c I reserved, connect HIGH or LOW
These pins are reserv ed and must be connec ted
either to V SS
or VDD.
Power Supply
8, 18,
33, 56 VDD –D igit a l Powe r Supply V oltage
(3.3 V ±5%)
46 VDDA –A n alo g Power Supply Volta ge
(3.3 V ±5%)
7, 17,
34, 37,
54, 55
VSS –D igit a l gr ound
(0 V)
45 VSSA –Ana log gr ound
(0 V)
Ta ble 1 ISAC -S X TE Pin De finit ions a nd Functions (Continued)
Pin No.
MQFP-64
TQFP-64
Sym bol Input (I)
Outpu t (O)
Open Drain
(OD)
Function
PSB 3186
Product Overview 14 09.99
3 Funct ional Block Di agr am
Figure Figure 4 shows the architecture of the ISAC-SX TE containing the following
functions:
•S/T-interface transc eiver supporting TE m ode
•Different host inter face modes :
- Par allel microc ontroller interfac e
(S iem ens/Int el mult iplex ed, Siemens/Int el non multiplexed, M otor ola modes )
- Ser ial Control Int erf ac e ( S CI)
•Optional indirec t register addr ess mode reduc es number of registers to be acc essed
to tw o locations
•One D-channel HDLC-controller with 64 byte FlFOs per dir ec tion with progr amm able
FIFO block size (threshold) of 4, 8, 16 or 32 by te ( r ec eiv e) and 16 or 32 byte (transm it).
•IOM- 2 inter face for terminal mode ( TE)
•One s erial data strobe s ignals (S DS)
•IOM handler with controller data acces s register s ( CDA ) allows flex ible ac c ess to IOM
times lots for reading/wr iting, looping and shifting data
•S ync hr onous trans fer interr upts ( STI) allow c ontrolled acc ess to IOM timeslots
•M ONITO R channel handler on I OM-2 f or master m ode, slav e mode or data exc hange
•C/I-c hannel handler and TIC bus ac cess controller
•D-c hannel acces s m echanism
•LE D connec ted t o pin A CL indicates S- inter fac e act iv ation status autom atically or c an
be contr olled by the host
•Level detect circuit on the S interface reduces power consumption in power down
mode
•Two t imers f or periodic or s ingle interrupts (periods between 1 m s and 14.336 s)
•Cloc k and timing generation
•Digital P LL t o s ynchronize the tr ansceiver to the S/T interface
•Buffered 7.68 MHz oscillator clock output allows connection of further devices and
sav es another crys tal on the sys tem board
•Res et generat ion (wat c hdog timer )
PSB 3186
Product Overview 15 09.99
Figure 4 Functional Bloc k D ia gram of the ISA C -S X TE
Reset
Interrupt
-generation
SCI8-bit paral lel
IOM-2 Interface
IOM-2 Handler
D-channel
HDLC
RX/TX
FIFOs
S Tr an sce iver
C/ITIC
MON
Handler
Ho st Interface OSC
DPLL
Host
P erip heral Device s
3186_18
PSB 3186
Product Overview 16 09.99
4 Com parison between I SAC - S TE and I SAC- SX TE
The f ollowing table pr ovides an overv iew on the differ ences between the previous
IS A C-S TE P SB 2186 and t he new ISAC-S X TE PS B 3186.
Ta ble 2 C om pa r ison of t he ISAC -S X TE wit h the pre v ious ve r s ion ISA C -S TE:
ISAC- S X TE P S B 3186 ISAC- S TE P S B 2186
Operating modes TE TE
Supply voltage 3.3V ± 5 % 5V ± 5 %
Technology CMOS CMOS
P ack age P - MQFP-64 / P- TQFP -64 P -M QFP- 64 / P- LCC-44 /
P-DIP-40
Transceiver
Tran sfo rm e r ra tio for the
transmitter
receive r 1:1
1:1 2:1
2:1
Tes t Functions - Dig. loop via Layer 2 (TLP)
- Layer 1 dis able ( DIS _TR)
- Analog loop (LP_A - bit
EXLP- bit, ARL)
- Dig. loop via Layer 2( TLP)
- Layer 1 disable ( DIS _TR)
- Analog loop (ARL)
M icr oc ontroller I nterface S er ial inter face ( SCI )
8-bit parallel interface:
Motorola Mux
S iem ens/Intel Mux
S iem ens/Intel Non-M ux
direc t/ indirec t Addr es sing
Not pr ovided
8-bit parallel interface:
Motorola Mux
Siem ens/Intel Mux
Siem ens/Intel Non-Mux
Com mand str ucture of the
r egis ter acces s (SCI) Header/address/data Address/data
Cry stal 7.68 MHz 7.68 MH z
B uffered 7.68 MHz output P r ov ided Not pr ovided
Contr oller data ac cess to
IOM- 2 ti me slots A ll times lots;
v ar ious poss ibilities of data
access
Restricted access to
B - and IC-channel
PSB 3186
Product Overview 17 09.99
Data c ontr ol and
manipulation Var ious pos sibilities of data
contr ol and dat a
m anipulation (enable/
disable, shifting, looping,
switching)
B- and IC-c hannel looping
IOM-2
IOM- 2 Interfac e Double c loc k (DCL),
bit c loc k pin (BCL) ,
s er ial data s tr obe ( S DS)
Double clock (DCL),
bit clo ck (B C L),
serial data strobe (S DS)
M onitor channel
programming Provided
(M ON 0 , 1 , 2 , ..., 7 ) Provided
( MON0 or 1)
C/I channels CI0 (4bit),
CI1 (4/6bit) CI0 ( 4bit) ,
CI1 ( 6bit)
Lay er 1 state mac hine With changes for
c or r espondenc e with the
actual ITU s pecification
Lay er 1 state mac hine
in softwar e Not possible Not poss ible
HDLC suppor t D- and B - channel tim eslots ;
non-auto mode,
trans parent mode 1-3,
ex tended trans parent mode
D-c hannel tim eslot;
auto mode,
non- auto mode,
trans par ent mode 1-3
D-c hannel FIF O size 64 bytes cyc lic buffer per
dir ection with
pr ogr am mable FI FO
thresholds
2x32 bytes buffer per
direction
Res et Signals RE S input signal
RSTO output s ignal RST input/output signal
ISAC- S X TE P S B 3186 ISAC- S TE P S B 2186
PSB 3186
Product Overview 18 09.99
Reset Sources RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
RST Input
Watchdog
C/I Code Change
EAW Pi n
Inter r upt Output S ignals INT
low active ( open drain) by
default , repr ogr ammable to
high activ e (pus h-pull)
Low active INT
ISAC- S X TE P S B 3186 ISAC- S TE P S B 2186
