intel. ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY m x8/x16 Input/Output Architecture 28F200BX-T, 28F200BX-B For High Performance and High Integration 16-bit and 32-bit CPUs m x8-only Input/Output Architecture 28F002BX-T 28F002BX-B For Space Constrained 8-bit Applications a Optimized High Density Blocked Architecture One 16-KB Protected Boot Block Two &8-KB Parameter Blocks ~ One 96-KB Main Block One 128 KB Main Block Top or Bottom Boot Locations @ Extended Cycling Capability 100,000 Block Erase Cycles m Automated Word/Byte Write and Block Erase Command User Interface Status Registers Erase Suspend Capability m SRAM-Compatible Write Interface @ Automatic Power Savings Feature 1 mA Typical Icc Active Current in Static Operation m Hardware Data Protection Feature Erase/Write Lockout during Power Transitions m Very High-Performance Read 60/80 ns Maximum Access Time - 30/40 ns Maximum Output Enable Time Low Power Consumption 20 mA Typical x8 Active Read Current ~ 25 mA Typical x16 Active Read Current Reset/Deep Power-Down input 0.2 A Icc Typical Acts as Reset for Boot Operations Extended Temperature Operation 40C to + 85C Write Protection for Boot Block Industry Standard Surface Mount Packaging 28F200BX: JEDEC ROM Compatible 44-Lead PSOP 56-Lead TSOP 28F002BX: 40-Lead TSOP 12V Word/Byte Write and Block Erase Vpp = 12V +5% Standard Vpp = 12V + 10% Option ETOX Ill Flash Technology 5V Read Independent Software Vendor Support 4-92 October 1993 Order Number: 290448-003a | ntel e 28F200BX-T/B, 28F002BX-T/B Intels 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec- tive erasure, automated write and erase operations and standard microprocessor interface. The 2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/out- put control, very high speed, low power, an industry standard ROM compatible pinout and surface mount packaging. The 2-Mbit flash family allows for an easy upgrade to Intels 4-Mbit Boot Block Flash Memory Family. The Intel 28F200BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-T and 28F200BX-B are 2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry standard ROM/EPROM pinout. The Intel 28FO02BX-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable systems. These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified word/byte write and block erasure. The 28F200BX-T/28F002BX-T provide block locations compatible with intels MCS-186 family, 80286, i386, i4867, i8GOTM and BSO960CA microprocessors. The 28F200BX-B/ 28F002BX-B provide compatibility with Intels BO960KX and 80960SX families as well as other embedded microprocessors. The boot block includes a data protection feature to protect the boot code in critical applications. With a maximum access time of 60 ns, these 2-Mbit flash devices are very high performance memories which interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total Voc power consumption to 1 .W typical. This is critical in handheld battery powered systems. For very low power applications using a 3.3V supply, refer to the Intel 28F200BX-TL/BL, 28F002Bx- TL/BL 2-Mbit Boot Block Flash Memory Family datasheet. Manufactured on Intels 0.8 micron ETOXIII process, the 2-Mbit flash memory family provides world class quality, reliability and cost-effectiveness at the 2-Mbit density level. ADVANCE INFORMATION 4-9328F200BX-T/B, 28F002BX-T/B 1.0 PRODUCT FAMILY OVERVIEW Throughout this datasheet the 28F200BX refers to both the 28F200BX-T and 28F200BX-B devices and 28F002BX refers to both the 28FO002BX-T and 28F002BX-B devices. The 2-Mbit flash memory fam- ily refers to both the 28F200BX and 28F002BxX prod- ucts. This datasheet comprises the specifications for four separate products in the 2-Mbit flash memory family. Section 1 provides an overview of the 2-Mbit flash memory family including applications, pinouts and pin descriptions. Sections 2 and 3 describe in detail the specific memory organizations for the 28F200BX and 28F002BX products respectively. Section 4 combines a description of the familys principles of operations. Finally Section 5 describes the familys operating specifications. PRODUCT FAMILY x8/x16 Products x8-Only Products 28F200BX-T 28F002BX-T 28F200BX-B 28F002BXx-B 1.1 Main Features The 28F200BX/28F002BxX boot block flash memory family is a very high performance 2-Mbit (2,097,152 bit) memory family organized as either 128 KWords (131,072 words) of 16 bits each or 256 Kbytes (262,144 bytes) of 8 bits each. Five Separately Erasable Blocks including a hard- ware-lockable boot block (16,384 Bytes), two pa- rameter blocks (8,192 Bytes each) and two main blocks (1 block of 98,304 Bytes and 1 block of 131,072 Bytes) are included on the 2-Mbit family. An erase operation erases one of the main blocks in typically 2.4 seconds, and the boot or parameter blocks in typically 1.0 second. Each block can be independently erased and programmed 100,000 times. The Boot Block is located at either the top (28F200BX-T, 28F002BX-T) or the bottom (28F200BX-B, 28F002BX-B) of the address map in order to accommodate different microprocessor pro- tocols for boot code location. The hardware locka- ble boot block provides the most secure code stor- age. The boot block is intended to store the kernel code required for booting-up a system. When the RP # pin is between 11.4V and 12.6V the boot block is unlocked and program and erase operations can be performed. When the RP # pin is at or below 6.5V the boot block is locked and program and erase op- erations to the boot block are ignored. 4-94 a intel. The 28F200BX products are available in the ROM/ EPROM compatible pinout and housed in the 44- Lead PSOP (Plastic Small Outline) package and the 56-Lead TSOP (Thin Small Outline, 1.2mm thick) package as shown in Figures 3 and 4. The 28F002BX products are available in the 40-Lead TSOP (1.2mm thick) package as shown in Figure 5. The Command User Interface (CUI) serves as the interface between the microprocessor or microcon- troller and the internal operation of the 28F200BX and 28F002BxX flash memory products. Program and Erase Automation allows program and erase operations to be executed using a two- write command sequence to the CUI. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, there- by unburdening the microprocessor or microcontrol- ler. Writing of memory data is performed in word or byte increments for the 28F200BX family and in byte increments for the 28FO002BX family typically within 9 pws which is a 100% improvement over current flash memory products. The Status Register (SR) indicates the status of the WSM and whether the WSM successfully completed the desired program or erase operation. Maximum Access Time of 60 ns (TACC) is achieved over the commercial temperature range (0C to 70C), 5% Voc supply voltage range (4.75V to 5.25V) and 30 pF output load. Refer to Figure 19; Tacc vs Output Load Capacitance for larger output loads. Maximum Access Time of 80 ns (TACC) is achieved over the commercial temperature range, 10% Voc supply range (4.5V to 5.5V) and 100 pF output load. Ipp maximum Program current is 40 mA for x16 operation and 30 mA for x8 operation. !pp Erase current is 30 mA maximum. Vpp erase and pro- gramming voltage is 11.4V to 12.6V (Vpp = 12V +5%) under all operating conditions. As an op- tion, Vpp can also vary between 10.8V to 13.2V (Vpp = 12V +10%) with a guaranteed number of 100 block erase cycles. Typical Icc Active Current of 25 mA is achieved for the x16 products (28F200BX), typical Icc Active Current of 20 mA is achieved for the x8 products (28F200BX, 28F002BX). Refer to the Icc active cur- rent derating curves in this datasheet. The 2-Mbit boot block flash family is also designed with an Automatic Power Savings (APS) feature to minimize system battery current drain and allow for very low power designs. Once the device is ac- ADVANCE INFORMATIONa intel. cessed to read array data, APS mode will immedi- ately put the memory in static mode of operation where Icc active current is typically 1 mA until the next read is initiated. When the CE# and RP# pins are at Vcc and the BYTE# pin (28F200BxX-only) is at either Voc or GND the CMOS Standby mode is enabled where Icc is typically 50 pA. A Deep Power-Down Mode is enabled when the RP# pin is at ground minimizing power consumption and providing write protection during power-up con- ditions. I current during deep power-down mode is 0.20 4A typical. An initial maximum access time or Reset Time of 300 ns is required from RP# switching until outputs are valid. Equivalently, the device has a maximum wake-up time of 215 ns until writes to the Command User Interface are recog- nized. When RP # is at ground the WSM is reset, the Status Register is cleared and the entire device is protected from being written to. This feature pre- vents data corruption and protects the code stored in the device during system reset. The system Reset pin can be tied to RP# to reset the memory to nor- mal read mode upon activation of the Reset pin. With on-chip program/erase automation in the 2-Mbit family and the RP # functionality for data pro- tection, when the CPU is reset and even if a program or erase command is issued, the device will not rec- ognize any operation until RP # returns to its normal state. For the 28F200BX, Byte-wide or Word-wide In- put/Output Control is possible by controlling the BYTE# pin. When the BYTE # pin is at a logic low the device is in the byte-wide mode (x8) and data is read and written through DOQ[0:7]. During the byte- wide mode, 0Q[8:14] are tri-stated and DQ15/A1 becomes the lowest order address pin. When the BYTE# pin is at a logic high the device is in the word-wide mode (x16) and data is read and written through DQ[0:15]. 1.2 Applications The 2-Mbit boot block flash family combines high density, high performance, cost-effective flash mem- ories with blocking and hardware protection capabili- ties. Its flexibility and versatility will reduce costs throughout the product life cycle. Flash memory is ideal for Just-In-Time production flow, reducing sys- tem inventory and costs, and eliminating component handling during the production phase. During the product life cycle, when code updates or feature en- | ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B hancements become necessary, flash memory will reduce the update costs by allowing either a user- performed code change via floppy disk or a remote code change via a serial link. The 2-Mbit boot block flash family provides full function, blocked flash memories suitable for a wide range of applications. These applications include Extended PC BIOS, Digital Cellular Phone program and data storage, Telecommunication boot/firmware, and various other embedded applications where both program and data storage are required. Reprogrammabie systems such as personal com- puters, are ideal applications for the 2-Mbit flash products. Portable and handheld personal computer applications are becoming more complex with the addition of power management software to take ad- vantage of the latest microprocessor technology, the availability of ROM-based application software, pen tabiet code for electronic hand writing, and diag- nostic code. Figure 1 shows an example of a 28F200BX-T application. This increase in software sophistication augments the probability that a code update will be required after the PC is shipped. The 2-Mbit flash products provide an inexpensive update solution for the note- book and handheld personal computers while ex- tending their product lifetime. Furthermore, the 2-Mbit flash products power-down mode provides added flexibility for these battery-operated portable designs which require operation at very low power levels. The 2-Mbit flash products also provide excellent de- sign solutions for Digital Cellular Phone and Tele- communication switching applications requiring high performance, high density storage capability cou- pled with modular software designs, and a small form factor package (x8-only bus). The 2-Mbits blocking scheme allows for an easy segmentation of the embedded code with: 16 Kbytes of Hardware- Protected Boot code, 2 Main Blocks of program code and 2 Parameter Blocks of 8 Kbytes each for frequently updatable data storage and diagnostic messages (e.g. phone numbers, authorization codes). Figure 2 is an example of such an applica- tion with the 28F002BxX-T. These are a few actual examples of the wide range of applications for the 2-Mbit Boot Block flash mem- ory family which enable system designers to achieve the best possible product design. Only your imagina- tion limits the applicability of such a versatile product family. 4-95a 28F200BX-T/B, 28F002BX-T/B i ntel 4 1 Contralier Pp RESET# pst XDEN# GPIO ReseT PWRGOOD XDIR DQ- 15 Vpp sp[o:14] X-BUS XCEIVER * 28F200BX-T| 5V sossest |_ROMCSO MEMRD# OE# BYTE MEMWR# EMWR wee 5V GPIO ROM 16/8# Figure 1. 28F200BX Interface to INTEL386SL Microprocessor Superset ADDRESS LATCHES LE Ate.17 Ag Ais ALE ADg ~ADz ADDRESS LATCHES LE DQy-DQ, Ag-Ar7 80C188EB usc# CE# 28F002Bx-T Vpp Vpp GENERATOR PIX WR# RD# RESIN# SYSTEM RESET 290448-24 4-96 Figure 2. 28F002BX Interface to INTEL 80C 188EB 8-Bit Embedded Microprocessor ADVANCE INFORMATION |. ; i ntel 28F200BX-T/B, 28F002BX-T/B i The 28F002BX 40-Lead TSOP pinout shown in Fig- 1.3 Pinouts ure 5 is 100% compatible and provides a density The 28F200BX 44-Lead PSOP pinout follows the in- upgrade to the 28F004BX 4-Mbit Boot Block flash dustry standard ROM/EPROM pinout as shown in memory. Figure 3 with an upgrade to the 28F400BX (4-Mbit flash family). Furthermore, the 28F200BX 56-Lead TSOP pinout shown in Figure 4 provides density up- grades to the 28F400BX and to future higher density boot block memories. 28F400BX 28F400BX Vpp Vpp Ft O 440 rps RP# DU pu C42 435 we* WE# Ai7 nc Os 4200 Ag Ag Az a, 44 41 [J Ay Ag Ag 45 5 40B) Ag A1o As A, C6 39D Ay Ai Ag 4,7 38E IA? A12 A3 a; 8 EAS Ai3 Ag oq? PA28F200BX = *P* Ava Ay A, E10 35D As Ais Ao Ag C11 44 LEAD PSOP MBDA, Ais CE# Ce# Cy12 0.525 x 1.110 330) BYTE# BYTE# GND GND [913 320 GND GND OE# OE* C414 TOP VIEW 310) pa,5 /A, DQ 45/A_ DQo DQ 15 30 F) ba, DQ; DQ, da, 416 2917 Da, DQ14 DQ, ba, 417 : 28 [1 09, DQ. DQg DQ C418 277) 0a, DQ43 DQ2 og, Cyig 26 00, DQs DQi0 DQ 9 C4 20 25 FI Da, , DQ12 DQ3 pa, Cy21 2411 va, DQ, DQ41 ba, , 22 23D) Voc Voc 290448-25 Figure 3. PSOP Lead Configuration for x8/x16 28F200BX | ADVANCE INFORMATION 4-9728F200BX-T/B, 28F002BX-T/B intel. 28F400BX 28F400BX NC nc 1 O 56 1c NC NC nc C=] 2 55 Ae Ai Ais Ars C3 54 [ pyTe# BYTE# Aa A. C4 53 [ cond GND Aig Ascos5 52 EF D5 /A- DQ15/A_1 Ai2 Av C6 51 - 00, DQ7 Ai A, 7 50 00, DQ14 Ato Aio D8 49 [9 DQ5 Ag 4g 19 48 [ 0,, DQ13 Ag 4g C10 vc Dee DQs NG nc O11 46 F) DQ) DQy2 NG NC Ed 12 28F200BX 45 FE 2% DQ, WE# We# [13 44 ES cc Voc RP# r+cu S6-LEAD TSOP ,; FE hee Voc NC NC C15 42 Eo 00, DQ11 NC NC CJ 16 14mm x 20mm 41 - 20, DQ3 Vpp Vpp D117 TOP VIEW 40 L 2A, DQ19 DU DU J 18 39 FJ 00, DQ2 NC NC 119 38 ( DQ DQg Aq7 nc J] 20 37 Fo 0, DQ, A7 Aro 21 36 00, DQg Ag Ag C1 22 35 HO DQo As As Cj 23 34 ( oc# OE# Ag Ag Co 24 33 [ cno GND Ag Ay 25 32 ce# CE# A2 An Co] 26 31 =" Ap Ao Ay 4 oo 27 30 = nc NC NC NC [] 28 29 [7 nc NC 290448-3 Figure 4. TSOP Lead Configuration for x8/x16 28F200BX 28F004BX 28F004BX A16 Ago O 40 A Air Ais Aso 2 39 =") cno GND Aa Azo 3 38 [I NC NC Aig A304 37 EDN NC Ai2 ADs 36 Eo Ao Ato Ai A,,o6 35 [ DQ, DQ; Ag 4407 uo bee DQ. Ag Agcis 33 20, DOs WE # we# C9 28F002BX 32 =, DQ, RP# RP# [J 10 40-LEAD TSOP 31 FJ Nec Voc Vpp Vpp C1 11 30 FE Yee Voc DU pU =4 12 10mm x 20mm 29 nc NC Ag NC Co 13 28 a O83 DQ3 Az Aco TOP VIEW 27 [= 0Q, DQ2 As Ag O15 26 F 20, DQ; As As 1 16 25 [FJ 0% DQo Ag A, 0417 24 -1 oF# OE# A3 4,018 23 [= Gnd GND Ao Ag J 19 22 == ce# CE# Ay A, J 20 21 40 Ao , 290448-20 Figure 5. TSOP Lead Configuration for x8 28F002BX 4-98 ADVANCE INFORMATIONintel. 28F200BX-T/8, 28F002BX-T/B 1.4 Pin Descriptions for the x8/x16 28F200BX Symbol Type Name and Function Ao-Ai6 ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. Ag ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this mode Ag decodes between the manufacturer and device IDs. When BYTE # is at a logic low only the lower byte of the signatures are read. DQ;5/A_ is a don't care in the signature mode when BYTE # is low. DQ o-DQ7 1/0 DATA iNPUTS/OUTPUTS: Inputs array data on the second CE # and WE# cycle during a program command. Inputs commands to the Command User Interface when CE # and WE # are active. Data is internally latched during the write and Program cycles. Outputs array, intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled. DQ,s-DQi5 1/0 DATA INPUTS/OUTPUTS: Inputs array data on the second CE # and WE # cycle during a program command. Data is internally latched during the write and program cycles. Outputs array data. The data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (BYTE # = 0). In the byte-wide mode DQ,5/A_ 4 becomes the lowest order address for data output on DQ9-DQz. CE# CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE # is active low; CE # high deselects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE # and RP # input stages. RP# RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in deep power-down mode. Locks the boot block from program/erase. When PP # is at logic high level and equals 6.5V maximum the boot block is locked and cannot be programmed or erased. When RP# = 11.4V minimum the boot block is unlocked and can be programmed or erased. When RP # is at a logic low level the boot block is locked, the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP # transitions from logic low to logic high the flash memory enters the read array mode. OE# OUTPUT ENABLE: Gates the devices outputs through the data buffers during a read cycle. OE # is active low. WE# WRITE ENABLE: Controls writes to the Command Register and array blocks. WE # is active low. Addresses and data are latched on the rising edge of the WE# pulse. BYTE# BYTE # ENABLE: Controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE # pin must be controlled at CMOS levels to meet 100 pA CMOS current in the standby mode. BYTE# = 0 enables the byte-wide mode, where data is read and programmed on DQg-DQz7 and DQ 5/A_ becomes the lowest order address that decodes between the upper and lower byte. DOg-DQj, are tri-stated during the byte-wide mode. BYTE# = 1 enables the word-wide mode where data is read and programmed on DQ9-DQ 45. Vpp PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block. Note: Vpp < Vpp_max Memory contents cannot be altered. Voc DEVICE POWER SUPPLY (5V + 10%, 5V + 5%) GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating. DU DONT USE PIN: Pin should not be connected to anything. | ADVANCE INFORMATION 4-99a 28F200BX-T/B, 28F002BX-T/B | ntel 1.5 Pin Descriptions for x8 28FO02BX Symbol Type Name and Function Ao-A17 ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. Ag ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this mode Ap decodes between the manufacturer and device IDs. DQo-DQz7 1/0 DATA INPUTS/OUTPUTS: Inputs array data on the second CE # and WE# cycle during a program command. Inputs commands to the command user interface when CE # and WE # are active. Data is internally latched during the write and program cycles. Outputs array, Intelligent Identifier and status register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled. CE# CHIP ENABLE: Activates the devices control logic, input buffers, decoders and sense amplifiers. CE # is active low; CE # high deselects the memory device and reduces power consumption to standby levels. If CE # and RP # are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP # input stages. #RP# RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in deep powerdown mode. Locks the Boot Block from program/erase. When FP # is at logic high level and equals 6.5V maximum the Boot Block is locked and cannot be programmed or erased. When RP# = 11.4V minimum the Boot Block is unlocked and can be programmed or erased. When RFP # is at a logic low level the Boot Block is locked, the deep powerdown mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP # transitions from logic low to logic high, the flash memory enters the read-array mode. OE# OUTPUT ENABLE: Gates the devices outputs through the data buffers during a read cycie. OE # is active low. WE # WRITE ENABLE: Controls writes to the Command Register and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE # pulse. PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each biock. Note: Vpp < Vpp_max memory contents cannot be altered. Voc DEVICE POWER SUPPLY (5V + 10%, 5V + 5%) GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating. DU DONT USE PIN: Pin should not be connected to anything. 4-100 ADVANCE INFORMATION |28F200BX-T/B, 28F002BX-T/B 2.0 28F200BX WORD/BYTE-WIDE PRODUCTS DESCRIPTION Ko L-8r06z Dott 7 ans ssa4gay a wv 5 ts J ES Fe |zelFo/ Bal. aNd > z4 z1 Salt al ote] | ysqoos0-x HOLY) 2, p 25 2a BLS) FST s ss3yggy SA QA jeele say 7 Q R IR dd mp] HOLIMS 39170A 3NIHOWN asvua/WYuoOud FLVIS ILM 4a44ne ' ONISN3S /ONILVO-A 430g0930-4 inant a t 4 . 7ONLNOD YOLvavdNOo Nolona3y + ______>} viva YaMOd #30 OvsNaLNI | = uasn meer | a GNVMOD uaisiogy x #39 SNLVLS -) Eg So dae a2] a m> nS a uqisiogd - a #3148 91901 O/t | a a A wS11ANaOL 3 l my i} ft 1 ,| uaaana ,| uaaang aadina |_| uaaana 4344 INdNI "| LMdNI "| LndNI f >I ingino Andino S-y7 Slog vn ro | 7 = 4 | 1 | Sya- 0 '-7 S'pa- 8a Figure 6. 28F200BX Word/Byte-Wide Block Diagram | ADVANCE INFORMATION 4-10128F2008X-T/B, 28F002BX-T/B 2.1 28F200BX Memory Organization 2.1.1 BLOCKING The 28F200BX uses a blocked array architecture to provide independent erasure of memory blocks. A block is erased independently of other blocks in the array when an address is given within the block ad- dress range and the Erase Setup and Erase Confirm commands are written to the CUI. The 28F200BxX is a random read/write memory, only erasure is per- formed by block. 2.1.1.1 Boot Block Operation and Data Protection The 16-Kbyte boot block provides a lock feature for secure code storage. The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of pow- er failure or other disruption during code update. This lock feature ensures absolute data integrity by preventing the boot block from being written or erased when RP # is not at 12V. The boot block can be erased and written when RP# is held at 12V for the duration of the erase or program operation. This allows customers to change the boot code when necessary while providing security when needed. See the Block Memory Map section for address locations of the boot block for the 28F200BX-T and 28F200BX-B. 2.1.1.2 Parameter Block Operation The 28F200BX has 2 parameter blocks (8 Kbytes each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The pa- rameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware write protection feature that the boot block has. The parameter blocks pro- vide for more efficient memory utilization when deal- ing with parameter changes versus regularly blocked devices. See the Block Memory Map section for ad- dress locations of the parameter blocks for the 28F200BX-T and 28F200BX-B. 4-102 intel. Two main blocks of memory exist on the 28F200BX (1 x 128 Kbyte block and 1 x 96-Kbyte block). See the following section on Block Memory Map for the address location of these blocks for the 28F200BX-T and 28F200BX-B products. 2.1.1.3 Main Block Operation 2.1.2 BLOCK MEMORY MAP Two versions of the 28F200BX product exist to sup- port two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location. The 28F200BX-T memory map is inverted from the 28F200BX-B memory map. 2.1.2.1 28F200BX-B Memory Map The 28F200BX-B device has the 16-Kbyte boot block located from OO0000H to 01FFFH to accommo- date those microprocessors that boot from the bot- tom of the address map at OOO00H. In the 28F200BX-B the first 8-Kbyte parameter block re- sides in memory space from 02000H to O2FFFH. The second 8-Kbyte parameter block resides in memory space from 03000H to O3FFFH. The 96-Kbyte main block resides in memory space from 04000H to OFFFFH. The 128-Kbyte main block re- sides in memory space from 10000H to 1FFFFH (word locations). See Figure 7. (Word Addresses) 1FFFFH 128-Kbyte MAIN BLOCK 10000H OFFFFH 96-Kbyte MAIN BLOCK 04000H O3FFFH 8-Kbyte PARAMETER BLOCK 03000H 02FFFH 8-Kbyte PARAMETER BLOCK 02000H O1FFFH 16-Kbyte BOOT BLOCK 00000H Figure 7. 28F200BX-B Memory Map ADVANCE INFORMATION |intel. 2.1.2.2 28F200BX-T Memory Map The 28F200BX-T device has the 16-Kbyte boot block located from 1EQ00H to 1FFFFH to accommo- date those microprocessors that boot from the top of the address map. In the 28F200BX-T the first 8-Kbyte parameter block resides in memory space from 1D000H to 1DFFFH. The second 8-Kbyte pa- rameter block resides in memory space from 1CO000H to 1CFFFH. The 96-Kbyte main block re- sides in memory space from 10000H to 1BFFFH. The 128-Kbyte main block resides in memory space from 00000H to OFFFFH as shown in Figure 8. ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B (Word Addresses) 1FFFFH 1E000H 1DFFFH 1D000H 1CFFFH 1C000H 1BFFFH 10000H OFFFFH 00000H 16-Kbyte BOOT BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 96-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK Figure 8. 28F200BX-T Memory Map 4-10328F200BX-T/B, 28F002BX-T/B 3.0 28F002BX BYTE-WIDE PRODUCTS DESCRIPTION 61-8hb062 _t t 1 + t L ot 43LNN0O ssauaay au uv z | zs = > P= 8- Zz Be [ETlEs| Saye aNo > 1 ! Salon x e HOLT wx os aalaa| o 4300030-Xx 2 > 23 2a SS(s 2) ee] ssaagay aa fa jenlen| a R {Rk dy mpl HOLIMS 30170A ANIHOVIN * 3SVUI/NVHOOUd JIVIS 411MM aaaing ONISN3S/ONILVO~A Me] -4300930-A Andi 6 4 1 1 _t TOYLNOD YOLVEVANOD nolwonagy +d _________ viva 43mOd #30 30V4U2 INI yasn ue aNvINRod 4a1si93y = #39 2 SNAVAS - Eo a ee ac a wes y yo a> noe zB 4aisio34 m7 I 31007 0/ PEEK) * im! J 4adana indino 43d4nd iAdNi 4na- pa fly - Oy Figure 9. 28F002BX Byte-Wide Block Diagram ADVANCE INFORMATION | 4-104intal. 3.1 28F002BX Memory Organization 3.1.1 BLOCKING The 28F002BX uses a blocked array architecture to provide independent erasure of memory blocks. A block is erased independently of other blocks in the array when an address is given within the block ad- dress range and the Erase Setup and Erase Confirm commands are written to the CUI. The 28F002BX is a random read/write memory, only erasure is per- formed by block. 3.1.1.1 Boot Block Operation and Data Protection The 16-Kbyte boot block provides a lock feature for secure code storage. The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of pow- er failure or other disruption during code update. This lock feature ensures absolute data integrity by preventing the boot block from being programmed or erased when RP# is not at 12V. The boot biock can be erased and programmed when RP # is held at 12V for the duration of the erase or program oper- ation. This allows customers to change the boot code when necessary while still providing security when needed. See the Block Memory Map section for address locations of the boot block for the 28F002BX-T and 28F002BX-B. 3.1.1.2 Parameter Block Operation The 28F002BX has 2 parameter biocks (8 Kbytes each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The pa- rameter blocks can also be used to stgre additional boot or main code. The parameter blocks however, do not have the hardware write protection feature that the boot block has. Parameter blocks provide for more efficient memory utilization when dealing with small parameter changes versus regularly blocked devices. See the Block Memory Map sec- tion for address locations of the parameter blocks for the 28F002BX-T and 28F002BX-B. ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B 3.1.1.3 Main Block Operation Two main blocks of memory exist on the 28FO02BX (1 x 128-Kbyte block and 1 x 96-Kbyte block). See the following section on Block Memory Map for address location of these blocks for the 28F002BX-T and 28F002BX-B. 3.1.2 BLOCK MEMORY MAP Two versions of the 28FO02BX product exist to sup- port two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location. The 28F002BX-T memory map is inverted from the 28F002BX-B memory map. 3.1.2.1 28FO002BX-B Memory Map The 28F002BX-B device has the 16-Kbyte boot block located from O0000H to O3FFFH to accommo- date those microprocessors that boot from the bot- tom of the address map at OO000H. In the 28F002BX-B the first 8-Kbyte parameter block re- sides in memory from 04000H to OSFFFH. The sec- ond 8-Kbyte parameter block resides in memory space from 06000H to O07FFFH. The 96-Kbyte main block resides in memory space from O8000H to {FFFFH. The 128-Kbyte main block resides in mem- ory space from 20000H to 3FFFFH. See Figure 10. 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 96-Kbyte MAIN BLOCK 08000H O7FFFH 8-Kbyte PARAMETER BLOCK 06000H OSFFFH 8-Kbyte PARAMETER BLOCK 04000H O3FFFH 16-Kbyte BOOT BLOCK 00000H Figure 10. 28F002BX-B Memory Map 4-10528F200BX-T/B, 28F002BX-T/B 3.1.2.2 28F002BX-T Memory Map The 28F002BX-T device has the 16-Kbyte boot block located from 3CO00H to 3FFFFH to accom- modate those microprocessors that boot from the top of the address map. In the 28F002BX-T the first 8-Kbyte parmeter block resides in memory space from 3A000H to 3BFFFH. The second 8-Kbyte pa- rameter block resides in memory space from 38000H to 39FFFH. The 96-Kbyte main block re- sides in memory space from 20000H to 37FFFH. The 128-Kbyte main block resides in memory space from O0000H to 1FFFFH. SFFFFH 16-Kbyte BOOT BLOCK 3C000H 3BFFFH 8-Kbyte PARAMETER BLOCK 3A000H 30FFFH 8-Kbyte PARAMETER BLOCK 38000H 37FFFH 96-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 00C00H Figure 11. 28F002BX-T Memory Map 4.0 PRODUCT FAMILY PRINCIPLES OF OPERATION Flash memory augments EPROM functionality with in-circuit electrical write and erase. The 2-Mbit flash 4-106 a Intel. family utilizes a Command User interface (CUI) and internally generated and timed algorithms to simplify write and erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and program- ming, and maximum EPROM compatibility. In the absence of high voltage on the Vpp pin, the 2-Mbit boot block flash family will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and Intelli- gent Identifier mode. The device provides standard EPROM read, standby and output disable opera- tions. Manufacturer Identification and Device Identi- fication data can be accessed through the CUI or through the standard EPROM AQ high voltage ac- cess (Vip) for PROM programming equipment. The same EPROM read, standby and output disable functions are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp al- lows write and erase of the device. All functions as- sociated with altering memory contents: write and erase, Intelligent Identifier read and Read Status are accessed via the CUI. The purpose of the Write State Machine (WSM) is to completely automate the write and erasure of the device. The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register. The CUI will handle the WE # interface to the data and address latches, as well as system software requests for status while the WSN is in operation. 4.1 28F200BX Bus Operations Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. ADVANCE INFORMATION |a 1 ntel 28F200BX-T/B, 28F002BX-T/B Table 1. Bus Operations for WORD-WIDE Mode (BYTE # = Vix) Mode Notes | RP# | CE# | OE# | WE# | Ag | Ao | Vpp | DQo-15 Read 1,2,3 Vin Vit Vit ViK x xX xX Dout Output Disable Vin VIL Vin VIH Xx xX X High Z Standby Vin Vin xX x xX xX xX High Z Deep Power-Down 9 VIL X xX x Xx xX xX High Z Intelligent Identifier (Mfr) 4 Vin ViL VIL Vin Vio | Vir xX 0089H Intelligent Identifier (Device) 4,5 Vin VIL VIL Vin Vip | Vin xX 2274H 2275H Write 6,7,8 ViH VIL Vin ViL Xx x xX Din Table 2. Bus Operations for BYTE-WIDE Mode (BYTE# = Vj.) Mode Notes | RP# | CE# | OE# | WE# | Ag | Ap | A_1| Vpp | DQo-7 | DQg-14 Read 1,23] Vin} Vir VIL Vin Xx X x X | Dour High Z Output Disable Vin | Vir | Vin Vin xX xX x X | HighZ | HighZ Standby Vin | Vin xX X xX Xx x X | HighZ | HighZ Deep Power-Down 9 VIL X X X X |X |'X X | HighZ | HighZ Intelligent Identifier (Mfr) 4 ViH Vit VIL Vin | Vio| Vie} X X | 89H High Z Intelligent Identifier 4,5 Vin | Vit ViL Vin | Vin | Vin | X X | 74H High Z (Device) 75H Write 67,8) Vin | Vir | Vin Vit X X xX X | Din High Z NOTES: 1, Refer to DC Characteristics. 2. X can be Vi, or Viq for control pins and addresses, Vpp,_ or Vppy for Vpp. 3. See DC characteristics for Vpp_, VepH, VHH. Vip voltages. 4. Manufacturer and Device codes may also be accessed via a CUI write sequence. Ay-A17 = X. 5. Device ID = 2274H for 28F200BX-T and 2275H for 28F200BXx-B. 6. Refer to Table 4 for valid Diy during a write operation. 7, Command writes for Block Erase or Word/Byte Write are only executed when Vpp = Vppy. 8. To write or erase the boot block, hold RP# at Vip. 9. RP# must be at GND +0.2V to meet the 1.2 A maximum deep power-down current. ADVANCE INFORMATION 4-10728F200BX-T/B, 28F002BX-T/B 4.2 28F002BX Bus Operations Table 3. Bus Operations Mode Notes | RP# | CE# | OE# | WE# | Ag Ao | Vpp | DQo-7 Read 1,2,3 Vin Vit ViL Vind xX xX xX Dout Output Disable Vin Vit Vin Vin xX xX X High Z Standby Vin Vin x xX xX xX X High Z Deep Power-Down Vit xX x xX X xX xX High Z Intelligent Identifier (Mfr) Vin Vit Vit Vin Vio | Vit xX 89H Intelligent identifier (Device) 4,5 Vin ViL Vit Vin Vio | Vin xX 7CH 7DH Write 6,7,8 Vin ViL Vin VIL x x X Din NOTES: 1. Refer to DC Characteristics. 2. X can be Vi, or Vix for control pins and addresses, Vppy or Vppy for Vpp. 3. See DC characteristics for VppL, VppH, VHH, Vip voltages. 4. Manufacturer and Device codes may also be accessed via a CU! write sequence. Ay-Ayg = X. 5. Device ID = 7CH for 28F002BX-T and 7DH for 28FO002BX-B. 6. Refer to Table 4 for valid Diy during a write operation. 7. Command writes for Block Erase or byte program are only executed when Vpp = Vppy. 8. Program or erase the Boot block by holding RP # at Viy. 9. RP# must be at GND +0.2V to meet the 1.2 uA maximum deep power-down current. 4.3 Read Operations | The 2-Mbit boot block flash family has three user read modes; Array, Intelligent identifier, and Status Register. Status Register read mode will be dis- cussed in detail in the Write Operations section. During power-up conditions (Vcc supply ramping), it takes a maximum of 600 ns from when Vcc is at 4.5V minimum to valid data on the outputs. 4.3.1 READ ARRAY If the memory is not in the Read Array mode, it is necessary to write the appropriate read mode com- mand to the CUI. The 2-Mbit boot biock flash family has three control functions, all of which must be logi- cally active, to obtain data at the outputs. Chip-En- able CE# is the device selection control. Power- Down RP # is the device power control. Output-En- able OE # is the DATA INPUT/OUTPUT (DQ([0:15] or DQ(0:7]) direction control and when active is used to drive data from the selected memory on to the 1/O bus. 4.3.1.1 Output Control With OE # at logic-high level (Vj), the output from the device is disabled and data input/output pins 4-108 (DQ{0:15] or DQ[0:7]) are tri-stated. Data input is then controlled by WE #. 4.3.1.2 Input Control With WE # at logic-high level (Vj), input to the de- vice is disabled. Data Input/Output pins (DQ-[0:15] or DQ[0:7]) are controlled by OE #. 4.3.2 INTELLIGENT IDENTIFIERS 28F200BX Products The manufacturer and device codes are read via the CUI or by taking the Ag pin to 12V. Writing 90H to the CUI places the device into Intelligent Identifier read mode. A read of location OO000H outputs the manufacturers identification code, 0089H, and loca- tion 00001H outputs the device code; 2274H for 28F200BX-T, 2275H for 28F200BX-B. When BYTE # is at a logic low only the lower byte of the above signatures is read and DQ,5/A_, is a dont care during Intelligent Identifier mode. A read array command must be written to the CUI to return to the read array mode. ADVANGE INFORMATION |intel. 28F002BX Products The manufacturer and device codes are also read via the CUI or by taking the A9 pin to 12V. Writing 90H to the CUI places the device into Intelligent Identifier read mode. A read of location 00000H out- puts the manufacturers identification code, 89H, and location 000014 outputs the device code; 7CH for 28F002BX-T, 7DH for 28F002BX-B. 4.4 Write Operations Commands are written to the CUI using standard mi- croprocessor write timings. The CUI serves as the interface between the microprocessor and the inter- nal chip operation. The CUI! can decipher Read Ar- ray, Read Intelligent Identifier, Read Status Register, Clear Status Register, Erase and Program com- mands. In the event of a read command, the CUI simply points the read path at either the array, the intelligent identifier, or the status register depending on the specific read command given. For a program or erase cycle, the CU! informs the write state ma- chine that a write or erase has been requested. Dur- ing a program cycle, the Write State Machine will control the program sequences and the CUI will only respond to status reads. During an erase cycle, the CUI will respond to status reads and erase suspend. After the Write State Machine has completed its task, it will allow the CUI to respond to its full com- mand set. The CUI will stay in the current command state until the microprocessor issues another com- mand. The CUI will successfully initiate an erase or write operation only when Vpp is within its voltage range. Depending upon the application, the system design- er may choose to make the Vpp power supply switchable, available only when memory updates are desired. The system designer can also choose to hard-wire Vpp to 12V. The 2 Mbit boot block flash family is designed to accommodate either de- sign practice. It is recommended that RP # be tied to logical Reset for data protection during unstable CPU reset function as described in the Product Family Overview section. | ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B 4.4.1 BOOT BLOCK WRITE OPERATIONS In the case of Boot Block modifications (write and erase), RP# is set to Vy = 12V typically, in addi- tion to Vpp at high voltage. However, if RP # is not at Vu when a program or erase operation of the boot block is attempted, the corresponding status register bit (Bit 4 for Program and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indi- cate the failure to complete the operation. 4.4.2, COMMAND USER INTERFACE (CUI) The Command User Interface (CUI) serves as the interface to the microprocessor. The CUI points the read/write path to the appropriate circuit block as described in the previous section. After the WSM has completed its task, it will set the WSM Status bit to a 1, which will also allow the CUI to respond to its full command set. Note that after the WSM has returned control to the CUI, the CUI will remain in its current state. 4.4.2.1 Command Set Command Device Mode Codes 00 Invalid/Reserved 10 Alternate Program Setup 20 Erase Setup 40 Program Setup 50 Clear Status Register 70 Read Status Register 90 Intelligent Identifier BO Erase Suspend bo Erase Resume/Erase Confirm FF - Read Array 4.4.2.2, Command Function Descriptions Device operations are selected by writing specific commands into the CUI. Table 4 defines the 2-Mbit boot block flash family commands. 4-10928F200BX-T/B, 28F002BX-T/B intel. Table 4. Command Definitions Bus Notes First Bus Cycle Second Bus Cycle Command Cycles Req'd! 3 |Operation|Address|Data Operation| Address|Data Read Array/Reset 1 1 Write X FFH intelligent identifier 3 2,4 Write xX 90H| Read IA ID Read Status Register 2 3 Write xX 70H| Read x SRD Clear Status Register 1 Write xX 50H Erase Setup/Erase Confirm 2 5 Write BA 20H; Write BA {DOH Word/Byte Write Setup/Write 2 6,7 Write WA |40H| Write WA | WD Erase Suspend/Erase Resume 2 Write X BOH| Write x DOH Alternate Word/Byte Write Setup/Write| 2 6,7 Write WA /10H] Write WA | WD NOTES: 1. Bus operations are defined in Tables 1, 2, 3. 2. 1A = Identifier Address: OOH for manufacturer code, 01H for device code. 3. SRD = Data read from Status Register. 4. IID = Intelligent Identifier Data. Following the Intelligent Identifier Command, two read operations access manufacturer and device codes. 5. BA = Address within the block being erased. 6. PA = Address to be programmed. PD = Data to be programmed at location PA. 7. Either 40H or 10H command is valid. 8. When writing commands to the device, the upper data bus [DQ8-DQ15] = X (28F200BX-only) which is either Voc or Vgg to avoid burning additional current. Invalid/Reserved These are unassigned commands. It is not recom- mended that the customer use any command other than the valid commands specified above. Intel re- serves the right to redefine these codes for future functions. Read Array (FFH) This single write command points the read path at the array. If the host CPU performs a CE#/OE controlled read immediately following a two-write se- quence that started the WSM, then the device will output status register contents. If the Read Array command is given after Erase Setup the device is reset to read the array. A two Read Array command sequence (FFH) is required to reset to Read Array after Program Setup. Inteligent Identifier (90H) After this command is executed, the CUI points the output path to the Intelligent Identifier circuits. Only intelligent Identifier values at addresses 0 and 1 can be read (only address AO is used in this mode, all other address inputs are ignored). 4-110 Read Status Register (70H) This is one of the two commands that is executable while the state machine is operating. After this com- mand is written, a read of the device will output the contents of the status register, regardless of the ad- dress presented to the device. The device automatically enters this mode after pro- gram or erase has completed. Clear Status Register (50H) The WSM can only set the Program Status and Erase Status bits in the status register, it can not clear them. Two reasons exist for operating the status register in this fashion. The first is a synchro- nization. The WSM does not know when the host CPU has read the status register, therefore it would not know when to clear the status bits. Secondly, if the CPU is programming a string of bytes, it may be more efficient to query the status register after pro- gramming the string. Thus, if any errors exist while programming the string, the status register will return the accumulated error status. ADVANCE INFORMATION |intel. Program Setup (40H or 10H) This command simply sets the CUI into a state such that the next write will load the address and data registers. Either 40H or 10H can be used for Pro- gram Setup. Both commands are included to ac- commodate efforts to achieve an industry standard command code set. Program The second write after the program setup command, will latch addresses and data. Also, the CUI initiates the WSM to begin execution of the program algo- rithm. While the WSM finishes the algorithm, the de- vice will output Status Register contents. Note that the WSM cannot be suspended during program- ming. Erase Setup (20H) Prepares the CUI for the Erase Confirm command. No other action is taken. If the next command is not an Erase Confirm command then the CUI will set both the Program Status and Erase Status bits of the Status Register to a 1, place the device into the Read Status Register state, and wait for another command. Erase Confirm (DOH) lf the previous command was an Erase Setup com- mand, then the CUI will enable the WSM to erase, at the same time closing the address and data latches, and respond only to the Read Status Register and - Erase Suspend commands. While the WSM is exe- cuting, the device will output Status Register data when OE # is toggled low. Status Register data can only be updated by toggling either OE # or CE # low. Erase Suspend (BOH) This command only has meaning while the WSM is executing an Erase operation, and therefore will only be responded to during an erase operation. After this command has been executed, the CUI will set an output that directs the WSM to suspend Erase operations, and then return to responding to only Read Status Register or to the Erase Resume com- mands. Once the WSM has reached the Suspend state, it will set an output into the CUI which allows the CU! to respond to the Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other com- mands. The WSM will also set the WSM Status bit to a 1. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B control pins, with the exclusion of RP#. RP# will immediately shut down the WSM and the remainder of the chip. During a suspend operation, the data and address latches will remain closed, but the ad- dress pads are able to drive the address into the read path. Erase Resume (DOH) This command will cause the CUI to clear the Sus- pend state and set the WSM Status bit to a 0, but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. 4.4.3 STATUS REGISTER The 2-Mbit boot block flash family contains a status register which may be read to determine when a pro- gram or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CUI. After writing this com- mand, all subsequent Read operations output data from the status register until another command is written to the CUI. A Read Array command must be written to the CUI to return to the Read Array mode. The status register bits are output on DQ[0:7] whether the device is in the byte-wide (x8) or word- wide (x16) mode for the 28F200BxX. In the word-wide mode the upper byte, DQ[8:15] is set to OOH during a Read Status command. In the byte-wide mode, DQ[8:14] are tri-stated and DQ15/A1 retains the low order address function. It should be noted that the contents of the status register are latched on the falling edge of OE# or CE# whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE# or OE# must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the mi- croprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits Three through Seven and clears bits Six and Seven, but cannot clear status bits Three through Five. These bits can only be cleared by the controlling CPU through the use of the Clear Status Register command. 4-11128F200BX-T/B, 28F002BX-T/B 4.4.3.1 Status Register Bit Definition intel. Table 5. Status Register Definitions SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS 1 = Error in Byte/Word Program 0 = Successful Byte/Word Program SR.3 = Vpp STATUS 1 = Vpp Low Detect; Operation Abort 0 = Vpp OK SR.2-SR.0 = RESERVED FOR FUTURE ENHANCE- MENTS WSMS Ess ES PS VPPS R R R 7 6 5 4 3 2 1 0 NOTES: Write State Machine Status bit must first be checked to determine byte/word program or block erase completion, before the Program or Erase Status bits are checked for success. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to 1. ESS bit re- mains set to 1 until an Erase Resume command is is- sued. When this bit is set to 1. WSM has applied the maxi- mum number of erase pulses to the block and is still un- able to successfully perform an erase verify. When this bit is set to 1, WSM has attempted but failed to Program a byte or word. The Vpp Status bit, unlike an A/D converter, does not provide continuous indication of Vpp level. The WSM in- terrogates the Vpp level only after the byte write or block erase command sequences have been entered and in- forms the system if Vpp has not been switched on. The Vpp Status bit is not guaranteed to report accurate feed- back between Vpp, and Vppx. These bits are reserved for future use and should be masked out when polling the Status Register. 4.4.3.2 Clearing the Status Register Certain bits in the status register are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure con- ditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in se- quence). The status register may then be read to determine if an error occurred during that program- ming or erasure series. This adds flexibility to the way the device may be programmed or erased. To clear the status register, the Clear Status Register command is written to the CUI. Then, any other command may be issued to the CUI. Note again that before a read cycle can be initiated, a Read Array command must be written to the CUI to specify whether the read data is to come from the array, status register, or Intelligent Identifier. 4-112 4.4.4 PROGRAM MODE Program is executed by a two-write sequence. The Program Setup command is written to the CUI fol- lowed by a second write which specifies the address and data to be programmed. The write state ma- chine will execute a sequence of internally timed events to: 1. Program the desired bits of the addressed memo- ty word (byte), and 2. Verify that the desired bits are sufficiently pro- grammed Programming of the memory results in specific bits within a byte or word being changed to a 0. If the user attempts to program 1s, there will be no change of the memory cell content and no error oc- curs. Similar to erasure, the status register indicates whether programming is complete. While the pro- gram sequence is executing, bit 7 of the status regis- ter is a 0. The status register can be polled by ADVANCE INFORMATION |intel. toggling either CE# or OE # to determine when the program sequence is complete. Only the Read Status Register command is valid while program- ming is active. When programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. If the programming operation was unsuccessful, Bit 4 of the status regis- ter is set to a 1 to indicate a Program Failure. !f Bit 3 is set then Vpp was not within acceptable limits, and the WSM will not execute the programming se- quence. The status register should be cleared before at- tempting the next operation. Any CUI instruction can follow after programming is completed; however, it must be recognized that reads from the memory, status register, or Intelligent Identifier cannot be ac- complished until the CUI is given the appropriate command. A Read Array command must first be giv- en before memory contents can be read. Figure 12 shows a system software flowchart for de- vice byte programming operation. Figure 13 shows a similar.flowchart for device word programming oper- ation (28F200BX-only). 4.4.5 ERASE MODE Erasure of a single block is initiated by writing the Erase Setup and Erase Confirm commands to the CUI, along with the addresses, A[12:16] for the 28F200BX or A[12:17] for the 28F002Bx, identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is is- sued. Block erasure results in all bits within the block being set to 1. The WSM will execute a sequence of internally timed events to: 1. Program all bits within the block 2. Verify that all bits within the block are sufficiently programmed 3. Erase all bits within the block and 4. Verify that all bits within the block are sufficiently erased While the erase sequence is executing, Bit 7 of the status register is a 0. When the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erasure operation was unsuccessful, Bit 5 of the status register is set to a 1 to indicate an Erase Failure. If Vpp was not within acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, Bit 5 of the status register is set to a 1 to indicate | ADVANCE INFORMATION 28F200BX-T/B, 28F002BX-T/B an Erase Failure, and Bit 3 is set to a 1 to identify that Vpp supply voltage was not within acceptable limits. The status register should be cleared before at- tempting the next operation. Any CUI instruction can follow after erasure is completed; however, it must be recognized that reads from the memory array, status register, or {ntelligent Identifier can not be ac- complished until the CUI is given the appropriate command. A Read Array command must first be giv- en before memory contents can be read. Figure 14 shows a system software flowchart for Block Erase operation. 4.4.5.1 Suspending and Resuming Erase Since an erase operation typically requires 1 to 3 seconds to complete, an Erase Suspend command is provided. This allows erase-sequence interruption in order to read data from another block of the mem- ory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the Write State Machine (WSM) pause the erase se- quence at a predetermined point in the erase algo- rithm. The status register must be read to determine when the erase operation has been suspended. At this point, a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended. The only other valid command at this time is the Erase Resume command or Read Status Register operation. Figure 15 shows a system software flowchart detail- ing the operation. During Erase Suspend mode, the chip can go into a pseudo-standby mode by taking CE # to Vi, and the active current is now a maximum of 10 mA. If the chip is enabled while in this mode by taking CE # to Vit, the Erase Resume command can be issued to resume the erase operation. Upon completion of reads from any block other than the block being erased, the Erase Resume com- mand must be issued. When the Erase Resume command is given, the WSM will continue with the erase sequence and complete erasing the block. As with the end of erase, the status register must be read, cleared, and the next instruction issued in or- der to continue. 4.4.6 EXTENDED CYCLING Intel has designed extended cycling capability into its ETOX Ill flash memory technology. The 2-Mbit boot block flash family is designed for 100,000 pro- gram/erase cycles on each of the five blocks. The combination of low electric fields, clean oxide pro- cessing and minimized oxide area per memory cell subjected to the tunneling electric field, results in very high cycling capability. 4-11328F200BX-T/B, 28F002BX-T/B intel. Write 40H, Byte Address 1 Write Byte Address/Data wi < Read Status Register NO YES Full Status Check If Desired Byte Program Completed 290448-6 Full Status Check Procedure Status Register Data Read (See Above) Vpp Range Error Byte Program Error Byte Program Successful 290448-7 Bus Command Comments Operation Write Setup Data = 40H Program Address = Byte to be programmed Write Program Data to be programmed Address = Byte to be programmed Read Status Register Data. Toggle OE # or CE # to update Status Register Standby Check SR.7 1 = Ready, 0 = Busy Repeat for subsequent bytes. Full status check can be done after each byte or after a sequence of bytes. Write FFH after the last byte programming operation to reset the device to Read Array Mode. Bus Operation Command Comments Standby Check SR.3 1 = Vpp Low Detect Standby Check SR.4 1 = Byte Program Error SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register Command, in cases where multiple bytes are programmed before full status is checked. \f error is detected, clear the Status Register before attempting retry or other error recovery. Figure 12. Automated Byte Programming Flowchart 4-114 ADVANCE INFORMATIONintel. 28F200BX-T/B, 28F002BX-T/B Write 40H, Word Address 1 Write Word Address/Data Read Status Register NO YES Full Status Check If Desired Word Program Completed 280448-8 Full Status Check Procedure Status Register Data Read (See Above) Vpp Range Error Byte Program Error YES Word Program Successful 290448-9 Bus Operation Command Comments Write Setup Data = 40H Program Address = Word to be programmed Write Program Data to be programmed Address = Word to be programmed Read Status Register Data. Toggle OE # or CE # to update Status Register Standby Check SR.7 1 = Ready, 0 = Busy Repeat for subsequent words. Full status check can be done after each word or after a sequence of words. Write FFH after the last word programming operation to reset the device to Read Array Mode. Bus Command Comments Operation Standby Check SR.3 1 = Vpp Low Detect Standby Check SR.4 1 = Word Program Error SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register Command, in cases where multiple words are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 13. Automated Word Programming Flowchart ADVANCE INFORMATION 4-11528F200BX-T/B, 28F002BX-T/B intel. Write 20H, Block Address 4 Write DOH, Block Address 4. i? Read Status Register Suspend Erase Loop Fuil Status Check If Desired Block Erase Completed 290448-10 Full Status Check Procedure Status Register Data Read (See Above) Vpp Range Error Command Sequence Error Block Erase Error YES Block Erase Successful 290448-11 Bus Operation Command Comments Write Setup Data = 20H Erase Address = Within block to be erased Write Erase Data = DOH Address = Within block to be erased Read Status Register Data. Toggle OE # or CE # to update Status Register Standby Check SR.7 1 = Ready, 0 = Busy Repeat for subsequent blocks. Full status check can be done after each block or after a sequence of blocks. Write FFH after the last block erase operation to reset the device to Read Array Mode. Bus Operation Command Comments Standby Check SR.3 1 = Vpp Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SA.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 14. Automated Block Erase Flowchart 4-116 ADVANGE INFORMATION28F200BX-T/B, 28F002BX-T/B Write BOH + Read Status Register Erase Has Completed Write DOH 290448-12 Bus Command Comments Operation Write Erase Data = BOH Suspend Read Status Register Data. Toggle OF # or CE # to update Status Register Standby Check SR.7 1 = Ready Standby Check SR.6 1 = Suspended Write Read Array Data = FFH Read Read array data from block other than that being erased. Write Erase Resume | Data = DOH Figure 15. Erase Suspend/Resume Flowchart 4.5 Power Consumption 4.5.1 ACTIVE POWER With CE # at a logic-low level and RP# ata logic- high level, the device is placed in the active mode. The device Icc current is a maximum of 60 mA at 10 MHz with TTL input signals. 4.5.2 AUTOMATIC POWER SAVINGS Automatic Power Savings (APS) is a low power fea- ture during active mode of operation. The 2-Mbit family of products incorporate Power Reduction Control (PRC) circuitry which basically allows the de- vice to put itself into a low current state when it is not being accessed. After data is read from the memory array, PRC logic controls the devices pow- er consumption by entering the APS mode where ADVANCE INFORMATION maximum Icc current is 3 mA and typical Icc current is 1 mA. The device stays in this static state with outputs valid until a new location is read. 4.5.3 STANDBY POWER With CE # at a logic-high level (Vj4), and the CU! in read mode, the memory is placed in standby mode where the maximum Icc standby current is 100 pA with CMOS input signals. The standby operation dis- ables much of the device's circuitry and substantially reduces device power consumption. The outputs (DQ[0:15] or DQ[0:7]) are placed in a high-imped- ance state independent of the status of the OE# signal. When the 2-Mbit boot block flash family is deselected during erase or program functions, the devices will continue to perform the erase or pro- gram function and consume program or erase active power until program or erase is completed. 4-11728F200BX-T/B, 28F002BX-T/B 4.5.4 RESET/DEEP POWER-DOWN The 2-Mbit boot block flash family supports a typical Icc of 0.2 A in deep power-down mode. One of the target markets for these devices is in portable equip- ment where the power consumption of the machine is of prime importance. The 2-Mbit boot block flash family has a RP # pin which places the device in the deep power-down mode. When RP# is at a logic- low (GND +0.2V), all circuits are turned off and the device typically draws 0.2 wA of Voc current. During read modes, the RP# pin going low dese- lects the memory and places the output drivers in a high impedance state. Recovery from the deep pow- er-down state, requires a minimum of 400 ns to ac- cess valid data (tpyay). During erase or program modes, RP # low will abort either erase or program operation. The contents of the memory are no longer valid as the data has been corrupted by the RP# function. As in the read mode above, all internal circuitry is turned off to achieve the 0.2 4A current level. RP transitions to Vi_ or turning power off to the device will clear the status register. This use of RP# during system reset is important with automated write/erase devices. When the sys- tem comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during write/ erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intels Flash Memories allow proper CPU initialization fol- lowing a system reset through the use of the RP# input. in this application RP# is controlled by the same RESET# signal that resets the system CPU. 4.6 Power-Up Operation The 2-Mbit boot block flash family is designed. to offer protection against accidental block erasure or programming during power transitions. Upon power- up the 2-Mbit boot block flash family is indifferent as to which power supply, Vpp or Voc, powers-up first. Power suppy sequencing is not required. The 2-Mbit boot block flash family ensures the CUI is reset to the read mode on power-up. In addition, on power-up the user must either drop CE# low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes for Vcc voltages above Viko when Vpp is 4-118 a intel. active. Since both WE # and CE# must be low for a command write, driving either signal to Vjy will inhibit writes to the device. The CUI architecture provides an added level of protection since alteration of mem- ory contents can only occur after successful com- pletion of the two-step command sequences. Fina!- ly, the device is disabled until RP # is brought to Vin, regardless of the state of its control inputs. This fea- ture provides yet another level of memory protec- tion. 4.7 Power Supply Decoupling Flash memorys power switching characteristics re- quire careful device decoupling methods. System designers are interested in 3 supply current issues: Standby current levels (Iccs) Active current levels (Iccr) Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 pF ceramic capacitor connected between each Vcc and GND, and be- tween its Vpp and GND. These high frequency, low- inherent inductance capacitors should be placed as close as possible to the package leads. 4.7.1 Vpp TRACE ON PRINTED CIRCUIT BOARDS Writing to flash memories while they reside in the target system, requires special consideration of the Vpp power supply trace by the printed circuit board designer. The Vpp pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout consider- ations given to the Vcc power supply trace. Ade- quate Vpp supply traces and decoupling will de- crease spikes and overshoots. 4.7.2 Vcc, Vpp AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by Vpp or CE# tran- sitions or WSM actions. Its state upon power-up, af- ter exit from deep power-down mode or after Voc transitions below Vio (Lockout voltage), is Read Array mode. After any word/byte write or block erase operation is complete and even after Vpp transitions down to Vpp_, the CUI must be reset to Read Array mode via the Read Array command when accesses to the flash memory are desired. ADVANCE INFORMATIONintal. ABSOLUTE MAXIMUM RATINGS* Commercial Operating Temperature During Read .................05. 0C to 70C(t) During Block Erase and Word/Byte Write............... 0C to 70C Temperature Under Bias....... 10C to + 80C Extended Operating Temperature During Read ................. 40C to + 85C During Block Erase and Word/Byte Write ......... 40C to + 85C Temperature Under Bias....... 40C to + 85C Storage Temperature .......... 65C to + 125C Voltage on Any Pin (except Voc, Vpp, Ag and RP #) with Respect toGND ........ 2.0V to +7.0V(2) Voltage on Pin RP# or Pin Ag with Respect toGND ..... ~2,0V to + 13.5V02, 3) Vpp Program Voltage with Respect to GND during Block Erase and Word/Byte Write ..... 2.0V to + 14.0V(2, 3) Voc Supply Voltage with Respect toGND ........ ~2.0V to + 7.0V(2) Output Short Circuit Current............. 100 mA(4) NOTES: 28F200BX-T/B, 28F002BX-T/B NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. 1. Operating temperature is for commercial product defined by this specification. 2, Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Vcc + 0.5V which, during transitions, may overshoot to Voc + 2.0V for periods <20 ns. 3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns. Maximum DC voltage on RP# or Ag may overshoot to 13.5V for periods < 20 ns. 4, Output shorted for no more than one second. No more than one output shorted at a time. 5. 10% Vcc specifications reference the 28F200BX-60/28F002BX-60 in their standard test configuration, and the 28F200BX-80/28F002BX-80. 6. 5% Voc specifications reference the 28F200BX-60/28F002BX-60 in their high speed test configuration. OPERATING CONDITIONS Symbol Parameter Notes | Min | Max | Units Ta Operating Temperature 0 70 C Voc Voc Supply Voltage (10%) 5 4.50 | 5.50 Vv Voc Voc Supply Voltage (5%) 6 4.75 | 5.25 Vv DC CHARACTERISTICS Symbol Parameter Notes | Min | Typ Max Unit Test Condition tt Input Load Current 1 +1.0 pA Voc = Voc Max Vin = Voc or GND ILo Output Leakage Current 1 +10 pA Voc = Voc Max Vout = Voc or GND | ADVANCE INFORMATION 4-119a 28F200BX-T/B, 28F002BX-T/B | ntel DC CHARACTERISTICS (Continued) Symbol Parameter Notes] Min |Typ| Max [Unit Test Condition locs Voc Standby Current 1,3 1.5 MA |Voc = Voc Max CE# = RP# = Viy 100 BA \Voc = Voc Max CE# = RP# = Vcc 0.2V 28F200BXx: BYTE# = Voc 0.2V or GND Iccp |Vcc Deep Power-Down Current | 1 0.20 1.2 pA |RP# = GND +0.2V IccR |Voc Read Current for 1,5, 20 55 MA |Vcc = Vcc Max, CE# = GND 28F200BX Word-Wide and 6, 1 f = 10 MHz, lout = OMA Byte-Wide Mode and CMOS Inputs 28F002BX Byte-Wide Mode 20 60 mA |Voc = Voc Max, CE# = Vi. f = 10 MHz, lout = OMA TTL Inputs Iccw |Vcc Word Byte Write Current 1,4 65 mA |Word Write in Progress Ioce Voc Block Erase Current 1,4 30 mA | Block Erase in Progress \cceEs |Vcc Erase Suspend Current 1,2 5 10 mA | Block Erase Suspended, CE# = Vin Ipps Vpp Standby Current +15 pA |Vpp < Voc 5.0 pA |RP# = GND +0.2V RP# 200 pA |Vpp > Voc 40 mA |Vpp = Vppy Word Write in Progress lppp Vpp Deep Power-Down Current lppR Vpp Read Current ajea{[af{oa 'ppw | Vpp Word Write Current Ippw | Vpp Byte Write Current 1 30 MA |Vpp = VppH Byte Write in Progress IppE Vpp Block Erase Current 1 30 mA |Vpp = VppH Block Erase in Progress lppes |Vpp Erase Suspend Current 1 200 pA |Vpp = VeppH Block Erase Suspended Inp# RP# Boot Block Unlock Current] 1, 4 500 pA |RP# = Vin lio Ag Intelligent Identifier Current 1,4 500 BLA |Ag = Vip Vio Ag Intelligent Identifier Voltage 11.5 13.0 Vv Vit Input Low Voltage -0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5) V VoL Output Low Voltage 0.45 V iVoc = Vcc Min lo. = 5.8mA 4-120 ADVANCE INFORMATION |a i ntel 28F200BX-T/B, 28F002BX-T/B DC CHARACTERISTICS (Continued) Symbol Parameter Notes | Min | Typ | Max | Unit Test Condition Vou Output High Voltage 2.4 V_| Voc = Vcc Min lon = 2.5mA VepPL Vpp during Normal Operations 3 0.0 65, V VppH Vpp during Erase/Write Operations 7 11.4] 12.0] 126) V VepH Vpp during Erase/Write Operations 8 10.8 | 12.0)13.2) V ViKo Voc Erase/Write Lock Voltage 2.0 Vv VHH RP# Unlock Voltage 11.5 13.0) V_ | Boot Block Write/Erase EXTENDED TEMPERATURE OPERATING CONDITIONS Symbol Parameter Notes | Min Max | Units Ta Operating Temperature -40 |} +85 C Voc Voc Supply Voltage (10%) 5 4.50 | 5.50 Vv DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION Symbol Parameter Notes | Min | Typ | Max | Unit Test Condition Iu Input Load Current 1 +1.0] mA | Voc = Voc Max Vin = Voc or GND ILo Output Leakage Current 1 +10 | pA | Voc = Voc Max Vout = Vcc or GND locs Voc Standby Current 1,3 1.5 | mA | Voc = Voc Max CE# = RP# = Vin 100 | wA | Voc = Voc Max CE# = RP# = Vcc +0.2V 28F200Bx: BYTE# = Vcc +0.2V or GND locp Voc Deep Power-Down Current 1 0.20; 8 pA | RP# = GND +0.2V loon Voc Read Current for 1, 5, 60 j; mA | Vcc = Vcc Max, CE# = GND 28F200BX Word-Wide and 6 f = 10 MHz, loyt = OMA Byte-Wide Mode and CMOS Inputs 28F002BX Byte-Wide Mode 65 | mA | Voc = VooMax, CE# = Vi, f = 10 MHz, loyt = OMA TTL Inputs | ADVANGE INFORMATION 4-121s 28F200BX-T/B, 28F002BX-T/B | ntel DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued) Symbol Parameter Notes| Min | Typ Max Unit Test Condition locw Voc Word Byte Write Current 1 70 __| mA | Word Write in Progress loce Voc Block Erase Current 1 40 mA | Block Erase in Progress Icces |Voc Erase Suspend Current 1,2 5 10 mA | Block Erase Suspended CE# = Vin Ipps Vpp Standby Current +15 pA | Vpp < Voc 5.0 pA | RP# = GND +0.2V 200 pA | Vpp > Voc 40 MA | Vpp = VepH Word Write in Progress Ippp Vpp Deep Power-Down Current IppR Vpp Read Current afta fo] o Ippw Vpp Word Write Current Ippw Vpp Byte Write Current 1 30 mA | Vpp = VppyH Byte Write in Progress IppE Vpp Block Erase Current 1 30 mA | Vpp = VppH Block Erase in Progress Ippeg | Vpp Erase Suspend Current 1 200 pA | Vpp = Vepy Block Erase Suspended IRP# RP # Boot Block Unlock Current 1,4 500 pA |RP# = Viy ho Ag Intelligent Identifier Current 1 500 BA | Ag = Vip Vio Ag Intelligent identifier Voltage 11.5 13.0 Vv Vit Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5| V VoL Output Low Voltage 0.45 V Vcc = Voc Min lo. = 5.8mA VoH Output High Voltage 2.4 V {Voc = Voc Min lon = 2.5mA Vpp_ | Vpp during Normal Operations 3 0.0 6.5 V VppH Vpp during Erase/Write Operations| 7 11.4 | 12.0 12.6 Vv VppH Vpp during Erase/Write Operations; 8 10.8 | 12.0 13.2 Vv Viko | Voc Erase/Write Lock Voltage 2.0 Vv VHH RP# Unlock Voltage 11.5 13.0 V_ | Boot Block Write/Erase 4-122 ADVANCE INFORMATIONintel. CAPACITANCE(4 9) T, = 25C, f = 1 MHz 28F200BX-T/B, 28F002BX-T/B Symbol Parameter Typ Max Unit Condition Cin Input Capacitance 6 8 pF Vin = OV Cout Output Capacitance 10 12 pF Vout = 0V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, Vpp = 12.0V, T = 25C. These currents are valid for all product versions (packages and speeds). 2. Ioces is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum of Icces and Iccr. 3. Block Erases and Word/Byte Writes are inhibited when Vpp = Vppi and not guaranteed in the range between Vpp}; and VPPL: 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces Iccp to less than 1 mA typical in static operation. 6. CMOS Inputs are either Voc +0.2V or GND +0.2V. TTL Inputs are either Vi. or Vin. 7. Vpp = 12.0V +5% for applications requiring 100,000 block erase cycles. 8. Vpp = 12.0V +10% for applications requiring wider Vpp tolerances at 100 block erase cycles. 9. For the 28F002BX, address pin A4o follows the Coyy capacitance numbers. 10. Iccr typical is 25 mA for X16 active read current. STANDARD TEST CONFIGURATION(1) STANDARD AC INPUT/OUTPUT REFERENCE WAVEFORM m input X 7 > TEST POINTS <x. OUTPUT 0.45 0.8 oe 0.8 . af 290448-14 AC test inputs are driven at Voy (2.4 Vt) for a Logic 1 and VoL (0.45 VrtL) for a logic 0. Input timing begins at Viy (2.0 VrrL) and Vic (0.8 Vr7L). Output timing ends at Vi, and Vi. Input rise and fall times (10% to 90%) < 10 ns. HIGH SPEED TEST CONFIGURATION(2) HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM 3.0 5 INPUT YK 1.s-< test POINTs > %1.5 OUTPUT 0.0 290448-22 AC test inputs are driven at 3.0V for a Logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) < 10 ns. NOTES: 1. Testing characteristics for 28F200BX-60/28F002BX-60 in standard test config- uration and 28F200BX-80/28F002BXx-80. 2. Testing characteristics for 28F200BX-60/28F002BX-60 in high speed test con- figuration. ADVANCE INFORMATION STANDARD AC TESTING LOAD CIRCUIT 1.3 | 1N914 RX DEVICE UNDER OUT TEST T G 290448-13 CL = 100 pF C\ Includes Jig Capacitance RL = 3.3 KO HIGH SPEED AC TESTING LOAD CIRCUIT 1.3V 1NO14 R DEVICE UNDER ouT TEST T G 290448-21 CL = 30 pF C, includes Jig Capacitance RL = 3.3 KO 4-123a 28F200BX-T/B, 28F002BX-T/B | ntel AC CHARACTERISTICSRead Only Operations(1) Vec +5% Voc + 10% Versions 28F200BX-60(4) | 28F200BX-60(5) | 28F200BX-80(5) || . 28F002BX-60(4) | 28F002BX-60(5) | 28F002BX-80(5) Symbol! Parameter Notes; Min Max Min Max Min Max tavav |tac |Read Cycle Time 60 70 80 ns tavav |tacc jAddress to 60 70 80 ns Output Delay teLav |tce |CE# to Output Delay 2 60 70 80 ns tpHav | tewH] RP # High to 300 300 300 ns Output Delay tetov |toe |OE# to Output Delay 2 30 35 40 ns teLox |tLz |CE# to OutputLowZ| 3 0 0 0 ns teHoz|tHz {CE# High to Output 3 20 25 30 ns High Z teLox |toLz |OE# to Output LowZ|] 3 0 0 0 ns tgHazitpr |OE# High to Output 3 20 25 30 ns High Z tox |Output Hold from 3 0 0 0 ns Addresses, CE# or OE # Change, Whichever is First tELFL CE# to BYTE# 3 5 5 5 ns tELFH Switching Low or High tFHOV BYTE # Switching 3,6 60 70 80 ns High to Valid Output Delay tFLQz BYTE # Switching 3 20 25 30 ns Low to . Output High Z NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tce-tog after the falling edge of CE# without impact on tog. 3. Sampled, not 100% tested. 4. See High Speed Test Configuration. 5. See Standard Test Configuration. 6. teLqv, BYTE# switching low to valid output delay, will be equal to tayqy, measured from the time DQ15/A-; becomes valid. 4-124 ADVANCE INFORMATIONa i ntel 28F200BX-T/B, 28F002BX-T/B EXTENDED TEMPERATURE OPERATIONS AC CHARACTERISTICSRead Only Operations(1): T28F200BX-80(4) Versions T28F002BX-80(4) Unit Symbol Parameter Notes Min Max tavaV trc Read Cycle Time 80 ns tavav tacc Address to 80 ns Output Delay tELav tceE CE# to Output Delay 2 80 ns tpHav tewH RP# High to 300 ns Output Delay teLav tor OE # to Output Delay 2 40 ns tELox tLz CE # to Output Low Z 3 0 ns teHaz tHz CE # High to Output 3 30 ns High Z tatox toLz OE # to Output Low Z 3 0 ns t6Haz tor OE # High to Output 3 30 ns High Z toH Output Hold from 3 0 ns Addresses, CE# or OE # Change, Whichever is First tELFL CE # to BYTE# 3 5 ns tELFH Switching Low or High tFHAV BYTE # Switching 3,5 80 ns High to Valid Output Delay tFLaz BYTE# Switching 3 30 ns Low to Output High Z NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE # may be delayed up to tce-tog after the falling edge of CE # without impact on tcg. 3. Sampled, not 100% tested. 4. See Standard Test Configuration. 5. teLav, BYTE # switching low to valid output delay, will be equa! to tayaqy, measured from the time DQs/A-, becomes valid. ADVANCE INFORMATION 4-12528F200BX-T/B, 28F002BX-T/B SL-8rr06e 7 7 W {d) #du Hy ADHd, | ano AOS ADA, 7 _ - YT Wn ANdLNO GVA b (0/0) viva Z HOIH K Z HOIH _ ___._._.____L XO7R, Hla ~| HO, _.| ba x019, ADT, pe ADI, (M) #3M [> ZDHS, Cf |_ A be an (9) #30 Wy [ Hi, MW / Hi, AVAY, NMO0-43MOd 2A ABONVLS \ Ws \ / (3) #39 Hl, anva viva 31avis sassaaday G3 18YN3I SiNdLNO NOHMLOITIS SS3YddV GNY 351A30 V Ty KX XX KKK (v) sassayaqv ] Hla, AGQNW1S dQ-YaMod 2A Figure 16. AC Waveforms for Read Operations ADVANCE INFORMATION | 4-126a i ntel 28F200BX-T/B, 28F002BX-T/B log (mA) log (ma) 12345 6 7 8 9 101112131415 16 FREQUENCY (MHz) 123 45 6 7 8 10111213 1415 16 FREQUENCY (MHz) 290448-26 Figure 17. Icc (RMS) vs Frequency (Voc = 5.5V) for x16 Operation 290448-27 Figure 18. icc (RMS) vs Frequency (Voc = 5.5V) for x8 Operation 100 95 90 85 ~ 80 Pal eo a = 70) <4 ma |_| 4 sod rm 28F 2008X/28F002BX-60 O 28F 200BX/28F002BX-B0 ott | | | 30 50 100 150 200 250 OUTPUT CAPACITANCE (pF) 290448~28 Figure 19. Tacc vs Output Load Capacitance (Voc = 4.5V, T = 70C) ADVANCE INFORMATION 4-12728F200BX-T/B, 28F002BX-T/B 62-8hh06e V S'oq No indino viva A Z Z HOIH N zo14, + ADAY, V// 0-2 4oq-nd No dy NO LNdino Indino viva AR viva Z| ot X07, le x09, | ee HO, aot, AdT9, / \ Z HOIH ZOHO, c Se Z0H3, fTt~CCNCSCSSSSC 1413, r : ABGNVILS 147. AY, [NY AVAY, \_- --- Kee anva Viva a1avis Sassaydav NOILOI1aS SS3IYadV JOIAId be KA AGONVIS ad, t-/ Slog (*'pa-%oq) viva W (40a-%a) viva Hl, WW (4) #3148 Hl, Wa () sassayaav Hy, Figure 20. BYTE # Timing for Both Read and Write Operations for 28F200BX ADVANCE INFORMATION | 4-128a | ntel 28F200BX-T/B, 28F002BX-T/B AC CHARACTERISTICS For WE #-Controlled Write Operations(t) Voc +5% Vec + 10% Versions 28F200BX-60(8) | 28F200BX-60(10) | 28F200BX-80(10) Unit 28F002BX-60(9) | 28FO02BX-60(19) | 28F002BX-80(10) Symbol Parameter Notes| Min Max Min Max Min Max tavav. itwc |Write Cycle Time 60 70 80 ns tpHwe jtps |RP# High 215 215 215 ns Recovery to WE # Going Low teLw. |tcs 1CE# Setup to WE# 0 0 0 ns Going Low tpHHWH|tpHs | RP# Vi Setup to | 6,8 100 100 100 ns WE # Going High tvpwH |tvps |Vpp Setup toWE# | 5,8 100 100 100 ns Going High tavwH jtas |Address Setup to 3 50 50 50 ns WE # Going High topvwH |tps |DataSetuptoWE#! 4 60 . 60 60 ns Going High twLwH |twe |WE# Pulse Width 50 50 50 ns twHpx |tpH |Data Hold from 4 0 0 0 ns WE # High twHax itaH |Address Hold 3 10 10 10 ns from WE # High tWHEH |tcH |CE# Hold from 10 10 10 ns WE # High twHWL |tweH| WE# Pulse 10 20 30 ns Width High twHovi Duration of 2,5 6 6 6 pS Word/Byte Write Operation twHave Duration of Erase |2,5,6} 0.3 0.3 0.3 s Operation (Boot) twHav3 Duration of Erase 2,5 0.3 0.3 0.3 s Operation (Parameter) twHavs Duration of Erase |2,5,6 0.6 0.6 0.6 s Operation (Main) tow. = | tveH | Vpp Hold from 5,8 0 0 0 ns Valid SRD | ADVANCE INFORMATION 4-129a 28F200BX-T/B, 28F002BX-T/B i ntel AC CHARACTERISTICS For WE#-Controlled Write Operations(1) (Continued) Vec +5% Vec + 10% Versions 28F200BX-60(9) | 28F200BX-60(19) | 28F200BX-80(10) || 28F002BX-60(9) 28F002BX-60(10) | 28F002BX-80(10) Symbol Parameter |Notes| Min Max Min Max Min Max tovperH | tpHH | RP-# Vi Hold] 6,8 0 0 0 ns from Valid SRD tpHBR Boot-Block 7,8 100 100 100 ns Relock Delay NOTES: 1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC characteristics during Read Mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter- nally which includes verify and margining operations. 3. Refer to command definition tabie for valid Ajj. 4. Refer to command definition table for valid Diy. 5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1). 6. For Boot Block Program/Erase, RP# should be held at Vij}4 until operation completes successfully. 7. Time tpygR, is required for successful relocking of the Boot Biock. 8. Sampled but not 100% tested. 9. See High Speed Test Configuration. 10. See Standard Test Configuration. BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp = 12.0V +5% 28F200BX-60 28F200BX-80 Parameter Notes 28F002BX-60 28F002BX-80 Unit Min Typ) Max Min Typ) Max Boot/Parameter 2 1.0 7 1.0 7 s Block Erase Time Main Block 2 2.4 14 2.4 14 s Erase Time Main Block Byte 2 1.2 4.2 1.2 4.2 s Program Time Main Block Word 2 0.6 2.1 0.6 2.1 s Program Time NOTES: 1. 26C 2. Excludes System-Level Overhead. BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp = 12.0V + 10% 28F200BX-60 28F200BX-80 Parameter Notes 28F002BX-60 28F002BX-80 Unit Min Typ() Max Min Typ() Max Boot/Parameter 2 5.8 40 5.8 40 s Block Erase Time Main Block 2 14 60 14 60 s Erase Time Main Biock Byte 2 6.0 20 6.0 20 s Program Time Main Block Word 2 3.0 10 3.0 10 s Program Time NOTES: 1. 26C 2. Excludes System-Level Overhead. 4-130 ADVANGE INFORMATION |a j ntel 28F200BX-T/B, 28F002BX-T/B EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS For WE #-Controlled Write Operations(1): Versions( 120F0028%-200) | unt Symbol Parameter Notes Min Max tavav two Write Cycle Time 80 ns tpHWL tps RP# High Recovery to 220 ns WE # Going Low teLwe tcs CE # Setup to WE # Going Low 0 ; ns tPHHWH tpHs RP # Vin Setup to WE # Going High 6,8 100 ns tvPWH types Vpp Setup to WE # Going High 5,8 100 ns tavwH tas Address Setup to WE # Going High 3 60 ns tovwH tps Data Setup to WE # Going High 4 60 ns twLWH twp WE # Pulse Width 60 ns twHpx tou Data Hoid from WE # High 4 0 ns tWHAX taH Address Hold from WE # High 3 10 ns tWHEH tcH CE # Hold from WE # High 10 ns tWHWL tweH WE # Pulse Width High 20 ns twHavi Duration of Word/Byte 2,5 7 pS ni Write Operation twHave Duration of Erase Operation (Boot) 2,5,6 0.4 s twHav3 Duration of Erase 2,5 0.4 s Operation (Parameter) twHava Duration of Erase Operation (Main) 2, 5,6 0.7 s tawL tveH Vpp Hold from Valid SRD 5,8 0 ns tavPH tPHH RP# Viyy Hold from Valid SRD 6,8 0 ns tpHBR Boot-Block Relock Delay 7,8 100 ns NOTES: 1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC characteristics during Read Mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter- nally which includes verify and margining operations. . Refer to command definition table for valid Ayy. . Refer to command definition table for valid Diy. . Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1). . For Boot Block Program/Erase, RP# should be held at Vi until operation completes successfully. . Time tpyppR is required for successful relocking of the Boot Block. . Sampled but not 100% tested. . See Standard Test Configuration. OONDOALD | ADVANCE INFORMATION 4-131| 28F200BX-T/B, 28F002BX-T/B i ntel EXTENDED TEMPERATURE OPERATION BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp = 12.0V +5% T28F200BX-80 Parameter Notes T28F002BX-80 Unit Min Typ) Max Boot/Parameter 2 1.5 10.5 s Block Erase Time Main Biock 2 3.0 18 s Erase Time Main Block Byte 2 1.4 5.0 s Program Time Main Biock Word 2 0.7 2.5 s Program Time NOTES: 1. 25C, 12.0V Vpp. 2. Excludes System-Level Overhead. 4-132 ADVANCE INFORMATION28F200BX-T/B, 28F002BX-T/B 9t-S8rr06e Rene aRNRNR| V/ AY YWYVYYVYYYYYYVYVY XX RXKRXRY RRS OAR aN EOI HA iy) at Y XX XXX KKK KKK KKK \/ AAS XXX) ) ( {) ) ) () iy 7d. dy TAAD, HMdAy Al ry | [ (d) ad v i AS 9 K-4H----------f-- hi HdAl } Leg HAH} Hoy I, AN [.,\ Ps "s ( % ) \\ anv t7/ { a >} 4 Ny oo viva XOHM, -] Hac, HATA, 1 /\ / \ [wae fat VEZ LADHMy SEER | j~< TAHA, e "a Al lA, / \ / (9) #30 HI 4 H3HA, > be 13, *, / \ / \ / \ / YS (3) #39 HI 4 XVHA, HMAY, AVAY, VY (XXX KKK XXXX XX) KXXXXXKXX XK x) XX XX VV XX VY x y A CEERI IRR rsa ONVYANOD AVUaY OVIY Fam VIVO YaLSI93 SMiVIS OV2 QONVNNOD WYIL4NOD 3SV4a 40 (Wyu90ud) V1G B SSauday GITVA 3LIUM AW130 3S43 YO WVY90Nd G3ILVWOLNY ABONVIS dh-4aM0d 9A GNVYAWOD dNl3s 3Svag YO WVY9ONd TLISM Figure 21. AC Waveforms for Write and Erase Operations (WE #-Controlled Writes) | ADVANCE INFORMATION 4-13328F200BX-T/B, 28F002BX-T/B AC CHARACTERISTICS FOR CE #-CONTROLLED WRITE OPERATIONS, 9) intel. Voc 15% Vec + 10% Versions 28F200BX-60(10) | 28F200BX-60(11) | 28F200BX-80(11) ||| 28F002BX-60(10) | 28FO02BX-60(11) | 28FOO2BX-80(11) Symbol Parameter Notes; Min Max Min Max Min Max tavav |two |Write Cycle Time 60 70 80 ns tpHeL |tps |RP# High Recovery 215 215 215 ns to CE# Going Low tWLeL |tws |WE# Setup to CE# 0 0 0 ns Going Low KPHHEH|tepHSIRP# VHH Setup to 6,8 100 100 400 ns CE# Going High tvpeH |tvps|Vpp Setup to CE # 5,8 100 100 100 ns Going High ltaveH itas jAddress Setup to 3 50 50 50 ns CE # Going High KDVEH |tps |Data Setup to CE# 4 60 60 60 ns Going High tELEH tcp |CE# Pulse Width 50 50 50 ns tEHDx |tpH j/Data Hold from 4 0 0 0 ns CE# High tEHAXx |taH |Address Hold 3 10 10 10 ns from CE # High tEMWH |twH |WE # Hold from CE # High 10 10 10 ns teHeEL |tcpH|CE # Pulse 10 20 30 ns Width High tEHOVI Duration of Word/Byte 2,5 6 6 6 ps Programming Operation teEHQvVe Duration of Erase 2,5,6) 0.3 0.3 0.3 s Operation (Boot) tEHOV3 Duration of Erase 2,5 0.3 0.3 0.3 s Operation (Parameter) teHOvs Duration of Erase 2,5 0.6 0.6 0.6 s Operation (Main) towt |tveH]Vpp Hold from 5,8 0 0 0 ns Valid SRD tqveH |tepHHIRP# Vi Hold 6,8 0 0 0 ns from Valid SRD tPHBR Boot-Block Relock Delay 7 100 100 100 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write pulse-width (within a longer WE # timing waveform), all set-up, hold and inactive WE # time should be measured relative to the CE# waveform. 2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics notes for WE #-Controlied Write Operations. 9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC Characteristics during Read Mode. 10. See High Speed Test Configuration. 11. See Stand: 4-134 lard Test Configuration. ADVANCE INFORMATIONa i ntel 28F200BX-T/B, 28F002BX-T/B EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS(1, 9) T28F200BX-80(10) Versions T28F002BX-80(10) Unit Symbol Parameter Notes Min Max tavav twco Write Cycle Time 80 ns tpHEL tps RP # High Recovery 220 ns to CE# Going Low tWLEL tws WE # Setup to CE# 0 ns Going Low tpHHEH tpHsS RP# Vi Setup to 6,8 100 ns CE# Going High tvPEH typs Vpp Setup to CE # 5,8 100 ns Going High tAVEH tas Address Setup to 3 60 ns CE# Going High toVEH tos Data Setup to CE# 4 60 ns Going High tELEH top CE# Pulse Width 60 ns teHpx tou Data Hold from 4 0 ns CE # High teHax taH Address Hold 3 10 ns from CE # High teHWH twH WE # Hold from CE # High 10 ns teHeEL tcpH CE# Pulse 20 ns Width High teHov1 Duration of Word/Byte 2,5 7 pS . Programming Operation teHove Duration of Erase 2,5,6 0.4 s Operation (Boot) teHav3 Duration of Erase 2,5 0.4 s Operation (Parameter) teHova Duration of Erase 2,5 0.7 s Operation (Main) towL tveH Vep Hold from 5,8 0 ns Valid SRD tavPH tpHH RP # Vip Hold 6,8 0 ns from Valid SRD tpHBR Boot-Block Relock Delay 7 100 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE # and WE # in systems where CE# defines the write pulse-width (within a longer WE # timing waveform), all set-up, hold and inactive WE # time should be measured relative to the CE# waveform. 2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics for WE #-Controlled Write Operations. 9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC Characteristics during Read Mode. 10. See Standard Test Configuration. ADVANCE INFORMATION 4-13528F200BX-T/B, 28F002BX-T/B Zi -S8Pr06e LEKKI A V/ XXX KKK K YY XX VY xX VV/ Mlle H3dAy 0? Oy XKXKXKKKKKKK KKK AORN m YY BY Wav av, YY \ Z AS"9 4 a HdA espe pe be 13Hd, W MTT ws \\\ fu \ 4% (0/0) viva Wc J / \ / -_ y Z HOM mm 7 HIAQ, HI, mn / \ / \ / \ / (3) #39 [Sn V'S'2*LADHA ___- 7 13H}, "a Wa [\. J) #0 Hl, HMH3, - +| Tay 1 Jf \ / (4) 83M Hl, XVH, HOAY, AVAY, MW SAO AAS AAXXM ARR N N OSORIO IRR sm ONVARWOD VIV0 d1Si9a A140 3SVI YO GNYNWOS WYHI4NOD 3SV3 YO GNVWNOD dflas JSY3 = ABQNYIS Ava OV3YN SLIM SNLVIS ava WVeS0dd OILVNOLNY (Wvud0ud) Viv SSINGY GITA ALtaM YO WYE90Nd ALM dN-4aMod 2% Figure 22. Alternate AC Waveforms for Write and Erase Operations (CE #-Controlled Writes) ADVANCE INFORMATION | 4-136a i ntel 28F200BX-T/B, 28F002BX-T/B ORDERING INFORMATION Lielztetrpzpofotelxt-jryspo} 4 4 OPERATING TEMPERATURE PACKAGE are SPEED (ns) T = EXTENDED TEMP = STANDARD 56 LEAD TSOP One BLANK = COMMERCIAL TEMP PA = 44 LEAD PSOP TB = 44 LEAD PSOP, EXTENDED TEMP 290448-18 Valid Combinations: E28F200BX-T60 PA28F200BX-T60 E28F200BX-B60 PA28F200BX-B60 E28F200BX-T80 PA28F200BX-T80 TE28F200BX-T80 TB28F200BX-T80 E28F2008X-B80 PA28F200BX-B80 TE28F200BX-B80 TB28F200BX-B80 EEBOGOOBROReEoo [+ To OPERATING TEMPERATURE PACKAGE Access SPEED (ns) T = EXTENDED TEMP E = STANDARD 40 LEAD TSOP 80 ne BLANK = COMMERCIAL TEMP 29044829 Valid Combinations: E28F002BX-T60 E28F002BX-B60 E28F002BX-T80 TE28F002BX-T80 28F002BX-B80 TE28F002BX-B80 ADDITIONAL INFORMATION Order Number 28F400BX/28F004BxX Datasheet 290451 28F200BXL/28F002BXL Datasheet 290449 28F400BXL./28F004BXL Datasheet 290450 AP-363 Extended Flash BIOS Design for Portable Computers 292098 ER-28 ETOX-IIl Flash Memory Technology 204012 ER-29 The Intel 2/4-Mbit Boot Biock Fiash Memory Family 294013 REVISION HISTORY Number | Description -002 Removed 70 speed bin Integrated 70 characteristics into 60 speed bin Added Extended Temperature characteristics Modified BYTE # Timing Diagram Improved tpHaqv, RP # High to Output Delay and tpye_, RP-# High Recovery to CE # going low specifications -003 PWD changed to RP # for JEDEC standardization compatibility. Combined Vcc Read current for 28F200BX Word-wide mode and Byte-wide mode, and 28F002BX Byte-wide mode in DC Characteristics tables. Change Ippg current spec from +10 pA to +15 pA in DC Characteristics tables. Improved Iccr and Iccw in DC Characteristics: Extended Temperature Operation table. improved tavav; tavav: teLav: teLav: teHaz, taHaz. tFHav and trLqz specifications for Extended Temperature Operations AC CharacteristicsRead and Write Operations. ADVANCE INFORMATION 4-137