Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08SE8 Rev. 4, 4/2015 MC9S08SE8 TBD MC9S08SE8 Series Covers: MC9S08SE8 MC9S08SE4 Features: * 8-Bit HCS08 Central Processor Unit (CPU) - 20 MHz HCS08 CPU (central processor unit) - 10 MHz internal bus frequency - HC08 instruction set with added BGND - Support for up to 32 interrupt/reset sources * On-Chip Memory - Up to 8 KB of on-chip in-circuit programmable flash memory with block protection and security options - Up to 512 bytes of on-chip RAM * Power-Saving Modes - Wait plus two stops * Clock Source Options - Oscillator (XOSC) -- Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz - Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz. * System Protection - Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock - Low voltage detection - Illegal opcode detection with reset - Illegal address detection with reset * Development Support - Single-wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging * Peripherals 28-Pin SOIC Case 751F 16-Pin TSSOP Case 948F-01 28-Pin PDIP Case 710-02 - SCI -- Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge - ADC -- 10-channel, 10-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; runs in stop3 - TPMx -- One 2-channel (TPM1) and one 1-channel (TPM2) 16-bit timer/pulse-width modulator (TPM) modules; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured for buffered, centered PWM (CPWM) on all channels - KBI -- 8-pin keyboard interrupt module - RTC -- Real-time counter with binary- or decimal-based prescaler * Input/Output - Software selectable pullups on ports when used as inputs - Software selectable slew rate control on ports when used as outputs - Software selectable drive strength on ports when used as outputs - Master reset pin and power-on reset (POR) - Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost * Package Options - 28-pin PDIP - 28-pin SOIC - 16-pin TSSOP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008-2009, 2015. All rights reserved. Table of Contents 1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .8 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .19 4 3.8 Internal Clock Source (ICS) Characteristics . . . . . . . . 3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 20 22 25 25 26 27 27 28 28 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 10/8/2008 Initial public released. 2 1/16/2009 In Table 8, added the Max. of S2IDD and S3IDD in 0-105 C; changed the Max. of S2IDD and S3IDD in 0-85 C; changed the typical of S2IDD and S3IDD; changed the S23IDDRTI to P. 3 4/7/2009 Added |IOZTOT| in the Table 7. Changed VDDAD to VDDA, VSSAD to VSSA. Updated Table 9, Table 10, Table 11, and Table 12. Updated Figure 13 and Figure 14. 4 4/10/2015 Updated Table 9. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08SE8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08SE8 Series MCU Data Sheet, Rev. 4 2 Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of the MC9S08SE8 series MCUs. HCS08 CORE BKGD/MS DEBUG MODULE (DBG) BDC CPU HCS08 SYSTEM CONTROL IRQ LVD KEYBOARD INTERRUPT MODULE (KBI) USER FLASH (MC9S08SE8 = 8192 BYTES) (MC9S08SE4 = 4096 BYTES) 2-CHANNEL TIMER/PWM MODULE (TPM1) USER RAM (MC9S08SE8 = 512 BYTES) (MC9S08SE4 = 256 BYTES) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) 20 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) KBIP7-KBIP0 TCLK PORT A COP TPM1CH1-TPM1CH0 PTA7/TPM1CH1/ADP5 PTA6/TPM1CH0/ADP4 PTA5/IRQ/TCLK/RESET PTA4/BKGD/MS PTA3/KBIP3/ADP3 PTA2/KBIP2/ADP2 PTA1/KBIP1/TPM1CH1/ADP1 PTA0/KBIP0/TPM1CH0/ADP0 PTB7/EXTAL RxD TxD PTB6/XTAL PTB5 1-CHANNEL TIMER/PWM MODULE (TPM2) TCLK TPM2CH0 PORT B IRQ REAL-TIME COUNTER (RTC) RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTB4/TPM2CH0 PTB3/KBIP7/ADP9 PTB2/KBIP6/ADP8 EXTAL PTB1/KBIP5/TxD/ADP7 PTB0/KBIP4/RxD/ADP6 XTAL PTC7 VSS PTC6 VOLTAGE REGULATOR VSSA/VREFL VDDA/VREFH VSSA VDDA VREFL VREFH PTC5 10-CHANNEL, 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) ADP9-ADP0 PORT C VDD PTC4 PTC3 PTC2 PTC1 PTC0 pins not available on 16-pin package Notes: When PTA4 is configured as BKGD, pin is bi-directional. For the 16-pin package: VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively. Figure 1. MC9S08SE8 Series Block Diagram MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 3 Pin Assignments 2 Pin Assignments This chapter shows the pin assignments in the packages available for the MC9S08SE8 series. Table 1. Pin Availability by Package Pin-Count Pin Number (Package) 1 <-- Lowest 28 (SOIC/PDIP) 16 (TSSOP) 1 -- PTC5 2 -- PTC4 3 1 PTA5 4 2 PTA4 Port Pin Priority Alt 1 IRQ --> Highest Alt 2 Alt 3 TCLK RESET BKGD MS 5 3 6 -- VDDA VDD VREFH 7 -- VSSA VREFL 8 4 VSS 9 5 PTB7 EXTAL 10 6 PTB6 XTAL 11 7 PTB5 12 8 PTB4 13 -- PTC3 14 -- PTC2 15 -- PTC1 16 -- PTC0 17 9 PTB3 KBIP7 ADP9 18 10 PTB2 KBIP6 ADP8 19 11 PTB1 KBIP5 TxD 20 12 PTB0 KBIP4 RxD TPM2CH0 ADP7 ADP6 1 21 -- PTA7 TPM1CH1 ADP5 22 -- PTA6 TPM1CH01 ADP4 23 13 PTA3 KBIP3 24 14 PTA2 KBIP2 ADP3 ADP2 1 25 15 PTA1 KBIP1 TPM1CH1 ADP1 26 16 PTA0 KBIP0 TPM1CH01 ADP0 27 -- PTC7 28 -- PTC6 TPM1 pins can be remapped to PTA7, PTA6 and PTA1,PTA0 MC9S08SE8 Series MCU Data Sheet, Rev. 4 4 Freescale Semiconductor Pin Assignments PTC5 1 28 PTC6 PTC4 2 27 PTC7 PTA5/IRQ/TCLK/RESET 3 26 PTA0/KBIP0/TPM1CH0/ADP0 PTA4/BKGD/MS 4 25 PTA1/KBIP1/TPM1CH1/ADP1 VDD 5 24 PTA2/KBIP2/ADP2 VDDA/VREFH 6 23 PTA3/KBIP3/ADP3 VSSA/VREFL 7 22 PTA6/TPM1CH0/ADP4 VSS 8 21 PTA7/TPM1CH1/ADP5 PTB7/EXTAL 9 20 PTB0/KBIP4/RxD/ADP6 PTB6/XTAL 10 19 PTB1/KBIP5/TxD/ADP7 PTB5 11 18 PTB2/KBIP6/ADP8 PTB4/TPM2CH0 12 17 PTB3/KBIP7/ADP9 PTC3 13 16 PTC0 PTC2 14 15 PTC1 Pins in bold are lost in the next lower pin count package. Figure 2. MC9S08SE8 Series in 28-Pin PDIP/SOIC Package PTA5/IRQ/TCLK/RESET 1 16 PTA0/KBIP0/TPM1CH0/ADP0 PTA4/BKGD/MS 2 15 PTA1/KBIP1/TPM1CH1/ADP1 VDD VSS 3 14 PTA2/KBIP2/ADP2 4 13 PTB7/EXTAL 5 12 PTA3/KBIP3/ADP3 PTB0/KBIP4/RxD/ADP6 PTB6/XTAL 6 11 PTB1/KBIP5/TxD/ADP7 PTB5 7 10 PTB2/KBIP6/ADP8 PTB4/TPM2CH0 8 9 PTB3/KBIP7/ADP9 Figure 3. MC9S08SE8 in 16-Pin TSSOP Package MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 5 Electrical Characteristics 3 Electrical Characteristics This chapter contains electrical and timing specifications. 3.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. MC9S08SE8 Series MCU Data Sheet, Rev. 4 6 Freescale Semiconductor Electrical Characteristics Table 3. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD -0.3 to 5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn -0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA Tstg -55 to 150 C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics Rating Symbol Value Unit TA TL to TH -40 to 85 -40 to 105 -40 to 125 C TJM 135 C Operating temperature range (packaged) C V M Maximum junction temperature Thermal resistance single-layer board 28-pin SOIC 70 28-pin PDIP 68 16-pin TSSOP 28-pin SOIC Thermal resistance four-layer board JA C/W 129 48 28-pin PDIP 49 16-pin TSSOP 85 C/W MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7 Electrical Characteristics The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) Eqn. 1 Where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user-determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.4 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions Model Human body Machine Description Symbol Value Unit Series resistance R1 1500 Storage capacitance C 100 pF Number of pulses per pin -- 3 -- Series resistance R1 0 Storage capacitance C 200 pF Number of pulses per pin -- 3 -- MC9S08SE8 Series MCU Data Sheet, Rev. 4 8 Freescale Semiconductor Electrical Characteristics Table 5. ESD and Latch-up Test Conditions (continued) Model Description Symbol Value Unit Minimum input voltage limit -- -2.5 V Maximum input voltage limit -- 7.5 V Latch-up Table 6. ESD and Latch-up Protection Characteristics Rating1 No. 1 3.5 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 -- V 2 Machine model (MM) VMM 200 -- V 3 Charge device model (CDM) VCDM 500 -- V 4 Latch-up current at TA = 125 C ILAT 100 -- mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 7. DC Characteristics Num C 1 Parameter -- Operating voltage Output high voltage -- Low drive (PTxDSn = 0) 5 V, ILoad = -2 mA 3 V, ILoad = -0.6 mA 5 V, ILoad = -0.4 mA 3 V, ILoad = -0.24 mA 2 Output high voltage -- High drive (PTxDSn = 1) 5 V, ILoad = -10 mA P 3 V, ILoad = -3 mA 5 V, ILoad = -2 mA 3 V, ILoad = -0.4 mA Output low voltage -- Low drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA 5 V, ILoad = 0.4 mA 3 V, ILoad = 0.24 mA 3 Output low voltage -- High drive (PTxDSn = 1) 5 V, ILoad = 10 mA P 3 V, ILoad = 3 mA 5 V, ILoad = 2 mA 3 V, ILoad = 0.4 mA 4 P Output high current -- Max total IOH for all ports 5V 3V Symbol Min Typical1 Max Unit -- 2.7 -- 5.5 V VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 -- -- -- -- -- -- -- -- VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 -- -- -- -- -- -- -- -- 1.5 1.5 0.8 0.8 -- -- -- -- -- -- -- -- 1.5 1.5 0.8 0.8 -- -- -- -- -- -- -- -- -- -- -- -- 100 60 VOH VOL IOHT V V mA MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 9 Electrical Characteristics Table 7. DC Characteristics (continued) Parameter Symbol Min Typical1 Max Unit Output low current -- Max total IOL for all ports 5V 3V IOLT -- -- -- -- 100 60 mA Num C 5 P 6 P Input high voltage; all digital inputs VIH 0.65 x VDD -- -- 7 P Input low voltage; all digital inputs VIL -- -- 0.35 x VDD 8 P Input hysteresis; all digital inputs Vhys 0.06 x VDD -- -- mV |IIn| -- 0.1 1 A |IOZ| -- 0.1 1 A -- -- 2 A 2 V 9 C Input leakage current; input only pins 10 P High impedance (off-state) leakage current2 11 C 12 P Internal pullup resistors3 RPU 20 45 65 k 13 P Internal pulldown resistors4 RPD 20 45 65 k -0.2 -5 -- -- 0.2 5 Total leakage combined for all inputs and Hi-Z pins |IOZTOT| -- All input only and I/O2 5, 6, 7 14 DC injection current VIN < VSS, VIN > VDD D Single pin limit Total MCU limit, includes sum of all stressed pins IIC 15 C Input capacitance; all non-supply pins CIn -- -- 8 pF 16 C RAM retention voltage VRAM 0.6 1.0 -- V VPOR 0.9 1.4 2.0 V tPOR 10 -- -- s 3.9 4.0 4.0 4.1 4.1 4.2 2.48 2.54 2.56 2.62 2.64 2.70 4.5 4.6 4.6 4.7 4.7 4.8 4.2 4.3 4.3 4.4 4.4 4.5 2.84 2.90 2.92 2.98 3.00 3.06 2.66 2.72 2.74 2.80 2.82 2.88 17 P POR re-arm voltage 18 D POR re-arm time 19 20 21 22 23 24 P P C P P C 8 Low-voltage detection threshold -- high range VDD falling VDD rising Low-voltage detection threshold -- low range VDD falling VDD rising Low-voltage warning threshold -- high range 1 VDD falling VDD rising Low-voltage warning threshold -- high range 0 VDD falling VDD rising Low-voltage warning threshold low range 1 VDD falling VDD rising Low-voltage warning threshold -- low range 0 VDD falling VDD rising VLVD1 VLVD0 VLVW3 VLVW2 VLVW1 VLVW0 mA V V V V V V MC9S08SE8 Series MCU Data Sheet, Rev. 4 10 Freescale Semiconductor Electrical Characteristics Table 7. DC Characteristics (continued) Num C Parameter Symbol Min Typical1 Max Unit Vhys -- -- 100 60 -- -- mV VBG 1.18 1.20 1.21 V Low-voltage inhibit reset/recover hysteresis 1 2 3 4 5 6 7 8 9 25 T 5V 3V 26 P Bandgap voltage reference9 Typical values are measured at 25 C. Characterized, not tested. Measured with VIn = VDD or VSS. Measured with VIn = VSS. Measured with VIn = VDD. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 5.0 V, Temp = 25 C. MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 11 Electrical Characteristics VOL vs IOL at VDD = 5.0 V, High Drive 700 -40C 600 0C 25C VDD/mV 500 70C 400 95C 300 125C 135C 200 100 0 1 1.5 2 2.5 3 9 9.5 10 10.5 11 IOL/mA Figure 4. Typical VOL vs. IOL for High Drive Enabled Pad (VDD = 5 V) VOL vs IOL at VDD = 3.0 V, High Drive 350 -40C 300 0C VDD/mV 250 25C 200 70C 150 95C 100 125C 50 135C 0 0.2 0.3 0.4 0.5 0.6 2 2.5 3 3.5 4 IOL/mA Figure 5. Typical VOL vs. IOL for High Drive Enabled Pad (VDD = 3 V) MC9S08SE8 Series MCU Data Sheet, Rev. 4 12 Freescale Semiconductor Electrical Characteristics VOL vs IOL at VDD = 5.0 V, Low Drive 600 -40C 0C 500 25C VDD/mV 400 70C 95C 300 125C 200 135C 100 0 0.2 0.3 0.4 0.5 0.6 1 1.5 2 2.5 3 IOL/mA Figure 6. Typical VOL vs. IOL for Low Drive Enabled Pad (VDD = 5 V) VOL vs IOL at VDD = 3.0 V, Low Drive 250 -40C 0C 200 VDD/mV 25C 70C 150 95C 125C 100 135C 50 0 160 200 240 280 320 400 500 600 700 800 IOL/mA Figure 7. Typical VOL vs. IOL for Low Drive Enabled Pad (VDD = 3 V) MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 13 Electrical Characteristics VOH vs IOH at VDD = 5.0 V, High Drive 5.1 -40C 5 0C 4.9 25C VOH/mV 4.8 4.7 70C 4.6 95C 4.5 125C 4.4 135C 4.3 4.2 4.1 -1 -1.5 -2 -2.5 -3 -9 -9.5 -10 -10.5 -11 IOH/mA Figure 8. Typical VOH vs. IOH for High Drive Enabled Pad (VDD = 5 V) VOH vs IOL at VDD = 3.0 V, High Drive 3.05 -40C VOH/mV 3 2.95 0C 2.9 25C 2.85 70C 2.8 95C 2.75 125C 2.7 135C 2.65 2.6 2.55 2.5 -200 -300 -400 -500 -600 -2 -2.5 -3 -3.5 -4 IOH/mA Figure 9. Typical VOH vs. IOH for High Drive Enabled Pad (VDD = 3 V) MC9S08SE8 Series MCU Data Sheet, Rev. 4 14 Freescale Semiconductor Electrical Characteristics VOH vs IOH at VDD = 5.0 V, Low Drive 5.2 -40C 5 0C 25C VOH/mV 4.8 70C 4.6 95C 4.4 125C 4.2 135C 4 3.8 -200 -300 -400 -500 -600 -1 -1.5 -2 -2.5 -3 IOH/mA Figure 10. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 5 V) VOH vs IOH at VDD = 3.0 V, Low Drive 3 -40C 2.95 0C 2.9 25C VOH/mV 2.85 70C 2.8 95C 2.75 125C 2.7 135C 2.65 2.6 2.55 -160 -200 -240 -280 -320 -400 -500 -600 -700 -800 IOH/mA Figure 11. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 3 V) 3.6 Supply Current Characteristics This section includes information about power supply current in various operating modes. MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 15 Electrical Characteristics Table 8. Supply Current Characteristics Num C Parameter 1 C Run supply current measured at (CPU clock = 4 MHz, fBus = 2 MHz) 2 P Run supply current measured at (CPU clock = 20 MHz, fBus = 10 MHz) 3 P Wait supply current measured at fBus = 2 MHz Symbol 2 RIDD 2 RIDD 2 WIDD Unit Temp (C) mA -40 to 125 mA -40 to 125 mA -40 to 125 19 28 45.8 A -40 to 85 -40 to 105 -40 to 125 1.3 15 22 37.2 A -40 to 85 -40 to 105 -40 to 125 1.61 23 43 76.1 A -40 to 85 -40 to 105 -40 to 125 1.44 19 38 66.4 A -40 to 85 -40 to 105 -40 to 125 5 300 500 500 nA -40 to 85 -40 to 125 3 300 500 500 nA -40 to 85 -40 to 125 5 122 180 A -40 to 125 3 110 160 A -40 to 125 5,3 5 8 A -40 to 125 VDD (V) Typical1 Max 5 2.4 2.72 3 2.18 2.26 5 6.35 7.29 3 5.79 6.42 5 1.4 1.56 3 1.36 1.53 1.4 5 4 P Stop2 mode supply current S2IDD 3 5 5 P Stop3 mode supply current S3IDD 3 6 P RTC adder to stop2 or stop33 S23IDDRTI 7 C LVD adder to stop3 (LVDE = LVDSE = 1) S3IDDLVD 8 C Adder to stop3 for oscillator enabled4 (OSCSTEN =1) S3IDDOSC 1 Typical values are based on characterization data at 25 C unless otherwise stated. See Figure 12 through Figure 13 for typical curves across voltage/temperature. 2 All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins. 3 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 220 A at 5 V with fBus = 1 MHz. 4 Values given under the following conditions: low range operation (RANGE = 0) with a 32.768 kHz crystal and low power mode (HGO = 0). MC9S08SE8 Series MCU Data Sheet, Rev. 4 16 Freescale Semiconductor Electrical Characteristics Run IDD at 10 MHz vs Temp 8 7 6 RIDD (mA) 5.5V 5 5.0V 4.5V 4 3.3V 3.0V 3 2.7V 2 1 0 -40C 0C 25C 70C 95C 125C 135C Temp (C) Figure 12. Typical Run IDD Curves Stop2 IDD vs Temp 20 18 S2IDD (uA) 16 14 5.5V 12 5.0V 4.5V 10 3.3V 8 3.0V 2.7V 6 4 2 0 -40C 0C 25C 70C 95C 125C 135C Temp (C) Figure 13. Typical Stop2 IDD Curves MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 17 Electrical Characteristics Stop3 IDD vs Temp 35 30 S3IDD (uA) 25 5.5V 5.0V 20 4.5V 3.3V 15 3.0V 2.7V 10 5 0 -40C 0C 25C 70C 95C 125C 135C Temp (C) Figure 14. Typical Stop3 IDD Curves 3.7 External Oscillator (XOSC) Characteristics Table 9. Oscillator electrical specifications (Temperature Range = -40 to 125C Ambient) Num 1 C Characteristic Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1)2 High range (RANGE = 1), low power (HGO = 0)2 2 3 -- Load capacitors -- -- Symbol Min. flo 32 1 1 fhi-hgo fhi-lp C1,C2 Feedback resistor Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) 4 High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz RF RS Typical1 Max. -- -- -- 38.4 16 8 Unit kHz MHz MHz See crystal or resonator manufacturer's recommendation -- -- 10 1 -- -- -- -- -- 0 100 0 -- -- -- M k -- -- -- 0 0 0 0 10 20 MC9S08SE8 Series MCU Data Sheet, Rev. 4 18 Freescale Semiconductor Electrical Characteristics Table 9. Oscillator electrical specifications (Temperature Range = -40 to 125C Ambient) Num C 5 T 6 T Characteristic Crystal start-up time3 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)4 High range, high gain (RANGE = 1, HGO = 1)4 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode 2 Typical1 Max. Symbol Min. t CSTL-LP t CSTH-HGO t CSTH-LP t CSTH-HGO -- -- -- -- 200 400 5 15 -- -- -- -- ms fextal 0.03125 0 -- -- 20 20 MHz MHz FBELP mode Unit Typical column was characterized at 5.0 V, 25 C or is recommended value. The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized by the crystal manufacturer. 4 4 MHz crystal. 1 2 XOSCVLP EXTAL XTAL RF C1 RS Crystal or Resonator C2 Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 19 Electrical Characteristics 3.8 Internal Clock Source (ICS) Characteristics Table 10. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient) Symbol Min. Typical1 Max. Unit Average internal reference frequency -- factory trimmed at VDD = 5 V and temperature = 25 C fint_t -- 39.0625 -- kHz P Internal reference frequency -- user trimmed fint_ut 31.25 -- 39.06 kHz 3 T Internal reference start-up time tIRST -- 60 100 s 4 D DCO output frequency range -- trimmed2 fdco_t 16 -- 20 MHz 5 2 D DCO output frequency Reference = 32768 Hz and DMX32 = 1 fdco_DMX32 -- 59.77 -- MHz 6 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) fdco_res_t -- 0.1 0.2 %fdco 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) fdco_res_t -- 0.2 0.4 %fdco 8 Total deviation of DCO output from trimmed frequency3 C Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 C fdco_t -- -1.0 to 0.5 0.5 2 1 %fdco 10 C FLL acquisition time4 tAcquire -- -- 1 ms 11 C CJitter -- 0.02 0.2 %fdco Num C 1 P 2 Characteristic Low range (DRS = 00) Long term jitter of DCO output clock (averaged over 2-ms interval)5 1 Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device. 4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 2 MC9S08SE8 Series MCU Data Sheet, Rev. 4 20 Freescale Semiconductor Electrical Characteristics 1.00% 0.50% Deviation (%) 0.00% -60 -40 -20 0 20 40 60 80 100 120 -0.50% -1.00% TBD -1.50% -2.00% Temperature Figure 17. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) 3.9 ADC Characteristics Table 11. 10-Bit ADC Operating Conditions Symb Min Typ1 Max Unit Absolute VDDA 2.7 -- 5.5 V Delta to VDD (VDD - VDDA)2 VDDA -100 0 100 mV Delta to VSS (VSS - VSSA)2 VSSA -100 0 100 mV Input voltage VADIN VREFL -- VREFH V Input capacitance CADIN -- 4.5 5.5 pF Input resistance RADIN -- 3 5 k RAS -- -- -- -- 5 10 k -- -- 10 0.4 -- 8.0 0.4 -- 4.0 Characteristic Supply voltage Ground voltage Analog source resistance Conditions 10-bit mode fADCK > 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK) ADC conversion clock frequency High speed (ADLPC = 0) Low power (ADLPC = 1) fADCK Comment External to MCU MHz MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 21 Electrical Characteristics 1 Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS + - - CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 18. ADC Input Impedance Equivalency Diagram Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) C Symb Min Typ1 Max Unit Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 T IDDA -- 133 -- A Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 T IDDA -- 218 -- A Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 T IDDA -- 327 -- A Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 D IDDA -- 0.582 1 mA D IDDA -- 0.011 1 A Characteristic Supply Current Conditions Stop, Reset, Module Off Comment MC9S08SE8 Series MCU Data Sheet, Rev. 4 22 Freescale Semiconductor Electrical Characteristics Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Characteristic ADC Asynchronous Clock Source Conversion Time (Including sample time) Sample Time Conditions C Symb D fADACK High Speed (ADLPC = 0) Low Power (ADLPC = 1) Short Sample (ADLSMP = 0) D D Temp Sensor Voltage -40C- 25C D D 2 3.3 5 1.25 2 3.3 -- 20 -- -- 40 -- -- 3.5 -- -- 23.5 -- -- 3.266 -- -- 3.638 -- -- 1.396 -- -- 1 2.5 -- 0.5 1.0 -- 0.5 1.0 -- 0.3 0.5 -- 0.5 1.0 -- 0.3 0.5 -- 0.5 1.5 -- 0.5 0.5 -- 0.5 1 -- 0.5 0.5 -- -- 0.5 -- -- 0.5 -- 0.2 2.5 -- 0.1 1 -- 1.5 3.5 0.7 1.5 m 25C- 125C 25C Max tADS Long Sample (ADLSMP = 1) Temp Sensor Slope Typ1 tADC Long Sample (ADLSMP = 1) Short Sample (ADLSMP = 0) Min VTEMP25 Unit Comment MHz tADACK = 1/fADACK ADCK cycles ADCK cycles See SE8 reference manual for conversion time variances mV/C mV Characteristics for 28-pin packages only Total Unadjusted Error Differential Non-Linearity Integral Non-Linearity 10-bit mode P 8-bit mode P 10-bit mode2 P DNL mode3 P 10-bit mode T 8-bit ETUE INL 8-bit mode T Zero-Scale Error 10-bit mode P 8-bit mode P Full-Scale Error 10-bit mode T Quantization Error 10-bit mode Input Leakage Error 10-bit mode 8-bit mode T D 8-bit mode D 8-bit mode EZS EFS EQ EIL LSB3 Includes quantization LSB3 LSB3 LSB3 VADIN = VSSA LSB3 VADIN = VDDA LSB3 LSB3 Pad leakage4 * RAS LSB3 Includes quantization Characteristics for 16-pin package only Total Unadjusted Error 10-bit mode 8-bit mode P P ETUE -- MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 23 Electrical Characteristics Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Characteristic Differential Non-Linearity Integral Non-Linearity Conditions 10-bit mode3 C P Min Typ1 Max -- 0.5 1.0 -- 0.3 0.5 -- 0.5 1.0 -- 0.3 0.5 -- 1.5 2.1 -- 0.5 0.7 -- 1 1.5 -- 0.5 0.5 -- -- 0.5 -- -- 0.5 -- 0.2 2.5 -- 0.1 1 DNL mode3 P 10-bit mode T 8-bit Symb INL 8-bit mode T Zero-Scale Error 10-bit mode P 8-bit mode P Full-Scale Error 10-bit mode T Quantization Error 10-bit mode Input Leakage Error 10-bit mode 8-bit mode T D 8-bit mode D 8-bit mode EZS EFS EQ EIL Unit Comment LSB3 LSB3 LSB3 VADIN = VSSA LSB3 VADIN = VDDA LSB3 LSB3 Pad leakage4 * RAS 1 Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes 3 1 LSB =(V N REFH - VREFL)/2 4 Based on input pad leakage current. Refer to pad electricals. MC9S08SE8 Series MCU Data Sheet, Rev. 4 24 Freescale Semiconductor Electrical Characteristics 3.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. 3.10.1 Control Timing Table 13. Control Timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus DC -- 10 MHz D Internal low power oscillator period tLPO 700 -- 1300 s D External reset pulse width2 textrst 100 -- -- ns 4 D Reset low drive3 trstdrv 34 x tcyc -- -- ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 -- -- ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes4 tMSH 100 -- -- s 7 D IRQ pulse width Asynchronous path2 Synchronous path5 tILIH, tIHIL 100 1.5 x tcyc -- -- 8 D Pin interrupt pulse width Asynchronous path2 Synchronous path5 tILIH, tIHIL 100 1.5 x tcyc -- -- Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall -- Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall -- Num C 1 D 2 3 9 1 2 3 4 5 6 Rating 40 75 ns ns -- ns -- ns C 11 35 Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of tcyc. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 C to 125 C. textrst RESET PIN Figure 19. Reset Timing MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 25 Electrical Characteristics tIHIL IRQ/Pin Interrupts IRQ/Pin Interrupts tILIH Figure 20. IRQ/Pin Interrupt Timing 3.10.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing Num C 1 D 2 Rating Symbol Min Max Unit External clock frequency fTPMext DC fBus/4 MHz D External clock period tTPMext 4 -- tcyc 3 D External clock high time tclkh 1.5 -- tcyc 4 D External clock low time tclkl 1.5 -- tcyc 5 D Input capture pulse width tICPW 1.5 -- tcyc tTCLK tclkh TCLK tclkl Figure 21. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 22. Timer Input Capture Pulse MC9S08SE8 Series MCU Data Sheet, Rev. 4 26 Freescale Semiconductor Ordering Information 3.11 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section in the reference manual. Table 15. Flash Characteristics Num C 1 D 2 D Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase Vprog/erase 2.7 -- 5.5 V Supply voltage for read operation VRead 2.7 -- 5.5 V fFCLK 150 -- 200 kHz tFcyc 5 -- 6.67 s 1 3 D Internal FCLK frequency 4 D Internal FCLK period (1/FCLK) 5 6 7 8 P P P P Byte program time (random Byte program time (burst location)2 mode)2 tprog 9 tFcyc tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time2 tMass 20,000 tFcyc endurance3 9 C Program/erase TL to TH = -40 C to 125 C T = 25 C nFLPE 10,000 -- 100,000 -- cycles 10 C Data retention4 tD_ret 15 100 -- years 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2 4 Ordering Information This chapter contains ordering information for the device numbering system. Example of the device numbering system: MC 9 S08 SE 8 C XX E Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family RoHS compliance indicator (E = yes) Package designator (see Table 16) Temperature range (C = -40 C to 85 C) (V = -40 C to 105 C) (M = -40 C to 125 C) Memory Size (in KB) MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 27 Ordering Information 4.1 Package Information Table 16. Package Descriptions Pin Count 28 4.2 Package Type Plastic Dual In-line Pin 28 Small Outline Integrated Circuit 16 Thin Shrink Small Outline Package Abbreviation Designator Case No. Document No. PDIP RL 710 98ASB42390B SOIC WL 751F 98ASB42345B TSSOP TG 948F 98ASH70247A Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 16. MC9S08SE8 Series MCU Data Sheet, Rev. 4 28 Freescale Semiconductor Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 29 Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 30 Freescale Semiconductor Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 31 Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 32 Freescale Semiconductor Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 33 Ordering Information MC9S08SE8 Series MCU Data Sheet, Rev. 4 34 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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