AD S5 220 ADS5220 SBAS261D - APRIL 2003 - REVISED JUNE 2007 12-Bit, 40MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER FEATURES * * * * * * * * * DESCRIPTION HIGH SNR: 70dB HIGH SFDR: 88dBFS LOW POWER: 195mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR FULLY DIFFERENTIAL ANALOG INPUT PROGRAMMABLE INPUT RANGE LOW DNL: 0.3LSB SINGLE +3.3V SUPPLY OPERATION TQFP-48 PACKAGE APPLICATIONS * * * * WIRELESS LOCAL LOOP COMMUNICATIONS MEDICAL IMAGING PORTABLE INSTRUMENTATION The ADS5220 is a pipeline, CMOS analog-to-digital converter (ADC) that operates from a single +3.3V power supply. This converter can be operated with a single-ended input or differential input. The ADS5220 includes a 12-bit quantizer, high bandwidth track-and-hold, and an internal reference. It also allows the user to disable the internal reference and utilize external references which provide excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required. The ADS5220 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS5220 offers power dissipation of 195mW and also provides two power-down modes. The ADS5220 is specified at a maximum sampling frequency of 40MSPS and a differential input range of 1V to 2V. The ADS5220 is available in a TQFP-48 package. AVDD CLK VDRV ADS5220 Timing/Duty Cycle Adjust Circuitry IN VIN S/H IN 12-Bit Pipelined ADC Error Correction Logic 3-State Output D0 D11 OVR Internal Reference STPD QPD REFT REFB RSEL VREF OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2007, Texas Instruments Incorporated ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS5220 TQFP-48 PFB -40C to +85C ADS5220PFB ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5220PFBT Tape and Reel, 250 ADS5220PFBR Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). AVDD, DVDD, VDRV UNIT +3.8 V Analog input -0.3V to (+VS + 0.3) V Logic input -0.3V to (+VS + 0.3) V Case temperature +100 C Junction temperature, TJ +150 C Storage temperature +150 C (1) 2 ADS5220 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS: AVDD = +3.3V TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5220 PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE Ambient air TYP MAX UNIT 12 Tested Bits -40 to +85 C ANALOG INPUT Single-Ended Input Range 2VPP 0.5 2.5 V Optional Single-Ended Input Range 1VPP 1 2 V Differential Input Range 2VPP 1 Input Impedance Analog Input Bandwidth 2 V 1 A Static, no clock 1.25 || 5 M || pF -3dBFS input 300 MHz Analog Input Bias Current CONVERSION CHARACTERISTICS Sample Rate 1M Data Latency Clock Duty Cycle Mode select enabled 40M Samples/s 4.5 Clock cycles 35 to 65 % DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 2.4MHz 0.3 f = 9.7MHz 0.35 No Missing Codes LSB LSB Tested 0.7 Integral Nonlinearity Error, f = 2.4MHz Spurious-Free Dynamic Range (1) 0.75 1.5 LSBs Referred to full-scale f = 2.4MHz f = 9.7MHz 83 f = 19.8MHz 88 dBFS (2) 88 dBFS 76 dBFS 86.3 dBc 70 dBFS 70 dBFS 69 dBFS 69 dBFS 69 dBFS 68 dBFS 11.2 Bits 0.3 LSBRMS 2-Tone Intermodulation Distortion (3) f = 9.5MHz and 10.5MHz (-7dB each tone) Signal-to-Noise Ratio (SNR) Referred to full-scale f = 2.4MHz f = 9.7MHz 68.5 f = 19.8MHz Signal-to-(Noise + Distortion) (SINAD) Referred to full-scale f = 2.4MH f = 9.7MHz 68 f = 19.8MHz Effective Number of Bits (4), f = 2.4MHz Output Noise Input Tied to Common-Mode Aperture Delay Time 3.0 ns Aperture Jitter 1.2 psRMS Over-Voltage Recovery Time 1.0 Clock Cycle Full-Scale Step Acquisition Time 5.0 ns (1) (2) (3) (4) Spurious-free dynamic range refers to the magnitude of the largest harmonic. dBFS means dB relative to Full-Scale. Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. Effective Number of Bits (ENOB) is defined by (SINAD - 1.76) / 6.02. Submit Documentation Feedback 3 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS: AVDD = +3.3V (continued) TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. ADS5220 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS Logic Family Convert Command CMOS-compatible Start conversion Rising edge of Convert clock High-Level Input Current (5) (VIN = 3VDD) Low-Level Input Current (VIN = 0V) High-Level Input Voltage 100 A 10 A +1.7 V Low-Level Input Voltage +0.7 Input Capacitance 5 V pF DIGITAL OUTPUTS Logic Family CMOS-compatible Logic Coding Straight Offset Binary or BTC Low Output Voltage (IOL = 50A to 1.5mA) High Output Voltage (IOH = 50A to 0.5mA) +0.1 V ns +2.4 V 3-State Enable Time 20 40 3-State Disable Time 2 10 Output Capacitance 5 ns pF ACCURACY (Internal Reference, 2VPP, unless otherwise noted) Zero Error (referred to midscale) Zero Error Drift (referred to midscale) fIN = 2.4MHz, at 25C 0.75 fIN = 2.4MHz 5 at 25C 0.4 Gain Error (6) Gain Error Drift 1.5 %FS ppm/C 3.0 %FS 38 ppm/C 52 dB Output Voltage Error (1V) 10 mV Load Regulation at 1mA 0.15 % Output Voltage Error (0.5V) 5 mV Load Regulation at 0.5mA 0.1 % Power-Supply Rejection of Gain VS = 5% INTERNAL VOLTAGE REFERENCE POWER-SUPPLY REQUIREMENTS Supply Voltage: AVDD, DVDD Operating Driver Supply Voltage Supply Current: +IS Operating (External reference) +3.0 +3.3 +3.6 +2.3 +2.5 +3.6 59 V V mA Power Dissipation: VDRV = 2.5V 195 215 mW VDRV = 3.3V 200 mW Standard Power-Down 15 mW Quasi-Power-Down 75 mW TQFP-48 63.7 C/W QFN-48 26.1 C/W Thermal Resistance, JA (5) (6) 4 A 50k pull-down resistor is inserted internally on the OE pin. Includes internal reference. Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 PIN CONFIGURATION DVDD DVDD CLK DGND DGND DGND IN IN AGND AGND AGND AVDD PFB PACKAGE TQFP-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 MSBI 1 36 AVDD OE 2 35 NC Mode Select 3 34 REFT STPD 4 33 NC QPD 5 32 REFB GDRV 6 31 RSEL GDRV 7 30 VREF VDRV 8 29 AGND VDRV 9 28 AGND D11 (MSB) 10 27 AGND D10 11 26 NC D9 12 25 NC 13 14 15 16 17 18 19 20 21 22 23 24 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) NC NC OVR ADS5220 PIN ASSIGNMENTS PIN NO. NAME 1 MSBI I/O DESCRIPTION Most Significant Bit Invert (HI = Binary Two's Complement, LO = Straight Offset Binary) 2 OE 3 Mode Select Tri-State (LO = Enabled, HI = Tri-State) Duty Cycle Stablilizer (HI = Enabled, LO = Normal Operation) 4 STPD Standard Power Down (LO = Normal Operation, HI = Enabled) 5 QPD Quasi Power Down (LO = Normal Operation, HI = Enabled) 6 GDRV Output Driver Ground 7 GDRV Output Driver Ground 8 VDRV Output Driver Supply 9 VDRV 10 D11 (MSB) O Output Driver Supply Data Bit 12 11 D10 O Data Bit 11 12 D9 O Data Bit 10 13 D8 O Data Bit 9 14 D7 O Data Bit 8 15 D6 O Data Bit 7 16 D5 O Data Bit 6 17 D4 O Data Bit 5 18 D3 O Data Bit 4 19 D2 O Data Bit 3 Submit Documentation Feedback 5 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 PIN ASSIGNMENTS (continued) PIN 6 NO. NAME I/O DESCRIPTION 20 D1 O Data Bit 2 21 D0 (LSB) O Data Bit 1 22 NC No internal connection 23 NC No internal connection 24 OVR Over-Range Indicator 25 NC No internal connection 26 NC No internal connection 27 AGND Analog Ground 28 AGND Analog Ground 29 AGND Analog Ground 30 VREF Internal Voltage Reference (1/2V Reference) 31 RSEL Reference Mode Select (see Table 1 for settings) 32 REFB Bottom Reference Bypass 33 NC No internal connection 34 REFT Top Reference Bypass 35 NC No internal connection 36 AVDD Analog Supply 37 AVDD Analog Supply 38 AGND Analog Ground 39 AGND Analog Ground 40 AGND 41 IN I Analog Input 42 IN I Complementary Analog Input 43 DGND Digital Ground 44 DGND Digital Ground 45 DGND 46 CLK I Convert Clock Input 47 DVDD I Digital Supply 48 DVDD I Digital Supply Analog Ground Digital Ground Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 TIMING DIAGRAM N+2 N+1 Analog In N+3 N tCONV tD tL N+4 N+5 N+6 N+7 tH Clock 4.5 Clock Cycles t2 Data Out N-5 N-4 N-3 N-2 N-1 N N+1 N+2 t1 Data Invalid TIMING CHARACTERISTICS SYMBOL DESCRIPTION MIN TYP 25 MAX UNIT 1000 ns tCONV Convert Clock Period tL Clock Pulse LOW 8.75 12.5 ns tH Clock Pulse HIGH 8.75 12.5 ns tD Aperture Delay 3 ns t1 New Data Delay Time, CL = 0pF t2 New Data Delay Time, CL = 15pF max 3.9 Submit Documentation Feedback ns 12 ns 7 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 TYPICAL CHARACTERISTICS: AVDD = 3.3V TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2VPP) SPECTRAL PERFORMANCE (Differential, 2VPP) 0 0 fIN = 2.4MHz (-1dBFS) SFDR = 88.2dBFS SNR = 70.0dBFS SINAD = 69.9dBFS -20 Amplitude (dB) Amplitude (dB) -20 -40 -60 -80 -100 2 4 6 8 10 12 14 16 18 -80 20 0 2 4 6 8 10 12 14 16 Frequency (MHz) Frequency (MHz) Figure 1. Figure 2. SPECTRAL PERFORMANCE EXTERNAL REFERENCE (Differential, 2VPP) SPECTRAL PERFORMANCE PROGRAMMED REFERENCE (Differential, 1.5VPP) 0 18 20 0 fIN = 9.7MHz (-1dBFS) SFDR = 88.7dBFS SNR = 69.3dBFS SINAD = 69.1dBFS fIN = 2.4MHz (-1dBFS) SFDR = 88.8dBFS SNR = 70.0dBFS SINAD = 70.0dBFS -20 Amplitude (dB) -20 Amplitude (dB) -60 -120 0 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 Frequency (MHz) Frequency (MHz) Figure 3. Figure 4. SPECTRAL PERFORMANCE (Differential, 1VPP) SPECTRAL PERFORMANCE (Single-Ended, 1VPP) 0 18 20 0 fIN = 9.7MHz (-1dBFS) SFDR = 84.9dBFS SNR = 67.4dBFS SINAD = 67.3dBFS fIN = 9.7MHz (-1dBFS) SFDR = 84.0dBFS SNR = 67.1dBFS SINAD = 66.9dBFS -20 Amplitude (dB) -20 Amplitude (dB) -40 -100 -120 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 8 fIN = 9.7MHz (-1dBFS) SFDR = 88.4dBFS SNR = 69.8dBFS SINAD = 69.7dBFS 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 Frequency (MHz) Frequency (MHz) Figure 5. Figure 6. Submit Documentation Feedback 14 16 18 20 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 TYPICAL CHARACTERISTICS: AVDD = 3.3V (continued) TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SPECTRAL PERFORMANCE (Single-Ended, 2VPP) TWO-TONE INTERMODULATION DISTORTION 0 0 fIN = 9.7MHz (-1dBFS) SFDR = 80.2dBFS SNR = 69.6dBFS SINAD = 69.1dBFS -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 2 4 6 8 10 12 14 16 20 18 0 4 6 8 10 12 14 16 Frequency (MHz) Figure 7. Figure 8. INTEGRAL LINEARITY ERROR INTEGRAL LINEARITY ERROR EXTERNAL REFERENCE 1.0 fIN = 9.7MHz 0.8 0.6 0.4 0.4 ILE (LSB) 0.6 0.2 0 -0.2 20 18 fIN = 9.7MHz 0.8 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1024 2048 3072 4096 0 1024 2048 Code Code Figure 9. Figure 10. DIFFERENTIAL LINEARITY ERROR EXTERNAL REFERENCE 1.0 3072 4096 DIFFERENTIAL LINEARITY ERROR 1.0 fIN = 9.7MHz 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 fIN = 9.7MHz 0.8 DLE (LSB) DLE (LSB) 2 Frequency (MHz) 1.0 ILE (LSB) fIN = 9.5MHz (-7dBFS) fIN = 10.5MHz (-7dBFS) SFDR = 93.3dBFS -20 Amplitude (dB) Amplitude (dB) -20 -1.0 0 1024 2048 3072 4096 0 1024 2048 Code Code Figure 11. Figure 12. Submit Documentation Feedback 3072 4096 9 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 TYPICAL CHARACTERISTICS: AVDD = 3.3V (continued) TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. SFDR/SNR vs CLOCK DUTY CYCLE (DCA = Duty Cycle Adjust) SWEPT POWER (SNR) EXTERNAL REFERENCE 90 80 SFDR: DCA on dBFS 60 SNR (dBc, dBFS) SFDR, SNR (dBFS) 80 70 SFDR: DCA off 70 60 SNR: DCA off SNR: DCA on 50 50 40 30 20 10 dBc 0 40 -10 30 fIN = 9.7MHz -20 30 35 40 45 50 55 60 70 65 -80 -60 -50 -20 Figure 14. 0 -10 SNR, SFDR vs INPUT FREQUENCY 90 90 85 SNR, SFDR (dBFS) dBFS 80 70 60 50 40 30 dBc 10 SFDR 75 70 65 SNR 60 50 fIN = 9.7MHz 0 -80 80 55 20 -70 -60 -50 -40 -30 -20 45 0 -10 1 100 10 Analog Input Level (dBFS) Frequency (MHz) Figure 15. Figure 16. DYNAMIC PERFORMANCE vs TEMPERATURE 95 DYNAMIC PERFORMANCE vs TEMPERATURE 95 fIN = 2.4MHz fIN = 9.7MHz 90 90 85 SFDR, SNR (dBFS) SFDR, SNR (dBFS) -30 Figure 13. SWEPT POWER (SFDR) SFDR 80 75 70 65 SNR 85 SFDR 80 75 70 60 65 55 60 SNR -50 10 -40 Analog Input Level (dBFS) 100 SFDR (dBc, dBFS) -70 Duty Cycle (%) -25 0 25 50 75 100 -50 -25 0 25 50 Temperature (C) Temperature (C) Figure 17. Figure 18. Submit Documentation Feedback 75 100 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 TYPICAL CHARACTERISTICS: AVDD = 3.3V (continued) TMIN = -40C, TMAX = +85C. Typical values are at TA = +25C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, -1dBFS, DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted. OUTPUT NOISE HISTOGRAM (DC Output) 60000 Counts 50000 40000 30000 20000 10000 0 N-2 N-1 N N+1 N+2 Code Figure 19. APPLICATION INFORMATION THEORY OF OPERATION The ADS5220 is a 12-bit, 40MSPS, CMOS ADC designed with a fully differential pipeline architecture. The pipeline consists of three sections: a 3-bit quantizer, seven stages with a 1.5-bit quantizer for each stage, and a 4-bit flash. The output of each pipeline stage is processed and formed into 12-bit data in the digital error correction logic section to ensure good differential linearity of the ADC. The converter includes a high bandwidth track-and-hold amplifier in the input stage as shown in Figure 20. The falling edge of the input clock initiates the conversion process. Once the signal is captured by the input track-and-hold, the bits are sequentially encoded starting with the Most Significant Bit (MSB). This process results in a data latency of 4.5 clock cycles . The ADS5220 includes a high accuracy internal reference and also allows the use of an external reference. The input full-scale range is up to 2VPP and is selectable based on the reference voltage setting. For normal operation, both analog inputs (IN, IN) require an external common-mode voltage as a bias. The output data of the ADS5220 are available as a 12-bit parallel word, either coded in a Straight Offset Binary or Binary Two's Complement format. The ADS5220 includes an on-chip duty-cycle adjust (DCA) circuit, controlled through the state of the Mode Select pin (3). When activated, this duty-cycle adjust circuit can accommodate for an incoming clock duty-cycle range of 35% to 65%, and re-time it to a 50% duty-cycle, which allows for optimum internal clock timing. The ADS5220 has low power dissipation in normal mode and has two power-down modes. The device operates from a single +3.3V power supply and has a separate digital output driver supply pin. S5 S3 VBIAS S1 CIN S2 CIN IN T&H IN S4 S6 VBIAS Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open Hold Phase: S1, S2, S3, S4 open; S5, S6 closed Figure 20. Simplified Circuit of Input Track-and-Hold Amplifier of ADS5220 Submit Documentation Feedback 11 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 ANALOG INPUT Depending on the application and the desired level of performance, the analog input of the ADS5220 can be configured in various ways and driven with different circuits. In any case, the analog interface requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency band and amplitude, as well as the available power supplies. and requires an external common-mode voltage. This configuration allows a symmetrical signal swing while maintaining sufficient headroom to the supply rails. The common-mode voltage can be generated from an external DC voltage source (for example, an analog +3.3V supply with a simple resistor divider), or from the input signal source with DC-coupling. For a single-ended input configuration, the common-mode voltage is typically +1.25V. When the input configuration is differential, the common-mode voltage is +1.5V. INPUT IMPEDANCE INPUT FULL-SCALE RANGE The input impedance of the ADS5220 is capacitive due to the input stray and sampling capacitors. These capacitors effectively result in a dynamic input impedance that is a function of the sampling and input frequency. Figure 21 depicts the differential input impedance of the ADS5220 as a function of the signal input frequency. For applications that use op amps to drive the ADC, it is recommended that a series resistor be added between the amplifier output and the converter inputs. This additional resistor isolates the capacitive input of the converter from the driving source and avoid gain peaking, or instability; furthermore, it creates a 1st-order, low-pass filter (LPF) in conjunction with the specified input capacitance of the ADS5220. The cutoff frequency of this LPF can be further adjusted by adding an external shunt capacitor. In any case, the use of the RC network is optional, but optimizing the values to adapt to the specific application is encouraged. The input full-scale range (FSR) of the ADS5220 is selectable from 1VPP to 2VPP and any value within this range, by the configuration of the reference select pin RSEL and the reference voltage pin VREF (see Table 1). The input FSR (differential) is always twice VREF (the voltage at the VREF pin) for all reference modes. By choosing different signal input ranges, trade-offs can be made between noise and distortion performance. For example, applications requiring the maximum signal-to-noise performance (SNR) will benefit from the 2VPP input range while lower distortion may be obtained with the reduced input range of 1VPP. Depending on the input driver configuration the 1VPP range may also relax the requirements for the driver, particularly for single-ended, single-supply applications. DIFFERENTIAL INPUTS Input Impedance (kW) 50 The ADS5220 input structure is designed to accept both a single-ended or differential analog signal. However, the ADS5220 achieves its optimum performance when the analog inputs are driven differentially. 40 30 20 10 0 1 10 100 Input Frequency (MHz) Figure 21. Differential Input Impedance vs Input Frequency INPUT COMMON-MODE VOLTAGE The ADS5220 operates from a single +3.3V supply, 12 Differential operation of the ADS5220 requires that an input signal at the inputs (IN, IN) has the same amplitude and is 180 degrees out-of-phase. Differential signals offer a number of advantages: * The signal amplitude is half that required for the single-ended operation, and is therefore less demanding to achieve, while maintaining good linearity performance from the signal source. * The reduced signal swing allows for more headroom of the interface circuitry, and therefore also allows a wider selection of the most suitable driver amplifier. * Minimization of even-order harmonics. * Improved noise immunity based on the common-mode input rejection of the converter. Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 ANALOG INPUT DRIVEN BY TRANSFORMER 24.9W 1:n The ADS5220 can be driven by a transformer, which provides signal AC-coupling and allows a signal conversion from single-ended input to differential output, or from single-ended input to single-ended output. Using a transformer offers a number of advantages. As a passive component, it does not add to the total noise and has better harmonics in wide frequency bands, compared to an op amp driver. By using a step-up transformer, further signal amplification can be realized; as a result, the signal swing from the source can be reduced. For transformer selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. A variety of miniature RF transformers from different manufacturers (such as Mini-Circuits, Coilcraft, or Trak) can be selected. IN RS ADS5220 22pF 24.9W IN RT 0.1mF 1.7kW 3.3V 1.5V 1.5kW Figure 22. Transformer-Coupled Differential Input Configuration of ADS5220 The resistor values typically range from 10 to 50, and capacitors are in the range of 10pF to 100pF for specific application requirements. ANALOG INPUT DRIVEN BY AMPLIFIER Figure 22 shows a transformer-coupled input configuration of the ADS5220. The ADS5220 receives a differential AC signal from the output of the transformer and common-mode voltage of +1.5V from the center tap. A source termination resistor, RT, is required, which may be placed at the primary or secondary side of the transformer to satisfy the termination requirements of the source impedance, RS. The circuit also shows the use of an additional RC low-pass filter placed in series with each converter input to attenuate some of the wideband noise. The ADS5220 can be driven by an operational amplifier with DC or AC signal coupling, as shown in Figure 23 and Figure 24. In Figure 23, the THS4503, a differential amplifier, is used to convert a single-ended input into a differential output with a gain of 2. The THS4503 provides an output common-mode voltage set by the VOCM pin, and is DC-coupled to the input of ADS5220. A low-pass filter can be created by adding small capacitors (for example, 10pF) in parallel with the feedback resistors of the THS4503 as needed for some applications. +5V 10pF (1) 392W 187W 24.9W IN 50W Source VOCM 60.4W THS4503 24.9W ADS5220 22pF IN 0.1mF 392W 215W 10pF (1) - 5V 1.7kW 3.3V 1.5V 1.5kW NOTE: (1) optional. Figure 23. Using the THS4503 Differential Amplifier (Gain = 2) to Drive the ADS5220 in a DC-Coupled Configuration Submit Documentation Feedback 13 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 +5V 0.1mF 6.8mF 1.6kW 806W 1kW 3.3V +5V 0.1mF 0.1mF 50W Source 57.6W 806W 30W IN OPA695 47pF 0.1mF 487W ADS5220 487W IN 0.1mF 1.6kW 1.25V 3.3V 47pF 1kW Figure 24. Single-Ended Input of ADS5220 Driven by OPA695 with Gain = 2 Due to the THS4503 driving a capacitive load, small series resistors in the output ensure stable operation. Further details of this and other functions of the THS4503 may be found in its product datasheet, located on the Texas Instruments web site (www.ti.com). In general, differential amplifiers provide a high-performance driver solution for applications that require DC signal coupling. As shown in Figure 24, an AC-coupled, single-ended input configuration is realized with TI's OPA695 for wideband applications. For narrowband applications, the OPA2822 can be used. In Figure 24, the OPA695 is configured for a single-supply +5V and noninverting operation. The AC gain of the amplifier is 2 and the DC bias of the amplifier is +2.5V, set by the voltage divider from the op amp power supply. The OPA695 is a very high bandwidth, current-feedback op amp that combines 4200V/s slew rate and low input voltage noise. The OPA695 high slew-rate and output drive capability can support the maximum full-scale input range of the ADS5220 up to high input frequencies. Further details of the OPA695 can be found in the OPA695 data sheet. The common-mode voltage at the ADS5220 input is +1.25V, set by a voltage divider from +3.3V power supply. The +3.3V power supply must be decoupled, as shown in Figure 30. CLOCK INPUT The clock input of the ADS5220 is designed to operate with a single-ended pulse clock with CMOS/TTL level and DC-coupling. There is no external common-mode voltage requirement at the clock input pin (see Figure 25). 3.3V CMOS/TTL 0V CLK Clock Source 50W 50W ADS5220 Mode Select A = DCA enabled B = DCA disabled DVDD A B Figure 25. General Input Clock Interface of ADS5220 14 Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 The clock input of the ADS5220 is referenced to the digital supply (DVDD) and the applied logic levels should comply with the specified levels (LV-logic). To obtain the specified level of performance the clock signal applied to the ADS5220 should have as close to a 50% duty cycle as possible. This clock signal is particularly important when the ADS5220 is operated at its maximum sampling rate. Since this condition cannot always easily be met, the ADS5220 features an on-chip duty-cycle adjust (DCA) circuit that allows for additional design flexibility. The function of this duty cycle adjust circuit is controlled through the Mode Select pin. Its default configuration is for a logic low (internal pull-down) which has the DCA circuit disabled. Applying a logic high, the DCA circuit becomes activated. Now the incoming clock duty cycle can be in the range of 35% to 65% and the DCA circuit adjusts this to be 50% for the internal timing. There may be situations where the user may prefer to disable the DCA function; for example, during asynchronous clocking (that is, when the sampling period is purposely not constant). In any case, a very low jitter clock is fundamental to preserving the excellent AC performance of the ADS5220. Generally, as input frequency increases, clock jitter becomes more critical to maintain a good signal-to-noise ratio. The following equation can be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in psRMS): SNR JA + 20 log 12 @ p @ f IN @ t JA Here, the tJA is the RMS aperture jitter from all jitter sources, such as clock edge, input signal and the device. The fIN is input frequency. The crystal oscillator has very low jitter, but if using a clock conditioning circuit (gate, divider, logic level converter, and so forth), the extra jitter and timing variation must be considered. In addition, the input clock is treated as an analog signal and its power supply should be separated from the power supply of the digital output driver to limit the digital noise. MINIMUM SAMPLING RATE The pipeline architecture of the ADS5220 uses a switched-capacitor technique in its internal track-and-hold stages. The high sampling speed necessitates the use of very small capacitor values. In order to hold droop errors low, the capacitors require a minimum refresh rate. To maintain accuracy of the acquired sample charge, the sampling clock on the ADS5220 must not drop below the specified minimum of 1MSPS. REFERENCE The ADS5220 provides both an internal and an external reference mode through the configuration of pins RSEL and VREF (see Table 1). The input full-scale range (FSR) of the ADS5220 is always twice the voltage at the VREF pin. The REFT and REFB pins are internally buffered, and drive the ADC core for both the external and internal reference modes. When the internal reference mode is selected the voltage at VREF is generated by an internal 0.5V bandgap voltage through a VREF amplifier. This internal buffer amplifier can be used to supply up to 2mA to external circuitry. Selecting the external reference mode powers down this reference amplifier, and the VREF pin becomes the input for the external reference voltage. In the power-down mode, the impedance of the VREF pin is approximately 6k. Table 1 shows the values for VREFT, VREFB, and VREF for the various modes and full-scale input ranges. Table 1. Reference Configuration SELECTED MODE RSEL PIN CONNECT TO VREF PIN (V) INPUT FSR (VPP) (Differential) Internal Fixed GND to 0.2V 1.0 2 2 1 Internal Fixed VREF Pin 0.5 1 1.75 1.25 Internal Program 0.2V to VREF 0.5 * (1 + R2/R1) 2 * VREF VREF/2 + 1.5 1.5 - VREF/2 External AVDD (3.3V) Ext. 0.5V to 1V 2 * VREF VREF/2 + 1.5 1.5 - VREF/2 Submit Documentation Feedback REFT (V) REFTB (V) 15 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 The ADS5220 requires its reference pins to be bypassed as outlined in Figure 26 through Figure 29. The configuration remains the same for the internal or external reference modes. The bypassing should consist of two pairs of 2.2F ceramic and 15F tantalum capacitors, and a 10F tantalum capacitor, as depicted in Figure 26. Connecting RSEL to the VREF pin provides an internal reference voltage of +0.5V at VREF, +1.75V at REFT, and +1.25V at REFB. In this case, the input FSR is +1V peak-to-peak. Setting the resistor divider as in Figure 28 provides an internal voltage between +0.5V and +1V at VREF, which is as follows: V REF + 0.5 @ 1)R 2R1 In this case, the voltage at REFT and REFB and input FSR is calculated based on Table 1. RSEL VREF 0.1mF + 2.2mF 1V Output RSEL 402W ADS5220 VREF +3.3V 0.1mF + 2.2mF 0.5V Output REFT 2W + 10mF 2.2mF + 15mF +3.3V REFT 2W 2W REFB 402W 402W ADS5220 2.2mF + + 10mF 2.2mF + 15mF 15mF 2W REFB In addition to the bypassing the top reference and bottom reference pins (REFT, REFB) also require a pull-up and a pull-down resistor, respectively. As shown in Figure 26, the pull-up resistor should be connected from the REFT pin to the analog supply (+3.3V AVDD), while the pull-down resistor on the REFB pin should be connected to ground. For proper operation the value of those resistors should be maintained as shown, that is, 402. Also, to ensure optimal settling of the internal reference amplifiers, the external configuration must include two low value resistors located in series with each of the REFT and REFB pins (see Figure 26). For best results, use small surface mount chip resistors and position them as close to the pins as possible. + 15mF Figure 27. Internal Reference Mode for VREF = 0.5V RSEL R2 VREF + 0.1mF 2.2mF R1 402W ADS5220 +3.3V REFT 2W Internal Reference + + 10mF 2.2mF 15mF 2W There are two internal fixed reference modes and one internal programmable reference mode as shown in Table 1 and Figure 26 through Figure 28. Setting RSEL to ground (or < 0.2V) provides an internal reference voltage of +1.0V at pin VREF, +2V at pin REFT, and +1V at pin REFB. In this case, the input FSR is +2V peak-to-peak. 16 2.2mF 402W Figure 26. Internal Reference Mode for VREF = 1V REFB + 402W 2.2mF Figure 28. Internal Reference for VREF = 0.5 * (1 + R2/R1) Submit Documentation Feedback 15mF ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 External Reference For even more design flexibility, the ADS5220 can be operated with external references (see Figure 29). Utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or flexible full-scale range. Particularly in multi-channel applications, the use of a common external reference offers the benefit of improving gain matching between converters. Setting RSEL to AVDD (+3.3V) provides an external reference mode for the ADS5220. In this case, the internal VREF amplifier is powered down, and the VREF pin requires an external reference voltage between +0.5V to +1V to provide an input full-scale range of 1VPP to 2VPP. The REFT and REFB appear with the voltage as shown in Table 1, and input FSR is always twice the voltage at the VREF pin. A voltage reference (REF1004 or TPS79225) and a single-supply amplifier (OPA2234 or OPA4227) can be used to generate a precision external reference. AVDD RSEL Input 0.5V to 1V VREF 0.1mF + 2.2mF 402W ADS5220 +3.3V REFT 2W + 10mF 2.2mF + 15mF 2W REFB 402W 2.2mF + 15mF Figure 29. External Reference Configuration output coding. The two code structures are identical with one exception: the MSB is inverted for the BTC format, as shown in Table 2. If the input signal exceeds the FSR, the output code will remain at all 1s or all 0s. Table 2. Coding Table for Differential Input Configuration with FSR of 2VPP STRAIGHT OFFSET BINARY (SOB) BINARY TWO'S COMPLEMENT (BTC) +FS - 1LSB (+FS: IN = 2V, IN = 1V) 1111 1111 1111 0111 1111 1111 +1/2 FS (IN = 1.75V, IN = 1.25V) 1100 0000 0000 0100 0000 0000 Bipolar Zero (IN = IN = 1.5V) 1000 0000 0000 0000 0000 0000 -1/2 FS (IN = 1.75V, IN = 1.25V) 0100 0000 0000 1100 0000 0000 -FS (IN = 2V, IN = 1V) 0000 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT Output Enable (OE) The digital outputs including the OVR pin of the ADS5220 can be set to output enable or output high impedance (tri-state) by the OE pin. For normal operation, this pin must be at a logic low (default is internal pull-down), whereas a logic high disables the outputs or sets the output tri-state. Output Loading It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 10pF. Higher capacitive loading causes larger dynamic currents as the digital outputs are changing. These high current surges can feed back to the analog portion of the ADC and adversely affect device performance. If necessary, external buffers or latches (for example, the SN74LVTH16374) close to the converter output pins can be used to minimize capacitive loading. Buffers or latches also provide the added benefit of isolating the ADS5220 from any digital activities on the bus to limit the high-frequency noise. Over-Range Indicator DIGITAL OUTPUTS Data Output Format The ADS5220 makes two data output formats available, either the Straight Offset Binary (SOB) code or the Binary Two's Complement (BTC) code. The selection of the output coding is controlled through the MSBI pin. Applying a logic high will enable the BTC coding, whereas a logic low will enable the SOB code. In its default configurations the MSBI pin assumes a logic low level (internal pull-down) and the ADS5220 operates with the SOB The ADS5220 has control functions for the input voltage over full-scale that includes output data code control and over-range indication. The output data code control of over full-scale is shown in Table 2. In SOB format, for example, when the input voltage is (+FS - 1 LSB) or above this value, the ADS5220 outputs all 1s at 12 data bits; when the input voltage is -FS or below this value, the ADS5220 outputs all 0s at 12 data bits. When the input voltage is 0 (mid-scale) or only the common-mode voltage at the input, the ADS5220 outputs 1 at MSB and 0s at the remaining 11 data bits. Another over-range control Submit Documentation Feedback 17 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 function of the ADS5220 is over-range indication, which is output by the OVR pin. The OVR pin is the function of the reference voltage and the output data bits, and has the same pipeline delay as the output data bits. OVR is at logic low if the input voltage is within the FSR, and is at logic high if the input voltage is over full-scale or under full-scale. OVR changes from logic low to high or logic high to low immediately following the change of the output data, when the input voltage changes from normal value to over FS or from over FS to normal value. The OVR signal remains high for as long as the input signal exceeds the input range limits of the ADS5220. The OVR pin is tri-stated by the use of the output enable pin (OE). chip capacitor. The analog supply (AVDD) and the digital supply (DVDD or VDRV) may be tied together externally with a ferrite bead or inductor between the supply pins. The ADS5220 is specified with the digital output driver supply, VDRV, set to +2.5V. Timing Power Dissipation The ADS5220 samples the analog signal at the falling edge of its input clock, and outputs the digital data at the rising edge of the input clock after a pipeline delay of 4.5 clocks . There is an aperture delay (typically 3ns) between the sampling edge and the actual sampling time. In normal operating mode (STPD = low and QPD = low), the typical total power dissipation of the ADS5220 is 195mW. The majority of the power consumption is a result of biasing; therefore, this part of the total power dissipation is independent of the applied clock frequency. The current on the VDRV supply is directly related to the capacitive loading of the data output pins; care must be taken to minimize such loading. There is also a propagation delay between the rising edge of the clock and the time that data is valid on the data bus (see the Timing Diagram). The output data of the ADS5220 is latched data. It is highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies can radiate noise that could interfere with any high-frequency input signal and cause unwanted modulation products. The supply voltage should stay within the tolerance given in the Electrical Characteristics table. A basic application configuration with the power-supply decoupling is shown in Figure 30. POWER SUPPLIES AND POWER DISSIPATION Analog and Digital Power Supplies The ADS5220 includes power-supply pins of AVDD, DVDD and VDRV. The analog supply AVDD and digital supply DVDD is +3.3V. The digital output driver supply, VDRV, can be set between +2.5V and +3.3V. AVDD, DVDD and VDRV are not tied together internally. Each of these supply pins must be bypassed separately with at least one 0.1F ceramic 18 Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 3.3V 1.5VDC 35 402W + 15mF 2.2mF +3.3V (AVDD) 2W 10mF 34 33 32 402W + 15mF 2.2mF 2W 38 39 40 43 44 45 27 28 29 46 VPULSE AVDD 37 36 AVDD 48 DVDD DVDD 47 5 Q PD OVR IN NC IN NC NC D11 (MSB) D10 REFT D9 NC D8 REFB D7 ADS5220 D6 AGND D5 AGND D4 AGND D3 DGND D2 DGND D1 DGND D0 (LSB) AGND 25 24 23 22 LATCH 10 11 12 13 14 15 16 17 18 19 20 21 SN74LVTH16374 AGND AGND CLK + - 4 Mode Select NC 49.9W GNDRV 41 RSEL 26 GNDRV 22pF 24.9W NC 7 1.5VDC 0.10mF 6 42 0.10mF VDRV 24.9W 10mF + VREF VDRV 31 8 30 ST PD 3 2 + 0.10mF 10mF + 9 2.2mF OE MSBI 1 3.3V 0.10mF 10mF + NC = No Connection. VDRV Figure 30. General Configuration for the ADS5220 Power Down The ADS5220 provides two power-down modes for different application requirements. One is the Standard Power-Down (STPD); the second is the Quasi-Power-Down (QPD). Both pins will assume a logic low level (internal pull-down) and configure the ADS5220 for normal operation. Setting STPD to logic high (and QPD to logic low or high) shuts down the internal ADC core and power down the reference circuit. In this case the power dissipation is typically 15mW. With 10F external decoupling capacitor at REFT and REFB, it takes about 800s to fully restore normal operation after the normal mode is enabled. Setting QPD to logic high (and STPD to logic low) shuts down the internal ADC core while the internal reference circuit power remains on. In this case, power dissipation is typically 75mW. It takes about 2s to fully restore normal operation after the normal mode is enabled. During power-down, data in the converter pipeline will be lost and new valid data is subject to the specified pipeline delay. Submit Documentation Feedback 19 ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 LAYOUT AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Achieving optimum performance with a fast sampling converter like the ADS5220 requires careful attention to the printed circuit board (PCB) layout in order to minimize the effect of board parasitics and optimize component placement. A multi-layer board usually ensures best results and allows convenient component placement. The ADS5220 must be treated as an analog component, and the AVDD pins connected to a clean analog supply. This configuration ensures the most consistent results, because digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. The driver supply pins (VDRV) must also be connected to a low-noise supply. Supplies of adjacent digital circuits can carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS5220 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins must directly connect to an analog ground plane that covers the PCB area under the converter. As a result of its high sampling frequency, the ADS5220 generates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this adds noise to the conversion process. See Figure 30 for the recommended supply decoupling scheme for the ADS5220. All AVDD pins should be bypassed with a combination of 0.1F ceramic chip capacitors (0805, low ESR) and a 10F tantalum tank capacitor. A similar approach may be used on the digital supply pins DVDD and driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors must be located as close to the supply pins as possible. They are best placed directly under the package where double-sided component 20 mounting is allowed. In addition, larger bipolar decoupling capacitors (2.2F to 10F), effective at lower frequencies, may also be used on the main supply pins. They can be placed on the PCB in close proximity (< 0.5 inches) to the ADC. If the analog inputs to the ADS5220 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences can create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps rather than one dual amplifier enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS5220 package follows a flow-through design with the analog inputs located on one side of the package, whereas the digital outputs are located on the opposite side of the quad-flat package. This configuration provides a good physical isolation between the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Single-ended clock lines must be short and should not cross any other signal traces. Short circuit traces on the digital outputs minimize capacitive loading. Trace length must be kept short to the receiving gate (< 2 inches) with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with the TI SN74LVTH16374, for example). Dynamic performance can also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow as the fast edge rate. The resistor value may be chosen to give a time constant of 15% to 25% of the used data. Submit Documentation Feedback ADS5220 www.ti.com SBAS261D - APRIL 2003 - REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from C Revision (May 2006) to D Revision ..................................................................................................... Page * * * * * * * * * * Changed document format to XML....................................................................................................................................... 1 Changed Data Latency from 5 to 4.5 clock cycles ............................................................................................................... 3 Changed Timing Diagram .................................................................................................................................................... 7 Changed Timing Characteristics table ................................................................................................................................. 7 Changed from "eight middle" to "seven" stages in Theory of Operation section (regarding pipeline sections) ................. 11 Changed from "rising" to "falling" edge in Theory of Operation section (regarding initiation of conversion)...................... 11 Changed from "5" to "4.5" clock cycles in Theory of Operation section (regarding data latency)...................................... 11 Changed Figure 21. Corrected grid lines and X,Y axes. .................................................................................................... 12 Changed from "rising" to "falling" edge in Timing section (regarding analog signal sampling) .......................................... 18 Changed from "5" to "4.5" clocks in Timing section (regarding pipeline delay).................................................................. 18 Changes from B Revision (March 2005) to C Revision ................................................................................................. Page * Changed device ordering number. ....................................................................................................................................... 2 Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS5220PFBT NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS5220PFBTG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS5221PFBT NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5221PFBTG4 NRND TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS5220PFBT TQFP PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS5221PFBT TQFP PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5220PFBT TQFP PFB 48 250 210.0 185.0 35.0 ADS5221PFBT TQFP PFB 48 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A - JANUARY 1995 - REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0- 7 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. 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