1. General description
The 74LVC1G66 provides one single pole, single-thro w analog switch function. It has two
input/output terminals (Yand Z) and an active HIGH enable input pin (E). When E is LOW ,
the analog switch is turned off.
Schmitt-trigger action at the enable inpu t makes the circuit tolerant of slower input rise and
fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at VCC =2.7V
6.5 Ω (typical) at VCC =3.3V
6Ω (typical) at VCC =5V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable input accepts voltages up to 5.5 V
Multiple package options
Specified from −40 °Cto+85°C and −40 °Cto+125°C
3. Ordering information
74LVC1G66
Bilateral switch
Rev. 7 — 30 July 2010 Product data sheet
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G66GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm SOT353-1
74LVC1G66GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G66GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1.45 ×0.5 mm SOT886
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Product data sheet Rev. 7 — 30 July 2010 2 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
74LVC1G66GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1×0.5 mm SOT891
74LVC1G66GN −40 °C to +125 °C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 ×1.0 ×0.35 mm SOT1115
74LVC1G66GS −40 °C to +125 °C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 ×1.0 ×0.35 mm SOT1202
Tabl e 1. Ordering information …continued
Type number Package
Temperature range Name Description Version
Table 2. Marking
Type number Marking code[1]
74LVC1G66GW VL
74LVC1G66GV V66
74LVC1G66GM VL
74LVC1G66GF VL
74LVC1G66GN VL
74LVC1G66GS VL
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aag48
7
E
ZY
mna076
4 # 12
X1
1
1
Fig 3. Logic diagra m
001aam39
7
VCC
E
Y
Z
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Product data sheet Rev. 7 — 30 July 2010 3 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
Fig 4. Pin configuration
SOT353-1 and SOT753 Fig 5. Pin co nfiguration SOT886 Fig 6. Pin configuration SOT891
and SOT1115 and SOT1202
74LVC1G66
YV
CC
Z
GND E
001aad654
1
2
3
5
4
74LVC1G66
Z
001aag498
Y
GND
n.c.
VCC
E
Transparent top view
2
3
1
5
4
674LVC1G66
Z
001aag499
Y
GND
n.c.
VCC
E
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
SOT353-1, SOT753 SOT886, SOT891, SOT1115 an d SOT1202
Y 1 1 independent input or output
Z 2 2 independent output or input
GND 3 3 ground (0 V)
E 4 4 enable input (active HIGH)
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table[1]
Input E Switch
LOFF-state
H ON-state
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Product data sheet Rev. 7 — 30 July 2010 4 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
8. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
VIinput voltage [1] −0.5 +6.5 V
IIK input clamping current VI<−0.5 V or VI>V
CC +0.5V −50 - mA
ISK switch clamping current VI<−0.5 V or VI>V
CC +0.5V - ±50 mA
VSW switch voltage enable and disable mode [2] −0.5 VCC +0.5 V
ISW switch current VSW >−0.5 V or VSW <V
CC +0.5V - ±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[3] -250 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VSW switch voltage [1] 0- V
CC V
Tamb ambient temp erature −40 - +125 °C
Δt/ΔV input transition rise and
fall rate VCC = 1.65 V to 2.7 V [2] --20ns/V
VCC = 2.7 V to 5.5 V [2] --10ns/V
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Product data sheet Rev. 7 — 30 July 2010 5 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
10. Static characteristics
[1] All typical values are measured at Tamb =25°C.
[2] These typical values are measured at VCC =3.3V.
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage VCC = 1.65 V to 1.95 V - - 0.35VCC -0.35V
CC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC -0.3V
CC V
IIinput leakage
current pin E; VI= 5.5 V or GND;
VCC = 0 V t o 5.5 V [2] -±0.1 ±5-±100 μA
IS(OFF) OFF-state
leakage
current
VCC = 5.5 V; see Figure 7 [2] -±0.1 ±5-±200 μA
IS(ON) ON-state
leakage
current
VCC = 5.5 V; see Figure 8 [2] -±0.1 ±5-±200 μA
ICC supply
current VI= 5.5 V or GND;
VSW =GNDorV
CC;
VCC =1.65Vto5.5V
[2] -0.110 - 200μA
ΔICC additional
supply
current
pin E; VI=V
CC −0.6 V;
VSW =GNDorV
CC; VCC =5.5V [2] -5500-5000μA
CIinput
capacitance -2.0---pF
CS(OFF) OFF-state
capacitance -6.5---pF
CS(ON) ON-state
capacitance -11---pF
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Product data sheet Rev. 7 — 30 July 2010 6 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
10.1 Test circuits
10.2 ON resistance
VI = VCC or GND and VO = GND or VCC.V
I = VCC or GND and VO = open circuit.
Fig 7. Test circuit for measuring OFF-state leakage
current Fig 8. Test circuit for measuring ON-state leakage
current
001aam38
9
I
S
VI
V
IL
VO
V
CC
GND
YZ
E
001aam39
0
I
S
VI
V
IH
VO
V
CC
GND
YZ
E
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI=GNDtoV
CC; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V - 34.0 130 - 195 Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 12.0 30 - 45 Ω
ISW =12mA; V
CC =2.7V - 10.4 25 - 38 Ω
ISW =24mA; V
CC = 3 .0 V to 3.6 V - 7.8 20 - 30 Ω
ISW =32mA; V
CC = 4 .5 V to 5.5 V - 6.2 15 - 23 Ω
RON(rail) ON resistance (rail) VI= GND; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V -8.218 - 27Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.1 16 - 24 Ω
ISW =12mA; V
CC = 2.7 V - 6.9 14 - 21 Ω
ISW =24mA; V
CC = 3 .0 V to 3.6 V - 6.5 12 - 18 Ω
ISW =32mA; V
CC = 4 .5 V to 5.5 V - 5.8 10 - 15 Ω
VI=V
CC; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V - 10.4 30 - 45 Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.6 20 - 30 Ω
ISW =12mA; V
CC = 2.7 V - 7.0 18 - 27 Ω
ISW =24mA; V
CC = 3 .0 V to 3.6 V - 6.1 15 - 23 Ω
ISW =32mA; V
CC = 4 .5 V to 5.5 V - 4.9 10 - 15 Ω
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Product data sheet Rev. 7 — 30 July 2010 7 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
[1] Typical values are measured at Tamb = 25 °C and nominal VCC.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical V CC and
temperature.
10.3 ON resistance test circuit and graphs
RON(flat) ON resistance
(flatness) VI=GNDtoV
CC [2]
ISW =4mA;
VCC = 1.65 V to 1.95 V -26.0- - - Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 5.0 - - - Ω
ISW =12mA; V
CC =2.7V - 3.5 - - - Ω
ISW =24mA; V
CC = 3.0 V to 3.6 V - 2.0 - - - Ω
ISW =32mA; V
CC = 4.5 V to 5.5 V - 1.5 - - - Ω
Table 8. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
RON =V
SW/ISW.(1)V
CC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 9. Test circuit for measuring ON resistance Fig 10. Typical ON resistance as a function of input
voltage; Tamb = 25 °C
001aam391
VI
VIH
VCC
GND
ZY
E
VSW
ISW
VI (V)
054231
mna673
20
10
30
40
RON
(Ω)
0
(1)
(2)
(3)
(4) (5)
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Product data sheet Rev. 7 — 30 July 2010 8 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 11. ON resistance as a function of input voltage;
VCC =1.8V Fig 12. ON resistance as a function of input voltage;
VCC =2.5V
VI (V)
0 2.01.60.8 1.20.4
001aaa712
25
35
15
45
55
RON
(Ω)
5
(4)
(3)
(2)
(1)
VI (V)
0 2.52.01.0 1.50.5
001aaa708
9
11
7
13
15
RON
(Ω)
5
(1)
(2)
(3)
(4)
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 13. ON resistance as a function of input voltage;
VCC =2.7V Fig 14. ON resistance as a function of input voltage;
VCC =3.3V
001aaa709
VI (V)
0 3.02.01.0 2.51.50.5
9
7
11
13
RON
(Ω)
5
(1)
(2)
(3)
(4)
VI (V)
04312
001aaa710
6
8
10
RON
(Ω)
4
(1)
(2)
(3)
(4)
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Product data sheet Rev. 7 — 30 July 2010 9 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
11. Dynamic characteristics
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 15. ON resistance as a function of input voltage; VCC =5.0V
VI (V)
054231
001aaa711
5
4
6
7
RON
(Ω)
3
(2)
(4)
(1)
(3)
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
tpd propagation delay Y to Z or Z to Y;
see Figure 16 [2][3]
VCC = 1.65 V to 1.95 V - 0.8 2.0 - 3.0 ns
VCC = 2.3 V to 2.7 V - 0.4 1.2 - 2.0 ns
VCC = 2.7 V - 0.4 1.0 - 1.5 ns
VCC = 3.0 V to 3.6 V - 0.3 0.8 - 1.5 ns
VCC = 4.5 V to 5.5 V - 0.2 0.6 - 1.0 ns
ten enable time E to Y or Z; see Figure 17 [4]
VCC = 1.65 V to 1.95 V 1.0 5.3 12 1.0 15.5 ns
VCC = 2.3 V to 2.7 V 1.0 3.0 6.5 1.0 8.5 ns
VCC = 2.7 V 1.0 2.6 6.0 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.5 5.0 1.0 6.5 ns
VCC = 4.5 V to 5.5 V 1.0 1.9 4.2 1.0 5.5 ns
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Product data sheet Rev. 7 — 30 July 2010 10 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
[1] Typical values are measured at Tamb =25°C and nominal VCC.
[2] tpd is the same as tPLH and tPHL
[3] propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL
[5] tdis is the same as tPLZ and tPHZ
[6] CPD is used to determine the dynamic power dissipation (PD in μW).
PD=C
PD ×VCC2×fi×N+Σ{(CL+C
S(ON))×VCC2×fo} where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ{(CL+C
S(ON)) ×VCC2×fo} = sum of the outputs.
11.1 Waveforms and test circuit
tdis disable time E to Y or Z; see Figure 17 [5]
VCC = 1.65 V to 1.95 V 1.0 4.2 10 1.0 13 ns
VCC = 2.3 V to 2.7 V 1.0 2.4 6.9 1.0 9.0 ns
VCC = 2.7 V 1.0 3.6 7.5 1.0 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 3.4 6.5 1.0 8.5 ns
VCC = 4.5 V to 5.5 V 1.0 2.5 5.0 1.0 6.5 ns
CPD power dissipation
capacitance CL=50pF; f
i=10MHz;
VI=GNDtoV
CC
[6]
VCC =2.5V - 9.8 - - - pF
VCC =3.3V - 12.0 - - - pF
VCC =5.0V - 17.3 - - - pF
Table 9. Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. In put (Y or Z) to output (Z or Y) propa ga tio n de la y s
mna66
7
t
PLH
t
PHL
V
M
V
M
Y or Z input
Z or Y output
GND
V
I
V
OH
V
OL
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Product data sheet Rev. 7 — 30 July 2010 11 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
mna66
8
tPLZ
tPHZ
switch
disabled
switch
enabled
VY
VX
switch
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
E
Y or Z
Y or Z
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 10. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V
2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V
2.7V 1.5V 1.5V V
OL + 0.3 V VOH − 0.3 V
3.0Vto3.6V 1.5V 1.5 V V
OL + 0.3 V VOH − 0.3 V
4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V
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Product data sheet Rev. 7 — 30 July 2010 12 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
11.2 Additional dynamic characteristics
Test data is given in Table 11.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Test circuit for measuring switching times
V
EXT
V
CC
V
I
V
O
mna61
6
DUT
CL
RT
RL
RL
G
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V VCC ≤2.0ns 30pF 1kΩopen GND 2VCC
2.3 V to 2.7 V VCC ≤2.0ns 30pF 500Ωopen GND 2VCC
2.7 V 2.7 V ≤2.5ns 50pF 500Ωopen GND 6 V
3.0 V to 3.6 V 2.7 V ≤2.5ns 50pF 500Ωopen GND 6 V
4.5 V to 5.5 V VCC ≤2.5ns 50pF 500Ωopen GND 2VCC
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb =25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic disto r ti on RL=10kΩ; CL=50pF; f
i= 1 kHz;
see Figure 19
VCC =1.65V - 0.032 - %
VCC = 2.3 V - 0.008 - %
VCC = 3.0 V - 0.006 - %
VCC = 4.5 V - 0.001 - %
RL=10kΩ; CL=50pF; f
i=10kHz;
see Figure 19
VCC =1.65V - 0.068 - %
VCC = 2.3 V - 0.009 - %
VCC = 3.0 V - 0.008 - %
VCC = 4.5 V - 0.006 - %
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Product data sheet Rev. 7 — 30 July 2010 13 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
f(−3dB) −3 dB frequency response RL=600Ω; CL=50pF;
see Figure 20
VCC =1.65V - 135 - MHz
VCC =2.3V - 145 - MHz
VCC =3.0V - 150 - MHz
VCC =4.5V - 155 - MHz
RL=50Ω; CL= 5 pF; see Figure 20
VCC =1.65V - > 500 - MHz
VCC =2.3V - > 500 - MHz
VCC =3.0V - > 500 - MHz
VCC =4.5V - > 500 - MHz
RL=50Ω; CL= 10 pF; see Figure 20
VCC =1.65V - 200 - MHz
VCC =2.3V - 350 - MHz
VCC =3.0V - 410 - MHz
VCC =4.5V - 440 - MHz
αiso isolation (OFF-state) RL=600Ω; CL=50pF; f
i= 1 MHz;
see Figure 21
VCC =1.65V - −46 - dB
VCC =2.3V - −46 - dB
VCC =3.0V - −46 - dB
VCC =4.5V - −46 - dB
RL=50Ω; CL=5pF; f
i=1MHz;
see Figure 21
VCC =1.65V - −37 - dB
VCC =2.3V - −37 - dB
VCC =3.0V - −37 - dB
VCC =4.5V - −37 - dB
Vct crosstalk voltage between digital input and switch;
RL=600Ω; CL=50pF; f
i= 1 MHz;
tr=t
f = 2 ns; see Figure 22
VCC =1.65V - 69 - mV
VCC =2.3V - 87 - mV
VCC =3.0V - 156 - mV
VCC =4.5V - 302 - mV
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb =25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 7 — 30 July 2010 14 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
11.3 Test circuits
Qinj charge injection CL= 0.1 nF; Vgen =0V; R
gen =0Ω;
fi= 1 MHz; RL=1 MΩ; see Figure 23
VCC = 1.8 V - 3.3 - pC
VCC = 2.5 V - 4.1 - pC
VCC = 3.3 V - 5.0 - pC
VCC = 4.5 V - 6.4 - pC
VCC = 5.5 V - 7.5 - pC
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb =25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 19. Test circuit for measuring total harmonic distortion
001aam39
2
VIH
VO
VCC 0.5VCC
Z/YY/Z
E
600 Ωfi
RL
10 μF
CLD
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
001aam39
3
V
IH
V
O
V
CC
0.5V
CC
Z/YY/Z
E
50 Ωfi
RL
0.1 μF
CL
dB
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Product data sheet Rev. 7 — 30 July 2010 15 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF -state)
001aam39
4
V
IL
V
O
V
CC
0.5V
CC
Z/YY/Z
E
50 Ωfi
RL
0.5V
CC
RL
0.1 μF
CL
dB
Fig 22. Test circuit for measuring crosstalk between digital input an d switch
001aam39
5
VO
VCC
0.5VCC
Z/YY/Z
E
50 Ω600 Ω
logic
input RL
0.5VCC
CL
G
Qinj =ΔVO ×CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
001aam39
6
V
O
V
CC
Z/YY/Z
E
logic
input
RL
1 MΩ
Rgen
CL
0.1 nF
Vgen
G
001aam39
8
onoff
logic
input (E)
V
O
off
ΔV
O
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 16 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
12. Package outline
Fig 24. Package outline SOT353-1 (TSSOP5)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15 0.65
e1
1.3 2.25
2.0
0.60
0.15
7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A 00-09-01
03-02-19
wM
bp
D
Z
e
e1
0.15
13
54
θ
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
1.5 3 mm0
scale
T
SSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-
1
1.1
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Product data sheet Rev. 7 — 30 July 2010 17 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Fig 25. Package outline SOT753 (SC-74A)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
bp
D
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface-mounted package; 5 leads SOT75
3
UNIT A1bpcDEHELpQywv
mm 0.100
0.013
0.40
0.25
3.1
2.7
0.26
0.10
1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2
0.33
0.23
A
1.1
0.9
02-04-16
06-03-16
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Product data sheet Rev. 7 — 30 July 2010 18 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Fig 26. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT88
6
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17
1.5
1.4
0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 19 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Fig 27. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT89
1
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12
1.05
0.95
0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 20 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Fig 28. Package outline SOT1115 (XSON6)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
X
SON6: extremely thin small outline package; no leads;
6
terminals; body 0.9 x 1.0 x 0.35 mm SOT111
5
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2)
A1A
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 21 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Fig 29. Package outline SOT1202 (XSON6)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
X
SON6: extremely thin small outline package; no leads;
6
terminals; body 1.0 x 1.0 x 0.35 mm SOT120
2
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 22 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
TTL Tr ansistor-Tran s istor Logic
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
DUT Device Under Test
Table 14. Revision history
Document ID Release date Data sheet status Cha nge notice Supersedes
74LVC1 G66 v.7 20100730 Product data sheet - 74LVC1G66 v.6
Modifications: •Added type number 74LVC1G66 GN (SOT1115/XSON6 package).
•Added type number 74LVC1G66 GS (SOT1202/XSON6 package).
74LVC1 G66 v.6 20070827 Product data sheet - 74LVC1G66 v.5
74LVC1 G66 v.5 20070807 Product data sheet - 74LVC1G66 v.4
74LVC1 G66 v.4 20040413 Product specification - 74LVC1G66 v.3
74LVC1 G66 v.3 20021115 Product specification - 74LVC1G66 v.2
74LVC1 G66 v.2 20020529 Product specification - 74LVC1G66 v.1
74LVC1G66 v.1 20011030 Product specification - -
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 23 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descri bed in this d ocument may have change d since this document was p ublished and may dif fer in case of multiple devices. The latest product st atus
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use i n automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medica l, military, aircraft, space or life support equipment,
nor in applications where failure or malf unction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo m er(s). Customer is responsible for doing all necessary
testing for the customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] data sheet Production This document contains the product specification.
74LVC1G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 7 — 30 July 2010 24 of 25
NXP Semiconductors 74LVC1G66
Bilateral switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G66
Bilateral switch
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 July 2010
Document identifier : 74LVC1G66
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.3 ON resistance test circuit and graphs. . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11.1 Waveforms and test circuit . . . . . . . . . . . . . . . 10
11.2 Additional dynamic characteristics . . . . . . . . . 12
11.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16 Contact information. . . . . . . . . . . . . . . . . . . . . 24
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
