74LVX125MTCX_NL - Fairchild Semiconductor

Februa ry 199 4

Revised February 2005

74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs

74LVX125

Low Voltage Quad Buffer with 3-STATE Outputs

General Descript ion

The LVX125 contains four independ ent non-inverting buff-

ers with 3-STATE outputs. The inputs tolerate voltages up

to 7V allowing the interface of 5V systems to 3V systems.

Features

■Input voltage level translation from 5V to 3V

■Ideal for low power/low noise 3.3V applications

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

Ordering Code:

Devices also available in Tape and Reel. Specify by appe nding suffix le tter “X” to the ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Devic e availa ble in Tape an d R eel only.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Truth Table

HIGH Voltage Leve l

LOW Voltage Lev el

High Impedance

Immaterial

Order Number Package Package Description

Number

74LVX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVX125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II , 5.3mm Wide

74LVX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LVX125MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names Description

AnInputs

OEnOutput Enable Inputs

OnOutputs

Inputs Output

OEnAnOn

LLL

LHH

HXZ

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74LVX125

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions (Note 3)

Note 2: The “Absolute Maximum Ratings” are those v alues beyon d which

the saf ety of the device cannot be guarante ed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “R ecomm ended Ope rating Condition s” tabl e will d efine th e cond itions

for actu al device operation.

Note 3: Unu s ed inputs m us t be held HIG H or LOW. They may no t f loat.

DC Electrical Characteristics

Noise Characteristics (Note 4)

Note 4: Input tr

3 ns

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current

(IIK) VI



0.5V



20 mA

DC Input Voltage (VI)



0.5V to



7.0V

DC Output Diode Current (IOK)

0.5V



20 mA

VCC



0.5V



20 mA

Output Voltage (VO)



0.5V to VCC



0.5V

DC Output Source/Sink Current (IO)

25 mA

DC VCC or Ground Curre nt

(ICC or IGND)

50 mA

Storage Temperature Range (TSTG)



C to



150

Power Dissipation 180 mW

Supply Voltage (VCC) 2.0V to 3.6V

Input Voltage (VI) 0V to 5.5V

Output Voltage (VO) 0V to VCC

Operating Temperature (TA)



C to



Input Rise and Fall Time (

V) 0 ns/V to 100 ns/V

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ Max Min Max

VIH HIGH Level 2.0 1.5 1.5

Input V olt age 3.0 2.0 2.0 V

3.6 2.4 2.4

VIL LOW Level 2.0 0.5 0.5

Input V olt age 3.0 0.8 0.8 V

3.6 0.8 0.8

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN

VIL or IOH



Output Voltage 3.0 2.9 3.0 2.9 V VIH IOH



3.0 2.58 2.48 IOH



4 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN

VIL or IOL

Output Voltage 3.0 0.0 0.1 0.1 V VIH IOL

3.0 0.36 0.44 IOL

4 mA

IOZ 3-STATE Output 3.6

0.25

2.5

VIH or VIL

Off-State Current VOUT

VCC or GND

IIN Input Leakage 3.6

0.1

1.0

5.5V or GND

Current

ICC Quiescent Supply 3.6 4.0 40.0

VCC or GND

Current

Symbol Parameter VCC TA

CUnits CL (pF)

(V) Typ Limit

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.8 V 50

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.3



0.8 V 50

VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50

VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50

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74LVX125

AC Electrical Characteristics

Note 5: Parameter guaranteed by design. tOSLH

|tPLHm



tPLHn|, tOSHL

|tPHLm



tPHLn|

Capacitance

Note 6: CPD is defined as t he v alue of the int ernal equ iv alent capacit anc e which is calcula te d f rom t he opera tin g c urrent co ns umption without load.

Symbol Parameter VCC TA





C to



CUnits Conditions

(V) Min Typ Max Min Max

tPLH Propagation De lay T im e 2.7 5.8 10.1 1.0 13.5

15 pF

tPHL Data to Output 8.3 13.6 1.0 17.0 CL

50 pF

3.3

0.3 4.4 6.2 1.0 8.5 CL

15 pF

6.9 9.7 1.0 12.0 CL

50 pF

tPZH Output Enable Time 2.7 5.3 9.3 1.0 12.5

15 pF, RL

1 k

tPZL 7.8 12.8 1.0 16.0 CL

50 pF, RL

1 k

3.3

0.3 4.0 5.6 1.0 7.5 CL

15 pF, RL

1 k

6.5 9.1 1.0 11.0 CL

50 pF, RL

1 k

tPHZ Output Disable 2.7 10.0 15.7 1.0 19.0 ns CL

50 pF, RL

1 k

tPLZ Time 3.3

0.3 8.3 11.2 1.0 13.0 CL

50 pF, RL

1 k

tOSHL Output to Output 2.7 1.5 1.5 ns CL

50 pF

tOSLH Skew (Note 5) 3.3 1.5 1.5

Symbol Parameter TA



C to



CUnits

Min Typ Max Min Max

CIN Input Capacit ance 4.0 10 10 pF

CPD Power Dissipation 14 pF

Capacitance (Note 6)

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74LVX125

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

5 www.fairchildsemi.com

74LVX125

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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2. A critical compon ent in any componen t of a life support

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