SN74LS395 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate in either a synchronous parallel load or a serial shift-right mode, as determined by the Select input. An asynchronous active LOW Master Reset (MR) input overrides the synchronous operations and clears the register. An active HIGH Output Enable (OE) input controls the 3-state output buffers, but does not interfere with the other operations. The fourth stage also has a conventional output for linking purposes in multi-stage serial operations. 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY * Shift Left or Parallel 4-Bit Register * 3-State Outputs * Input Clamp Diodes Limit High-Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 O1 O2 O3 Q3 CP OE 15 14 13 12 11 10 9 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 1 MR 2 DS 3 P0 4 P1 5 P2 6 P3 7 S 8 GND D SUFFIX SOIC CASE 751B-03 16 1 PIN NAMES P0 - P3 DS S CP MR OE O0 - O3 Q3 LOADING (Note a) Parallel Inputs Serial Data Input Mode Select Input Clock (Active LOW) Input Master Reset (Active LOW) Input Output Enable (Active HIGH) Input 3-State Register Outputs Register Output HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 5 U.L. ORDERING INFORMATION SN74LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. 7 3 4 5 6 S P0 P1 P2 P3 2 10 9 DS CP OE Q3 MR O0 O1 O2 O3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 11 SN74LS395 LOGIC DIAGRAM P0 S P1 P2 P3 Ds CP CP D Q CD CP D Q CD CP D Q CD CP CD D Q MR OE O0 O1 O2 O3 Q3 FUNCTION DESCRIPTION The SN74LS395 contains four D-type edge-triggered flip-flops and auxiliary gating to select a D input either from a Parallel (Pn) input or from the preceding stage. When the Select input is HIGH, the Pn inputs are enabled. A LOW signal on the S input enables the serial inputs for shift-right operations, as indicated in the Truth Table. State changes are initiated by HIGH-to-LOW transitions on the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs can change when the Clock is in either state, provided that the recommended set-up and hold times are observed. When the S input is LOW, a CP HIGH-LOW transition transfers data in Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished by connecting the outputs back to the Pn inputs, but offset one place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3 acting as the linking input from another package. When the OE input is HIGH, the output buffers are disabled and the Q0 - Q3 outputs are in a high impedance condition. The shifting, parallel loading or resetting operations can still be accomplished, however. MODE SELECT -- TRUTH TABLE Inputs @ tn Operating Mode Outputs @ tn+1 MR CP S Ds Pn O0 O1 O2 O3 Asynchronous Reset Shift, SET First Stage L H X X L X H X X L H L O0n L O1n L O2n Shift, RESET First Stage Parallel Load H H L H L X X Pn L P0 O0n P1 O1n P2 O2n P3 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial tn, n + 1 = time before and after CP HIGH-to-LOW transition NOTE: When OE is HIGH, outputs O0 - O3 are in the high impedance state; however, this does not affect other operations or the Q3 output. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 C VCC Supply Voltage TA Operating Ambient Temperature Range IOH Output Current -- High - 0.4 mA IOL Output Current -- Low 8.0 mA FAST AND LS TTL DATA 5-2 SN74LS395 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IOZH Min Typ Max U i Unit V Guaranteed Input HIGH Voltage for All Inputs 0.8 V Guaranteed Input LOW Voltage for All Inputs - 1.5 V VCC = MIN, IIN = - 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 2.0 - 0.65 2.7 T Test C Conditions di i 3.5 VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA Output Off Current HIGH 20 A VCC = MAX, VO = 2.4 V IOZL Output Off Current LOW - 20 A VCC = MAX, VO = 0.4 V 20 IIH Input HIGH Current A VCC = MAX, VIN = 2.7 V - 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current - 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) - 100 mA VCC = MAX mA VCC = MAX, OE = GND, CP = GND mA VCC = MAX, OE = 4.5 V, CP momentary 3.0 V then GND - 20 Power Supply Current Total, Output HIGH 31 Total, Output LOW 34 ICC Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits S b l Symbol P Parameter Min Typ 30 45 Max U i Unit fMAX Maximum Input Clock Frequency tPHL Propagation Delay, Clear to Output 22 35 ns tPLH tPHL Propagation Delay, Low to High Propagation Delay, High to Low 15 25 30 30 ns tPZH tPZL Output Enable Time 15 17 25 25 ns tPLZ tPHZ Output Disable Time 12 11 20 17 ns T Test C Conditions di i MHz VCC = 5.0 50V CL = 15 pF CL = 5.0 pF AC SETUP REQUIREMENTS (TA = 25C) Limits S b l Symbol P Parameter Min Typ Max U i Unit tW Clock Pulse Width 16 ns ts Setup Time, Mode Select 40 ns ts Setup Time, All Others 20 ns th Data Hold Time 10 ns FAST AND LS TTL DATA 5-3 T Test C Conditions di i VCC = 5 5.0 0V SN74LS395 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. D 1.3 V * 1.3 V th(L) ts(L) LOAD SERIAL DATA SHIFT RIGHT th(H) ts(H) 1.3 V S CP OR MR LOAD PARALLEL DATA 1.3 V 1.3 V 1.3 V 1/fmax tPHL Q th(L) ts(L) tW tPLH th(H) ts(H) 1.3 V CP 1.3 V *The Data Input is DS for S = LOW and Pn for S = HIGH. Figure 1 VE 1.3 V 1.3 V tPZL VOUT Figure 2 VE tPZH tPLZ 1.3 V VOL 1.3 V 1.3 V VOUT 1.3V tPHZ VOH 1.3 V 0.5 V 1.3 V 0.5 V Figure 4 Figure 3 AC LOAD CIRCUIT VCC RL SWITCH POSITIONS SW1 TO OUTPUT UNDER TEST 5 k CL* SW2 * Includes Jig and Probe Capacitance. Figure 5 FAST AND LS TTL DATA 5-4 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed