5-1
FAST AND LS TTL DATA
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate
in either a synchronous parallel load or a serial shift-right mode, as
determined by the Select input. An asynchronous active LOW Master Reset
(MR) input overrides the synchronous operations and clears the register. An
active HIGH Output Enable (OE) input controls the 3-state output buffers, but
does not interfere with the other operations. The fourth stage also has a
conventional output for linking purposes in multi-stage serial operations.
•Shift Left or Parallel 4-Bit Register
•3-State Outputs
•Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1234567
16 15
8
VCC
MR
O0O1O2O3CPQ3OE
DS P0P1P2P3S GND
PIN NAMES LOADING (Note a)
HIGH LOW
P0–P3
DS
S
CP
MR
OE
O0–O3
Q3
Parallel Inputs
Serial Data Input
Mode Select Input
Clock (Active LOW) Input
Master Reset (Active LOW) Input
Output Enable (Active HIGH) Input
3-State Register Outputs
Register Output
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
SN74LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN74LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
1
2
3456
10
9
15 14 13 12
11
7
SP
0
P
1P
2P
3
D
S
CP
OE MR O0O1O2O3
Q3
5-2
FAST AND LS TTL DATA
SN74LS395
LOGIC DIAGRAM
S
Ds
CP
MR
OE
P0P1P2P3
O0O1O2O3Q3
CP D
CD QCP D
CD QCP D
CD QCP D
CD Q
FUNCTION DESCRIPTION
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
Parallel (Pn) input or from the preceding stage. When the
Select input is HIGH, the Pn inputs are enabled. A LOW signal
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, Ds and S inputs
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
S input is LOW, a CP HIGH-LOW transition transfers data in
Q0 to Q1, Q1 to Q2, and Q2 to Q3. A left-shift is accomplished
by connecting the outputs back to the Pn inputs, but offset one
place to the left, i.e., O3 to P2, O2 to P1 and O1 to P0, with P3
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q0–Q3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still be
accomplished, however.
MODE SELECT — TRUTH TABLE
Inputs @ tnOutputs @ tn+1
Operating Mode MR CP S DsPnO0O1O2O3
Asynchronous Reset L X X X X L L L L
Shift, SET First Stage H L H X H O0n O1n O2n
Shift, RESET First Stage H L L X L O0n O1n O2n
Parallel Load H H X PnP0P1P2P3
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
tn, n + 1 = time before and after CP HIGH-to-LOW transition
NOTE:
When OE is HIGH, outputs O0–O3 are in the high impedance state; however, this does not affect other operations or the Q3 output.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient Temperature Range 0 25 70 °C
IOH Output Current — High –0.4 mA
IOL Output Current — Low 8.0 mA
5-3
FAST AND LS TTL DATA
SN74LS395
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per T ruth Table
VOL
Output LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IOZH Output Off Current HIGH 20 µA VCC = MAX, VO = 2.4 V
IOZL Output Off Current LOW –20 µA VCC = MAX, VO = 0.4 V
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
–0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC
Power Supply Current
Total, Output HIGH 31 mA VCC = MAX, OE = GND, CP = GND
I
CC Total, Output LOW 34 mA VCC = MAX, OE = 4.5 V, CP
momentary 3.0 V then GND
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Input Clock Frequency 30 45 MHz
V50V
tPHL Propagation Delay, Clear to Output 22 35 ns
V50V
tPLH
tPHL Propagation Delay, Low to High
Propagation Delay, High to Low 15
25 30
30 ns VCC = 5.0 V
CL = 15 pF
tPZH
tPZL Output Enable T ime 15
17 25
25 ns
tPLZ
tPHZ Output Disable T ime 12
11 20
17 ns CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Sbl
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tWClock Pulse Width 16 ns
V50V
tsSetup T ime, Mode Select 40 ns
VCC =50V
tsSetup T ime, All Others 20 ns
V
CC =
5
.
0
V
thData Hold T ime 10 ns
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
*The Data Input is DS for S = LOW and Pn for S = HIGH.
Figure 1 Figure 2
Figure 3 Figure 4
D
CP OR
MR
Q
VE
VOUT VOUT
VE
1.3 V1.3 V
1.3 V 1.3 V
1.3 V
tPLH
tPHL
th(L) th(H)
1.3 V
1.3 V
1.3 V
≈
1.3 V
1.3 V
1.3 V
1.3V
≈
1.3 V
0.5 V 0.5 V
tPZL tPLZ
VOL
tPZH tPHZ
≥
VOH
*
1/fmax tW
ts(L) ts(H) S
CP
1.3 V1.3 V
1.3 V
th(L) th(H)
ts(L) ts(H)
LOAD SERIAL DATA
SHIFT RIGHT LOAD PARALLEL DATA
Figure 5
AC LOAD CIRCUIT
SW2CL*
5 k
Ω
SW1
VCC
RL
TO OUTPUT
UNDER TEST
SWITCH POSITIONS
* Includes Jig and Probe Capacitance.
5-4
FAST AND LS TTL DATA
SN74LS395
SYMBOL SW1 SW2
tPZH Open Closed
tPZL Closed Open
tPLZ Closed Closed
tPHZ Closed Closed