MX7535JCWI+ - Maxim Integrated Products, Inc.

_______________General Description

The MX7534/MX7535 are high-performance, CMOS,

monolithic, 14-bit digital-to-analog converters (DACs).

Wafer-level, laser-trimmed, thin-film resistors and tempera-

ture-compensated NMOS switches assure operation over

the full operating temperature range with exceptional lin-

ear and gain stability.

The MX7534 accepts right-justified data in two bytes from

an 8-bit bus, while the MX7535 operates with a 14-bit data

bus with separate MS-byte and LS-byte select controls. In

addition, all digital inputs are compatible with both TTL and

5V CMOS-logic levels. The MX7534/MX7535 are intended

for unipolar operation, but may be operated as bipolar

DACs with additional external components. Both devices

are protected against CMOS latchup, and neither requires

the use of external Schottky protection diodes.

The MX7534 is available in 20-pin narrow (0.3") DIP, wide

SO, or PLCC packages. The MX7535 is available in

28-pin, 600 mil wide DIP, wide SO, or PLCC packages.

________________________Applications

Machine and Motion Control Systems

Automatic Test Equipment

Digital Audio

µP-Controlled Calibration Circuitry

Programmable-Gain Amplifiers

Digitally Controlled Filters

Programmable Power Supplies

____________________________Features

♦14-Bit Monotonic Over Full Temperature Range

♦Full 4-Quadrant Multiplication

♦µP-Compatible, Double-Buffered Inputs

♦Exceptionally Low Gain Tempco (2.5ppm/°C)

♦Low Output Leakage (<20nA) Over Temp.

♦Low Power Consumption

♦TTL and CMOS Compatible

______________Ordering Information

Ordering Information continued at end of data sheet.

Dice are tested at +25°C, DC parameters only.

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

________________________________________________________________

Maxim Integrated Products

MX7534

DAC REGISTER

MS

INPUT

LS

INPUT

7–14

14-BIT DAC

CONTROL

LOGIC

REF RFB

IOUT

AGNDS

AGNOF

VDD

D7–D0 DGND VSS

Functional diagrams continued at end of data sheet.

_______________Functional Diagrams

_________________Pin Configurations

19-1116; Rev 1; 11/96

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

PART TEMP. RANGE PIN-PACKAGE INL (LSBs)

MX7534KN 0°C to +70°C 20 Plastic DIP ±1

MX7534JN 0°C to +70°C 20 Plastic DIP ±2

MX7534KCWP 0°C to +70°C 20 SO ±1

MX7534JCWP 0°C to +70°C 20 SO ±2

MX7534KP 0°C to +70°C 20 PLCC ±1

MX7534JP 0°C to +70°C 20 PLCC ±2

MX7534J/D 0°C to +70°C Dice* ±2

MX7534BQ -25°C to +85°C 20 CERDIP ±1

MX7534AQ -25°C to +85°C 20 CERDIP ±2

MX7534BD -25°C to +85°C 20 Ceramic SB ±1

MX7534AD -25°C to +85°C 20 Ceramic SB ±2

MX7534KEWP -40°C to +85°C 20 SO ±1

MX7534JEWP -40°C to +85°C 20 SO ±2

MX7534TQ -55°C to +125°C 20 CERDIP ±1

MX7534SQ -55°C to +125°C 20 CERDIP ±2

MX7534TD -55°C to +125°C 20 Ceramic SB ±1

MX7534SD -55°C to +125°C 20 Ceramic SB ±2

VSS

VDD

AGNDS

IOUT

RFB

REF

TOP VIEW

DGND

AGNDF

MX7535 at end of data sheet.

DIP/SO/PLCC/Ceramic SB

MX7534

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +11.4V to +15.75V (Note 1), VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA= TMIN to TMAX, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to DGND ............................................................-0.3V, +17V

VSS to AGND.............................................................-15V, +0.3V

REF to AGND (MX7534) ......................................................±25V

REFS to AGND (MX7535)....................................................±25V

REFF to AGND (MX7535) ....................................................±25V

RFB to AGND.......................................................................±25V

Digital Input Voltage to DGND.........................-0.3V, VDD + 0.3V

IOUT to DGND.................................................-0.3V, VDD + 0.3V

AGND to DGND...............................................-0.3V, VDD + 0.3V

Continuous Power Dissipation (TA= +70°C)

20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

28-Pin Plastic DIP (derate 14.29mW/°C above +70°C)......1.14W

20-Pin SO (derate 10.00mW/°C above +70°C)..............800mW

28-Pin SO (derate 12.50mW/°C above +70°C).....................1W

20-Pin PLCC (derate 10.00mW/°C above +70°C) .........800mW

28-Pin PLCC (derate 10.53mW/°C above +70°C) .........842mW

20-Pin CERDIP (derate 11.11mW/°C above +70°C)......889mW

28-Pin CERDIP (derate 16.67mW/°C above +70°C)........1.33W

20-Pin Ceramic SB

(derate 11.76mW/°C above +70°C).............................941mW

28-Pin Ceramic SB

(derate 20.00mW/°C above +70°C)................................1.6W

Operating Temperature Ranges

MX753_J/K............................................................0°C to +70°C

MX753_A/B........................................................-25°C to +85°C

MX753_EW_.......................................................-40°C to +85°C

MX753_S/T.......................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

±10

Input Leakage Current µA

±1

VINL

Input Low Voltage V0.8 V2.4VINH

Input High Voltage

kΩ3.5 6 10RREF

Reference Voltage Input

Resistance (Note 3)

±150

IOUT

Output Leakage Current

±1 Bits14Resolution

±25

±5

ppm/°C

±0.5 ±5

Gain Temperature Coefficient

(Note 2) ±0.5 ±2.5

LSB

±2

INLRelative Accuracy

±4 LSB

±8

Full-Scale Error

UNITSMIN TYP MAXSYMBOLPARAMETER

MX753_K/B/T

TA= TMIN to TMAX

MX753_J/K/A/B

MX753_J/A/S

Measured with internal RFB,

includes effects of leakage

current and gain TC

MX753_S/T

CONDITIONS

LSB±1Guaranteed MonotonicDifferential Nonlinearity

pF7CIN

Input Capacitance (Note 2)

TA= TMIN

to TMAX

All digital

inputs at 0V

All digital

inputs at 0V,

VSS = 0V

TA= +25°C

MX753_J/A/S

MX753_K/B/T

MX753_J/A/S

MX753_K/B/T

TA= +25°C

Digital inputs

at 0V or VDD

DC ACCURACY

REFERENCE INPUT

DIGITAL INPUTS

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

_______________________________________________________________________________________ 3

mV-200 -500VSS

Negative Supply-Voltage Range V11.4 15.75VDD

Positive Supply-Voltage Range

IDD

Positive Supply Current

µA500ISS

Negative Supply Current

UNITSMIN TYP MAXSYMBOLPARAMETER

For specific performance

MX7534

MX7535

Digital inputs at 0V or VDD

CONDITIONS

Digital inputs at

VINH or VINL

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +11.4V to +15.75V (Note 1), VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA= TMIN to TMAX, unless otherwise noted.)

mVp-p

nV-sec50

µs0.8 1.5Output Current Setting Time

Digital-to-Analog Glitch Impulse

nV/Hz15

Output Noise Voltage Density

(10Hz–100kHz)

130

COUT

Output Capacitance (IOUT Pin)

Multiplying Feedthrough Error

(Note 5)

%/%

±0.01

±0.02

Power-Supply Rejection

260

UNITSMIN TYP MAXSYMBOLPARAMETER

TA= +25°C

Measured with VREF = 0V,

IOUT loads = 100Ω

13pF, DAC register

alternately loaded with all 1s and all 0s

TA= +25°C, to 0.003% of full-scale range,

IOUT load = 100Ω

13pF, DAC register

alternately loaded with all 1s and all 0s

Measured between RFB and IOUT

DAC register loaded with all 0s

TA= TMIN to TMAX

TA= +25°C

TA= TMIN to TMAX

DAC register loaded with all 1s

CONDITIONS

VREF = ±10V, 10kHz

sine wave, DAC register

loaded with all 0s

∆VDD = ±5%

Note 1: Specifications are guaranteed for VDD of +11.4V to +15.75V. At VDD = +5V, device is still functional with degraded specifications.

Note 2: Guaranteed by design, not tested.

Note 3: Resistors have a typical -300ppm/°C tempco.

AC PERFORMANCE CHARACTERISTICS (Note 4)

(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGND (VAGNDS for MX7535) = VSS = 0V, output amplifier is AD544*,

TA= TMIN to TMAX, unless otherwise noted.)

Note 4: These characteristics are included for design guidance only, and are not subject to test.

Note 5: Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.

* AD544 is an Analog Devices part.

POWER REQUIREMENTS

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS (MX7534)

(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGND = VSS = 0V, TA= TMIN to TMAX, unless otherwise noted. See Figure 1a for

timing diagram.)

170 ns0t2

ns0t1

CSMSB or CSLSB to WR Setup Time

CSMSB or CSLSB to WR Hold Time

240

Write Pulse Width

200

240

LDAC Pulse Width

170

200

UNITSMIN TYP MAXSYMBOLPARAMETER

TA= +25°C

TA= -55°C to +125°C

TA= -25°C to +85°C

TA= -55°C to +125°C

TA= +25°C

TA= -25°C to +85°C

CONDITIONS

140

Data-Hold Time

160

180

Data-Setup Time

TA= +25°C

TA= -55°C to +125°C

TA= -25°C to +85°C

TA= -55°C to +125°C

TA= +25°C

TA= -25°C to +85°C

TIMING CHARACTERISTICS (MX7535)

(VDD = +11.4V to +15.75V, VREF = 10V, VIOUT = VAGNDS = VSS = 0V, TA= TMIN to TMAX, unless otherwise noted. See Figure 1b for

timing diagram.)

60 ns0t2

ns0t1

Address Valid to Write Setup Time

Address Valid to Write Hold Time

Data Hold Time

Data Setup Time

UNITSMIN TYP MAXSYMBOLPARAMETER

TA= +25°C

TA= -55°C to +125°C

TA= -25°C to +85°C

TA= -55°C to +125°C

TA= +25°C

TA= -25°C to +85°C

CONDITIONS

240

Write Pulse Width

170

200

TA= -55°C to +125°C

TA= +25°C

TA= -25°C to +85°C

Chip-Select to Write-Hold Time

Chip-Select to Write-Setup Time

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

_______________________________________________________________________________________ 5

__________Pin Description (MX7534)

NAME FUNCTION

1REF Reference Input to DAC

2 RFB

3 IOUT Current Output

4 AGNDS Analog Ground Sense. Reference

point for external circuitry. AGNDS

should carry minimum current.

8 D6 Data Bit 6

7 D7 Data Bit 7

6 DGND Digital Ground

5 AGNDF

Analog Ground Force. Carries current

from internal analog ground connec-

tions. AGNDS and AGNDF are tied

together internally.

Feedback Resistor. Used to close the

loop around an external op amp.

__________Pin Description (MX7535)

NAME FUNCTION

1REFS Reference Voltage Sense

2 REFF

3 RFB Feedback Resistor. Used to close the

loop around an external op amp.

5 AGNDS Analog Ground Sense. Reference

point for external circuitry. This pin

should carry minimum current.

9 D12 Data Bit 12

8 D13 Data Bit 13 (MSB)

7 DGND Digital Ground

6 AGNDF

Analog Ground Force. Carries current

from internal analog ground

connections. AGNDS and AGNDF

are tied together internally.

IOUT Current Output

11 D10 Data Bit 10

10 D11 Data Bit 11

13 D8 Data Bit 8

12 D9 Data Bit 9

Reference Voltage Force

11 D3 Data Bit 3 or Data Bit 11

10 D4 Data Bit 4 or Data Bit 12

9 D5 Data Bit 5 or Data Bit 13 (MSB)

14 D0 Data Bit 0 (LSB) or Data Bit 8

13 D1 Data Bit 1 or Data Bit 9

12 D2 Data Bit 2 or Data Bit 10

17 WR Write Input. Active low.

16 A0 Address Input 0

15 A1 Address Input 1

20 VSS Bias pin for high-temperature,

low-leakage configuration

19 VDD +12V to +15V Supply-Voltage Input

18 CS Chip-Select Input. Active low.

14 D7 Data Bit 7

15 D6 Data Bit 6

16 D5 Data Bit 5

20 D1 Data Bit 1

17 D4 Data Bit 4

18 D3 Data Bit 3

19 D2 Data Bit 2

21 D0 Data Bit 0 (LSB)

22 CSMSB Chip-Select Most Significant Byte.

Active low.

23 LDAC Asynchronous Load DAC Input.

Active low.

24 CSLSB Chip-Select Least Significant Byte.

Active low.

25 WR Write Input. Active low.

28 N.C.

No Connection. Not internally connected.

26 VDD +12V to +15V Supply-Voltage Input

27 VSS Bias pin for high-temperature,

low-leakage configuration

MX7534/MX7535

_______________Detailed Description

Digital-to-Analog Section

The basic MX7534/MX7535 digital-to-analog converter

(DAC) circuit consists of a laser-trimmed, thin-film,

11-bit R-2R resistor array, a 3-bit segmented resistor

array, and NMOS current switches, as shown in Figure

2. The three MSBs are decoded to drive switches A–G

of the segmented array, and the remaining bits drive

switches S0–S10 of the R-2R array.

Binary weighted currents are switched to either AGNDF

or IOUT, depending on the status of each input bit. The

R-2R ladder current is one-eighth of the total reference

input current. The remaining seven-eighths of the cur-

rent flows in the segmented resistors, dividing equally

among these seven resistors. The input resistance at

REF is constant; therefore, it can be driven by a voltage

or current source of positive or negative polarity.

The MX7534/MX7535 are optimized for unipolar output

operation (analog output from 0V to -VREF), although

bipolar operation (analog output from +VREF to -VREF) is

possible with some added external components.

Figure 3 shows the equivalent circuit for the two DACs.

COUT varies from about 90pF to 180pF, depending on

the digital code. R0denotes the DAC’S equivalent out-

put resistance, which varies with the input code.

g(VREF,N) is the Thevenin equivalent voltage generator

due to the reference input voltage, VREF, and the trans-

fer function of the R-2R ladder, N.

Digital Section

All digital inputs are both TTL and 5V CMOS logic compat-

ible. The digital inputs are protected from electrostatic dis-

charge (ESD) with typical input currents of less than 1nA.

To minimize power-supply currents, keep digital input volt-

ages as close to 0V and 5V logic levels as possible.

__________Applications Information

Unipolar Operation (2-Quadrant

Multiplication)

Figures 4a and 4b show the circuit diagram for unipolar

binary operation. With an AC input, the circuit performs

2-quadrant multiplication. The code table for Figure 4 is

given in Table 2.

Capacitor C1 provides phase compensation and helps

prevent overshoot and ringing when high-speed op

amps are used. Note that the output polarity is the

inverse of the reference input.

Microprocessor-Compatible,

14-Bit DACs

6 _______________________________________________________________________________________

VIH + VIL

NOTES:

1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90% 

OF +5V. tR = tF = 20ns.

2) TIMING MEASUREMENT REFERENCE LEVEL IS

t5t6

t1t2

t3t4

A0,A1

DATA



t1t2

NOTES:

1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90% 

OF +5V. tR = tF = 20ns.

2) TIMING MEASUREMENT REFERENCE LEVEL IS



3) IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR, THEN IT MUST

STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH.

VIH + VIL

CSLSB

CSMSB

LDAC

DATA

Figure 1a. MX7534 Timing Diagram Figure 1b. MX7535 Timing Diagram

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

_______________________________________________________________________________________ 7

Zero-Offset Adjustment

(Figures 4a and 4b)

1) Load the DAC register with all 0s.

2) Adjust the offset of amplifier A1 so that V0(see fig-

ure) is at a minimum (i.e., ≤30µV).

Gain Adjustment

(Figures 4a and 4b)

1) Load the DAC register with all 1s.

2) Trim potentiometer R1 so that VOUT = -VIN

(

16383

)

16384

In fixed-reference applications, adjust full scale by

omitting R1 and R2 and trimming the reference voltage

magnitude. In many applications, the excellent Gain

Tempco and Gain Error specifications eliminate the

need for gain adjustment. However, if trims are

required and the DAC is to operate over a wide temper-

ature range, use low-tempco (>300ppm/°C) resistors.

Bipolar Operation

(4-Quadrant Multiplication)

Bipolar or 4-quadrant operation is shown in Figures 5a

and 5b. This configuration provides for offset binary

coding. Table 4 shows DAC codes and the corre-

sponding analog outputs for Figures 5a and 5b. With

the DAC loaded to 10 0000 0000 0000, either adjust R1

for VOUT = 0V, or omit R1 and R2 and adjust the ratio of

R5 and R6 for VOUT = 0V. Adjust the amplitude of VIN

or vary the value of R7 for full-scale trimming.

Resistors R5, R6, and R7 must be matched to 0.003%.

Mismatch of R5 and R6 causes both offset and full-

scale errors. For wide temperature range operation,

use resistors of the same material so that their tempera-

ture coefficients match and track.

2R 2R

G F E D C B A S10 S9 S0

2R 2R 2R 2R 2R 2R 2R

2R2R

R/4

RFB

IOUT

AGNDS

AGNDF

*NOTE: VALID FOR MX7535. IN MX7534, 0REFS AND 0REFF ARE REPLACED BY ONE PIN: REF.

REFS*

REFF*

R/4

–

AGNDS

AGNDF

IOUT

RFB

ILEAKAGE

g(VREF, N) COUT

Figure 2. Simplified Circuit Diagram

Figure 3. Equivalent Analog Output Circuit

Table 1. MX7534 Logic States

WR CS

A1 A2 FUNCTION

X 1 X X Device not selected (Note 1)

1 X X X No data transfer

0000

DAC loaded directly from

Data Bus (Note 2)

0001

MS Input Register loaded

from Data Bus

0010

LS Input Register loaded

from Data Bus

0011

DAC Register loaded from

Input Registers

Note 1: X = Don’t Care.

Note 2: When A1 = 0 and A0 = 0, all DAC registers are trans-

parent. By placing all 0s or all 1s on the data inputs, the

user can load the DAC to zero or full-scale output in

one write operation. This simplifies system calibration.

MX7534/MX7535

Grounding Considerations

Since IOUT and the output amplifier noninverting input

are sensitive to offset voltages, connect nodes that

must be grounded directly to a single-point ground

through a separate, very-low-resistance path. Note that

the output currents at IOUT and AGNDF vary with input

code and create code-dependent error if these termi-

nals are connected to ground (or a virtual ground)

through a resistive path.

To obtain high accuracy, it is important to use a proper

grounding technique. The two AGND pins (AGNDF‚

AGNDS) provide flexibility in this respect. In Figures 4a

and 4b, AGNDS and AGNDF are shorted together

externally and an extra op amp, A2, is not used.

Voltage-drops due to bond-wire resistance are not

compensated for in this circuit; this could create a lin-

earity error of approximately 0.1LSB due to bond-wire

resistance alone. This can be eliminated by using the

circuits shown in Figures 6a and 6b, where A2 main-

tains AGNDS at signal ground potential. By using

force/sense techniques, all switch contacts on the DAC

are kept at exactly the same potential, and any error

caused by bond-wire resistance is eliminated.

Figure 7 shows a remote voltage reference driving the

MX7535. Op amps A2 and A3 compensate for voltage

drops along the reference input line and analog

ground line.

Figure 8 shows a printed circuit board (PCB) layout with

a single output amplifier for the MX7534. The input to

REF (Pin 1) is shielded to reduce AC feedthrough, while

the digital inputs are shielded to minimize digital

feedthrough. The traces connecting IOUT and AGNDS

to the inverting and noninverting op amp inputs are

kept as short as possible. Gain trim components, R3

and R4, are omitted.

Zero-Offset Adjustment

(Figures 6a and 6b)

1) Load DAC register with all 0s.

2) Adjust offset of amplifier A2 for minimum potential at

AGNDS. This potential should be ≤30µV with respect

to signal ground.

3) Adjust A1’s offset so that VOUT is at a minimum

(i.e., ≤30µV).

Microprocessor-Compatible,

14-Bit DACs

8 _______________________________________________________________________________________

Table 2. Unipolar Binary Code Table

BINARY NUMBER IN

DAC REGISTER ANALOG OUTPUT

(VOUT)

MSB LSB

11 1111 1111 1111

10 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0000

-VIN

(

16383

)

16384

-VIN

(

8192

)

= - 1VIN

16384 2

-VIN

(

)

16384

R1

100Ω

R2

33Ω

INPUT

DATA

ANALOG

GROUND

7–14

620

2191 C1

33pF

VDD

VIN

VSS

MX7534

REF RFB

IOUT

AGNDS

AGNDF

DGND

D7–D0

17 VO



R1

20ΩR2

10Ω

INPUT

DATA

ANALOG

GROUND

LDAC

CSMSB

8–21

CSLSB

727

32261 C1

33pF

VDD

VIN

VSS

MX7535

REFF REFS RFB

IOUT

AGNDS

AGNDF

DGNDD13–DO

24 VO



Figure 4a. Unipolar Binary Operation Figure 4b. Unipolar Binary Operation

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

_______________________________________________________________________________________ 9

Gain Adjustment

(Figures 6a and 6b)

1) Load DAC register with all 1s.

2) Trim potentiometer R3 so that VOUT = -

(

16383

)

VIN

16384

Low-Leakage Configuration

Leakage current in the DAC flowing into the IOUT line

can cause gain, linearity, and offset errors. Leakage is

worse at high temperatures.

Negatively bias VSS for a high-temperature, low-leakage

configuration.

Dynamic Considerations

In static or DC applications, the output amplifier’s AC

characteristics are not critical. In higher-speed applica-

tions, where either the reference input is an AC signal

or the DAC output must quickly settle to a new pro-

grammed value, the output op amp’s AC parameters

must be considered.

Another error source in dynamic applications is the par-

asitic signal coupling from the REF terminal to IOUT.

This is normally a function of board layout and lead-to-

lead package capacitance. Signals can also be inject-

ed into the DAC outputs when the digital inputs are

switched. This digital feedthrough depends on circuit-

board layout and on-chip capacitive coupling. Minimize

layout-induced feedthrough with guard traces between

digital inputs, REF, and DAC outputs.

R1

100ΩR2, 33ΩR6

20k R7

20k

R5 10k

R8, 5k,10%



INPUT

DATA ANALOG

GROUND

A1 A2

7–14

6205

2191 C1

33pF

VIN VDD

VSS

MX7534

REF RFB

IOUT

AGNDS

AGNDF

DGNDD7–D0

17 ++





Figure 5a. Bipolar Operation

R1

20ΩR2 10Ω

R6

20k R7

20k

R5

10k

R8, 5k,10%



INPUT

DATA

ANALOG

GROUND

LDAC

A1 A2

CSMSB

8–21

CSLSB

727 6

2261 C1

33pF

VIN

VDD

VSS

MX7535

REFF REFS RFB

IOUT

AGNDS

AGNDF

DGNDD13–D0

24 +



Figure 5b. Bipolar Operation

CSMSB CSLSB LDAC WR

FUNCTION

0 1 1 0 Load MS Input Register

1 0 1 0 Load LS Input Register

0010

Load LS and MS Input

Registers

110X

Load DAC Register

from Input Register

0000

All registers are

transparent.

1 1 1 X No operation

X X 1 1 No operation

Table 3. MX7535 Logic States

Table 4. Offset Binary Bipolar Code Table

BINARY NUMBER IN

DAC REGISTER Analog Output

(VOUT)

MSB LSB

11 1111 1111 1111

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0000

+VIN

(

8191

)

8192

+VIN

(

)

8192

-VIN

(

)

8192

-VIN

(

8192

)

= -VIN

8192

Note: X = Don’t Care.

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

10 ______________________________________________________________________________________

Compensation

A compensation capacitor, C1, may be needed when

the DAC is used with a high-speed output amplifier.

The capacitor cancels the pole formed by the DAC’s

output capacitance and internal feedback resistance.

Its value depends on the type of op amp used, but typi-

cal values range from 10pF to 33pF. Too small a value

causes output ringing, while excess capacitance over-

damps the output. Minimize C1’s size and improve out-

put settling performance by keeping the PC board

trace as short as possible and stray capacitance at

IOUT as small as possible.

Bypassing

Place a 1µF bypass capacitor, in parallel with a 0.01µF

ceramic capacitor, as close to the DAC’s VDD and GND

pins as possible. Use a 1µF tantalum bypass capacitor

to optimize high-frequency noise rejection. Place a

4.7µF decoupling capacitor at VSS to minimize the DAC

output leakage current.

The MX7534/MX7535 have high-impedance digital

inputs. To minimize noise pickup, connect them to

either VDD or GND terminals when not in use. Connect

active inputs to VDD or GND through high-value resis-

tors (1MΩ) to prevent static charge accumulation if

these pins are left floating, as might be the case when

a circuit card is left unconnected.

Op-Amp Selection

Input offset voltage (VOS), input bias current (IB), and

offset voltage drift (TC VOS) are three key parameters in

determining the choice of a suitable amplifier. To main-

tain specified accuracy with VREF of 10V, VOS should

be less than 30µV and IBshould be less than 2nA.

Open-loop gain should be greater than 340,000.

Maxim’s MAX400 has low VOS (10µV max), low IB

(2nA), and low TC VOS (0.3µV/°C max). This op amp

can be used without requiring any adjustments. For

OP AMP INPUT OFFSET

VOLTAGE (VOS)INPUT BIAS

CURRENT (IB)OFFSET VOLTAGE

DRIFT (TC VOS)SETTLING

TO 0.003% FS

MAX400 10µV 2nA 0.3µV/°C 50µs

Maxim OP07 25µV 2nA 0.6µV/°C 50µs

AD554L* 500µV 25pA 5µV/°C 5µs

HA2620* 4mV 35nA 20µV/°C 0.8µs

Table 5. Amplifier Performance Comparisons

* AD544L is an Analog Devices part; HA2620 is a Harris Semiconductor part.

R4

33Ω

R3

100Ω

INPUT

DATA SIGNAL

GROUND

7–14 6205

191

C1

33pF

VDD

VSS

MX7534

REF RFB

IOUT

AGNDS

AGNDF

DGNDD7–D0

VIN

NOTE: CONTROL INPUTS OMITTED FOR CLARITY.



Figure 6a. Unipolar Binary Operation with Forced Ground

R2

10Ω

R1

20Ω

INPUT

DATA

SIGNAL

GROUND

ANALOG

GROUND

8–21 727 6

32621

C1

33pF

VDD

VSS

MX7535

REFF REFS RFB

IOUT

AGNDS

AGNDF

DGNDD13–D0

VOLTAGE

REFERENCE

NOTE: CONTROL INPUTS OMITTED FOR CLARITY.



Figure 6b. Unipolar Binary Operation with Forced Ground for

Remote Load

medium-frequency applications, the OP27 is recom-

mended. For higher-frequency applications, the HA-

2620 is recommended. However, these op amps

require external offset adjustment (Table 5).

________Microprocessor Interfacing

8086 with MX7535

The MX7534/MX7535 interface to both 8-bit and 16-bit

processors. Figure 9a shows the 8086 16-bit processor

interfacing to a single MX7535. In this setup, the double-

buffering feature of the DAC is not used. AD0–AD13 of

the 16-bit data bus are connected to the DAC data bus

(D0–D13). The 14-bit word is written to the DAC in one

MOV instruction, and the analog output responds imme-

diately. In this example, the DAC address is D000. Table

6a shows a software routine for Figure 9a.

In a multiple DAC system, the double buffering of the

DAC chips allows the user to simultaneously update all

DACs. In Figure 10, a 14-bit word is loaded to each of

the DAC’s input registers in sequence. Then, with one

instruction to the appropriate address, CS4 (i.e., LDAC)

is brought low, updating all the DACs simultaneously.

8086 with MX7534

Figure 9b shows an interface circuit to a 16-bit micro-

processor. The bottom 8 bits (AD0–AD7) of the 16-bit

data bus are connected to the DAC data bus. The

14-bit word is loaded in two bytes, using the MOV

instruction. A further MOV loads the DAC register and

causes the analog data to appear at the converter out-

put. For the example given here, the appropriate DAC

6b shows the program for loading the DAC.

8085A with MX7534

A typical interface circuit is shown in Figure 9c. The

DAC is treated as four memory locations addressed by

A0 and A1. In standard operation, three of these memo-

ry locations are used. Table 6c shows a sample pro-

gram for loading the DAC with a 14-bit word. The

MX7534 has address locations 3000–3003.

The six MSBs are written into location 3001, and eight

LSBs are written to 3002. Then, with a write instruction to

3003, the full 14-bit word is loaded to the DAC register.

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

______________________________________________________________________________________ 11

INPUT

DATA

8–21 727 6

2261 C1

33pF

VDD

VSS

VDD

MX7535

REFF REFS RFB

IOUT

AGNDS

AGNDF

DGNDD13–D0

NOTE: CONTROL INPUTS OMITTED FOR CLARITY.



Figure 7. Driving the MX7535 with a Remote Voltage Reference

AGND

DGND

REF

PIN 1 AD544*

OUTPUT

VSS

VDD

C1 LOCATION

V+ V-

NOTE:

LAYOUT IS FOR DOUBLE-SIDED

PCB. BOLD LINE INDICATES

TRACK ON COMPONENT SIDE.

*AD544 IS AN ANALOG DEVICES PART.



PIN 1 MX7534

Figure 8. Suggested Layout for MX7534 Incorporating Output

Amplifier

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

12 ______________________________________________________________________________________

MC68000 with MX7535

Figure 11a shows an interface diagram. The following

routine writes data to the DAC input registers and then

outputs the data via the DAC register:

01000 MOVE.W #W,D0 DAC data, W, loaded

into Data Register 0.

MOVE.W D0,$E000 Data W transferred

between D0 and DAC

MOVE.B #228,D7 Control returned to the

System.

TRAP #14 Monitor Program

MC68000 with MX7534

Figure 11b shows the MC68000 interface diagram. The

following routine writes data to the DAC input registers

and then outputs the data via the DAC register:

.A2 E003 Address Register 2

loaded with E003.

01000 MOVE.W #W,D0 DAC data, W, loaded

into Data Register 0.

MOVEP.W D0,$0000

(A2)

Data W transferred

between D0 and the

DAC’s Input Register.

High-ordered byte trans-

ferred first. Memory

address specified using

the address register

indirect plus displace-

ment addressing mode.

Address used here

(E003) is odd, so data is

transferred on the low-

order half of the data

bus (D0–D7).

MOVE.W D0,$E006 This instruction provides

appropriate signals to

transfer data W from

the DAC Input Register

to the DAC Register,

which controls the R-2R

ladder switches.

MOVE.B #228,D7 Control returned to the

System.

TRAP #14 Monitor Program

Since this interfacing system uses only the lower half of

the data bus, it is also suitable for use with the

MC68008, which provides the user with an 8-bit data

bus instead of the MC68000’s 16-bit bus.

ADDRESS

DECODE

LATCH

ADDRESS BUS

D0–D7

A1 A0

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

A8–A15

8085A

DATA BUS

AD0–AD7

Figure 9c. MX7534—8085A Interface Circuit

ADDRESS

DECODE

16-BIT

LATCH

ADDRESS BUS

DATA BUS

ALE

8086

D0–D7

A1 A0

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

AD0–AD15

Figure 9b. MX7534—8086 Interface Circuit

ADDRESS

DECODE

16-BIT

LATCH

ADDRESS BUS

DATA BUS

ALE

8086 LDAC

CSLSB

CSMSB

D0–D13

AD13

AD0

MX7535*



*SOME CIRCUITRY OMITTED FOR CLARITY

AD0–AD15



Figure 9a. MX7535—8086 Interface Circuit

Z80 with MX7534/MX7535

Figure 12a is an interface circuit for the Z80, using the

MX7535. This is an example of an 8-bit processor inter-

face for these DACs. Figure 12b shows the schematic

for the MX7534.

MC6809 with MX7534

Figure 13a shows an interface circuit that enables the

MX7534 to be programmed using the MC6809 8-bit

microprocessor. Use the 16-bit D accumulator to simplify

data transfer. The two key processor instructions are:

LDD Load D accumulator from memory

STD Store D accumulator to memory

MC6502 with MX7534

Figure 13b shows an interface diagram for the MC6502

using the MX7534.

________________Digital Feedthrough

In the interface diagrams shown in Figures 9–13, the

digital inputs of the DAC are directly connected to the

microprocessor bus. Even when the device is not

selected, activity on the bus can feed through on the

DAC output through package capacitance and appear

as noise. To minimize noise, isolate the DACs from the

digital bus, as shown in Figures 14a and 14b.

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

______________________________________________________________________________________ 13

ASSUME DS:DACLOAD,CS:DACLOAD

DACLOAD SEGMENT AT 000

8CC9

8ED9

BF00D0

C705“YZWX”

EA0000

00FF

MOV CX,CS

MOVDS,CX

MOVDI,#D000

MOV MEM,#YZWX

:DEFINE DATA SEGMENT REGISTER EQUAL

:TO CODE SEGMENT REGISTER

:LOAD DI WITH D000

:DAC LOADED WITH WXYZ

:CONTROL IS RETURNED TO THE MONITOR PROGRAM

ASSUME DS:DACLOAD,CS:DACLOAD

DACLOAD SEGMENT AT 000

8CC9

8ED9

BF02D0

C605“MS”

C605“LS”

C60500

EA0000

MOV CX,CS

MOVDS,CX

MOVDI.#D002

MOV MEM,#“MS”

INC DI

MOV MEM,#“LS”

INC DI

MOV MEM,#00

JMP MEM

:DEFINE DATA SEGMENT REGISTER EQUAL

:TO CODE SEGMENT REGISTER

:LOAD DI WITH D002

:DAC LOADED WITH “MS”

:LS INPUT REGISTER LOADED WITH “LS”

:CONTENT OF INPUT REGISTERS ARE LOADED TO THE DAC REGISTER

:CONTROL IS RETURNED TO THE MONITOR PROGRAM

Table 6a. Sample Program for Loading the MX7535

Table 6b. Sample Program for Loading the MX7534 from 8086

2000

200D

“MS”

“LS”

MVIH,#30

MVIL,#01

MVIA,#“MS”

MOV M,A

INR L

MVI A#“LS”

MOV M,A

INR L

MOV M,A

RST I

Table 6c. Sample Program for Loading

the MX7534 from 8085A

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

14 ______________________________________________________________________________________

ADDRESS

DECODE

ADDRESS BUS

DATA BUS

DTACK

A1–A23

MC68000 LDAC

CSLSB

CSMSB

D0–D13

D0–D15

MX7535*



*SOME CIRCUITRY OMITTED FOR CLARITY

R/W



Figure 11a. MX7535—MC68000 Interface

ADDRESS

DECODE

ADDRESS BUS

DATA BUS

DTACK

A1–A23

A1A0

D0–D7

A2A1

MC68000 CS

D0–D7

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

R/W

Figure 11b. MX7534—MC68000 Interface

CSMSB

D0–D13

LDAC

CSLSB

ADDRESS

DECODE

16-BIT

LATCH

ADDRESS BUS

CSMSB

CSLSB

LDAC

CS4 CS2

CS1

D0–D13

MX7535*



MX7535*



MX7535*



*SOME CIRCUITRY OMITTED FOR CLARITY

ALE

8086

AD0–AD15

CSMSB

CSLSB

LDAC

DATA BUS

CS3

Figure 10. MX7535—8086 Interface: Multiple DAC Systems

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

______________________________________________________________________________________ 15

ADDRESS

DECODE CS

D0–D7

A0 A1

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

A0–A15

MC6809

D0–D7

R/W

DATA BUS

Figure 13a. MX7534—MC6809 Interface Circuit

ADDRESS

DECODE

ADDRESS BUS

D0–D7

A0 A1

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

A0–A15

6502

D0–D7

R/W

∅2

DATA BUS 



Figure 13b. MX7534—6502 Interface

EN

QUAD LATCH

EN

QUAD LATCH

EN

QUAD LATCH

ADDRESS

DECODE

MICRO-

PROCESSOR

SYSTEM

A0–A15

A1 CS

A0 A1

D0–D7

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY



Figure 14a. MX7534—Interface Circuit Using Latches to

Minimize Digital Feedthrough

ADDRESS

DECODE

EN



16-BIT

LATCH

CSMSB

D0–D13

MX7535*



*SOME CIRCUITRY OMITTED FOR CLARITY

CSLSB

LDAC

A0–A15

MICRO-

PROCESSOR

SYSTEM

D0–D15

Figure 14b. MX7535—Interface Circuit Using Latches to

Minimize Digital Feedthrough

ADDRESS

DECODE

ADDRESS BUS

DATA BUS

MREQ

Z80

A0–A15

LDAC

CSMSB

CSLSB

D0–D7

D8–D13

D8–D7

MX7535*



*SOME CIRCUITRY OMITTED FOR CLARITY

Figure 12a. MX7535—Z80 Interface

ADDRESS

DECODE CS

D0–D7

A0 A1

MX7534*



*SOME CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

A0–A15

Z80

D0–D7

MREQ

DATA BUS

Figure 12b. MX7534—Z80 Interface

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

MX7534/MX7535

Microprocessor-Compatible,

14-Bit DACs

_Ordering Information (continued)

Dice are tested at +25°C, DC parameters only.



MX7535

DAC REGISTER

MS

INPUT

LS

INPUT

8–21



14-BIT DAC

REFS 2

REFF

RFB

IOUT

AGNDS

AGNDF

LDAC

CSMSB

VDD

D13–D0 DGND VSS

CSLSB



__ _ Functional Diagrams (continued)

N.C.

VSS

VDD

CSLSB

LDAC

CSMSB

D0 (LSB)

D10

D11

D12

(MSB) D13

DGND

AGNDF

AGNDS

IOUT

RFB

REFF

REFS

DIP/SO/PLCC/Ceramic SB

TOP VIEW

MX7535

_____Pin Configurations (continued)

±228 Ceramic SB-55°C to +125°CMX7535SD ±128 Ceramic SB-55°C to +125°CMX7535TD ±228 CERDIP-55°C to +125°CMX7535SQ ±128 CERDIP-55°C to +125°CMX7535TQ ±228 Wide SO-40°C to +85°CMX7535JEWI ±128 Wide SO-40°C to +85°CMX7535KEWI ±228 Ceramic SB-25°C to +85°CMX7535AD ±128 Ceramic SB-25°C to +85°CMX7535BD ±228 CERDIP-25°C to +85°CMX7535AQ ±128 CERDIP-25°C to +85°CMX7535BQ ±2Dice*0°C to +70°CMX7535J/D ±228 PLCC0°C to +70°CMX7535JP ±128 PLCC0°C to +70°CMX7535KP ±228 Wide SO0°C to +70°CMX7535JCWI ±128 Wide SO0°C to +70°CMX7535KCWI ±228 Plastic DIP0°C to +70°CMX7535JN ±128 Plastic DIP0°C to +70°C

MX7535KN INL (LSBs)PIN PACKAGETEMP. RANGEPART