G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 1 -
Features : Description :
∗ 65,536 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual
CAS
Input.
∗ Low power dissipation.
∗ Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ and 40/44
pin TSOP (II).
∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
The GLT41016 is a 65,536 x 16 bit high-
performance CMOS dynamic random access
memory. The GLT41016 offers Fast Page
mode with Extended Data Output, and has
both BYTE WRITE and WORD WRITE
access cycles via two
CAS
pins. The
GLT41016 accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 256 x 16 bits, within a page, with cycle
times as short as 12ns.
The GLT41016 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE 30 35 40 45
Max.
RAS
Access Time, (tRAC)30 ns 35 ns 40 ns 45 ns
Max. Column Address Access Time, (tAA)15 ns 18 ns 20 ns 22 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)12 ns 13 ns 15 ns 18 ns
Min. Read/Write Cycle Time, (tRC)65 ns 70 ns 75 ns 80 ns
Max.
CAS
Access Time (tCAC)10 ns 11 ns 12 ns 12 ns
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 2 -
Pin Configuration :
Pin Descriptions:
Name Function
A0 - A7Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
DQ0 - DQ15 Data Inputs / Outputs
VCC +5V Power Supply
VSS Ground
NC No Connection
GLT41016
SOJ Top View TSOP(Type II)
Top View
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 3 -
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
.......................................-0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
CIN1
CIN2
COUT
Parameter
Address Input
RAS
,
LCAS
,
UCAS
,
WE
,
OE
Data Input/ Output
Max.
5
7
7
Unit
pF
pF
pF
*Note: Operation above Absolute Maximum Ratings
can adversely affect device reliability. *Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
CAS
means
UCAS
and
LCAS
.
l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 4 -
Extended Data Output (EDO) Page Mode
The EDO page mode is a kind of page mode with enhanced features. The two major features
of the EDO page mode are as follows.
1. Data output time is extended.
In the EDO page mode, the output data is held to the next
CAS
cycle‘s falling edge,
instead of the rising edge. For this reason, valid data output time in the EDO page mode is
extended compared with the fast page mode (=data extend function). In the fast page mode,
the data output time becomes shorter as the
CAS
cycle time becomes shorter. Therefore, in
the EDO page mode, the timing margin in read cycle is larger than of the fast page mode
even if the
CAS
cycle time becomes shorter.
2. The
CAS
cycle time in the EDO page mode is shorter than that in the fast page mode.
In the EDO page mode, due to the data extend function, the
CAS
cycle time can be
shorter than in the fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60ns as an example, the
CAS
cycle time in the EDO page
mode is 25ns while that in the fast page mode is 40ns.
In the EDO page mode, read (data out) and write (data in) cycles can be executed
repeatedly during one
RAS
cycle. The EDO page mode allows both read and write
operations during one cycle, but the performance is equivalent to that of the fast page mode
in that case.
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 5 -
Truth Table: GLT41016
Function
RAS
CASL
CASH
WE
OE
ADDRESS DQs Notes
Standby HH→XH→XX X High-Z
Read: Word L L L HLROW/COL Data Out
Read: Lower Byte L L H H LROW/COL Lower Byte,Data-
Out
Upper Byte,High-Z
Read: Upper Byte LHLHLROW/COL Lower Byte,High-Z
Upper Byte,Data-
Out
Write: Word(Early Write) L L L L XROW/COL Data-In
Write: Lower Byte (Early) L L HLXROW/COL Lower Byte,Data-In
Upper Byte,High-Z
Write: Upper Byte (Early) LHL L XROW/COL Lower Byte,High-Z
Upper Byte,Data-In
Read Write L L L H→L L→HROW/COL Data-Out,Data-In 1,2
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
H
H
L
L
ROW/COL
COL
Data-Out
Data-Out
1
1
EDO-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
L
L
X
X
ROW/COL
COL
Data-In
Data-In
2
2
EDO-Page-
Mode Read-
Write
1st Cycle
2nd Cycle
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
COL
Data-Out,Data-In
Data-Out,Data-In
1,2
1,2
Hidden
Refresh Read
Write
L→H→L
L→H→L
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
Data-Out
Data-In
1
2,3
RAS
-Only Refresh LH H X X ROW High-Z
CBR Refresh H→LL L X X High-Z 4
Notes:
1. These READ cycles may also be BYTE READ cycles (either
UCAS
or
LCAS
active).
2. These WRITE cycles may also be BYTE READ cycles (either
UCAS
or
LCAS
active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (
UCAS
or
LCAS
).
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 6 -
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym
.Parameter Test Conditions Access
Time Min. Typ Max. Unit Notes
ILI Input Leakage Current
(any input pin) 0V ≤ VIN ≤ 5.5V
(All other pins not under
test=0V)
-10 +10 µA
ILO Output Leakage Current
(for High-Z State) 0V ≤ Vout ≤ 5.5V
Output is disabled (Hiz) -10 +10 µA
I
CC1
Operating Current,
Random READ/WRITE tRC = tRC (min.) tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA 1,2
I
CC2
Standby Current,(TTL)
RAS
,
UCAS
,
LCAS
at
VIH other inputs ≥VSS 4mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
UCAS
,
LCAS
at VIH
tRC = tRC (min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA 2
I
CC4
Operating Current,
EDO Page Mode
RAS
at VIL,
UCAS
,
LCAS
address
cycling: tPC = tPC(min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA 1,2
I
CC5
Refresh Current,
CAS Before
RAS
RAS
,
UCAS
,
LCAS
address cycling:
tRC = tRC (min.)
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
mA 1
I
CC6
Standby Current, (CMOS)
RAS
≥VCC-0.2V,
UCAS
≥VCC-0.2V,
LCAS
≥VCC-0.2V,
All other inputs VSS
2mA
VIL Input Low Voltage -1 +0.8 V3
VIH Input High Voltage 2.4 V
CC
+1 V3
VOL Output Low Voltage IOL = 4.2mA 0.4 V
V
OH
Output High Voltage IOH = -5mA 2.4 V
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output
open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one
transition per address cycle in random Read/Write and EDO Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to
exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 7 -
AC Characteristics
TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V
An initial pause of 100 µs and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
30 35 40 45
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time tRC 65 70 75 80 ns
Read Modify Write Cycle Time tRWC 90 95 100 103 ns
RAS
Precharge Time tRP 25 25 25 30 ns
RAS
Pulse Width tRAS 30 100k 35 100k 40 100k 45 100k ns
Access Time from
RAS
tRAC 30 35 40 45 ns 1,2,3
Access Time from
CAS
tCAC 10 11 12 12 ns 1,5,10
Access Time from Column Address tAA 15 18 20 22 ns 1,5,6
CAS
to Output Low-Z tCLZ 0 0 0 0 ns
CAS
to Output High-Z tCEZ 3 8 3 8 3 8 3 8 ns
RAS
Hold Time tRSH 10 12 12 13 ns
RAS
Hold Time Referenced to
OE
tROH 7 8 8 9 ns
CAS
Hold Time tCSH 25 30 34 40 ns
CAS
Pulse Width tCAS 610k 610k 610K 710K ns
RAS
to CAS Delay Time tRCD 13 20 17 24 18 28 18 33 ns
RAS
to Column Address Delay Time tRAD 10 15 12 17 13 20 13 23 ns 7
CAS
to
RAS
Precharge Time tCRP 5 5 5 5 ns
Row Address Set-Up Time tASR 0 0 0 0 ns
Row Address Hold Time tRAH 6 7 8 8 ns
Column Address Set-Up Time tASC 0 0 0 0 ns
Column Address Hold Time tCAH 6 6 6 6 ns
Column Address to
RAS
Lead Time tRAL 15 18 20 23 ns
Column Address Hold Time Referenced to
RAS
tAR 26 30 34 39 ns
Read Command Set-Up Time tRCS 0 0 0 0 ns
Read Command Hold Time Referenced to
CAS
tRCH 0 0 0 0 ns 4
Read Command Hold Time Referenced to
RAS
tRRH 0 0 0 0 ns 4
Write Command Set-Up Time tWCS 0 0 0 0 ns 8,9
Write Command Hold Time tWCH 6 6 6 6 ns
Write Command Pulse Width tWP 6 6 6 6 ns
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 8 -
AC Characteristics 30 35 40 45
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Write Command to
RAS
Lead Time tRWL 10 11 12 12 ns
Write Command to
CAS
Lead Time tCWL 10 11 12 12 ns
Data Set-Up Time tDS 0 0 0 0 ns
Data Hold Time tDH 6 7 8 8 ns
Data Hold Time Referenced to
RAS
tDHR 26 31 36 41 ns
RAS
to
WE
Delay Time tRWD 44 49 54 59 ns
CAS
to
WE
Delay Time tCWD 22 23 24 24 ns
Column Address to WE Delay Time tAWD 25 30 32 34 ns
RAS
to
CAS
Precharge Time tRPC 0 0 0 0 ns
Access Time from
CAS
Precharge tCPA 17 20 22 24 ns
EDO Page Mode Cycle Time tPC 12 13 15 18 ns
EDO Page Mode Read-Modify-Write Cycle Time tPRWC 43 47 50 52 ns
CAS
Precharge Time (EDO Page Mode) tCP 5 5 5 7 ns
RAS
Pulse Width (EDO Page Mode Only) tRASP 30 100k 35 100k 40 100k 45 100k ns
Access Time from
OE
tOEA 10 11 12 12 ns
OE
to Data Delay Time tOED 8 8 8 8 ns
OE
to Output High-Z tOEZ 3 8 3 8 3 8 3 8 ns
OE
Command Hold Time tOEH 6 6 7 7 ns
Data Output Hold after
CAS
low tDOH 3 3 3 5 ns
RAS
to Output High-Z tREZ 3 8 3 8 3 8 3 8 ns
WE
to Output High-Z tWEZ 3 10 3 10 3 10 3 10 ns
OE
to
CAS
Hold Time tOCH 8 8 8 8 ns
CAS
Hold Time to
OE
tCHO 8 8 8 8 ns
OE
Precharge Time tOEP 8 8 8 8 ns
CAS
Set-Up Time for
CAS
-before-
RAS
Cycle tCSR 10 10 10 10 ns
CAS
Hold Time for
CAS
-before-
RAS
Cycle tCHR 10 10 10 10 ns
Transition Time tT1.5 50 2 50 2 50 2 50 ns
Refresh Period tREF 4 4 4 4 ms
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 9 -
Notes:
1. Measure with a load equivalent to two TTL inputs and 50 pF.
2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA
dominant.
3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be
controlled by tCAC.
4. Either tRRH or tRCH must be satisfied for a Read Cycle.
5. Access time is determined by the longest of tAA, tCAC and tCPA.
6. Assumes that tRAD ≥ tRAD (max.).
7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.)
is specified as a reference point only. If tRAD is greater than the specified tRAD (max.)
limit, the access time is controlled by tAA and tCAC.
8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
9. tWCS (min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of
CAS
of
WE
.
11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 10 -
Read CYCLE
Note : DIN = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 11 -
Early Write Cycle
NOTE : DOUT = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 12 -
OE
Controlled Write Cycle
NOTE : DOUT = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 13 -
Read - Modify - Write Cycle
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 14 -
EDO Page Mode Read Cycle
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 15 -
EDO Page Mode Early Write Cycle
NOTE : DOUT = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 16 -
EDO Page Mode Read - Modify - Write Cycle
NOTE : DOUT = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 17 -
CAS
- Before -
RAS
Refresh Cycle
RAS-Only Refresh Cycle
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 18 -
Hidden Refresh Cycle ( Read )
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 19 -
Hidden Refresh Cycle ( Write )
NOTE : DOUT = OPEN
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 20 -
CAS
-Before-
RAS
Refresh Counter Test Cycle
Ordering Information
Read Cycle
Write Cycle
Read-Modify-Write
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 21 -
Part Number SPEED POWER FEATURE PACKAGE
GLT41016-30J4 30ns Normal EDO SOJ 400mil 40L
GLT41016-35J4 35ns Normal EDO SOJ 400mil 40L
GLT41016-40J4 40ns Normal EDO SOJ 400mil 40L
GLT41016-45J4 45ns Normal EDO SOJ 400mil 40L
GLT41016-30TC 30ns Normal EDO TSOP 400mil 44L
GLT41016-35TC 35ns Normal EDO TSOP 400mil 44L
GLT41016-40TC 40ns Normal EDO TSOP 400mil 44L
GLT41016-45TC 45ns Normal EDO TSOP 400mil 44L
Parts Numbers (Top Mark) Definition :
GLT 4 10 16 - 40 J4
Note : CÙCDROM , HÙHDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 22 -
Package Information
400mil 40 pin Small Outline J-form Package (SOJ)
G-LINK GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 23 -
40/44 Lead Thin Small Outline Package TSOP(Type II)
