3 kV RMS Signal and Power Isolated RS-485 Transceiver with 15 kV IEC ESD Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E FEATURES GENERAL DESCRIPTION 3 kV rms isolated RS-485/RS-422 transceiver Low radiated emissions, integrated, isolated dc-to-dc converter Passes EN 55032 Class B with margin on a 2-layer PCB Cable invert smart feature Correct reversed cable connection on A, B, Y, and Z bus pins while maintaining full receiver fail-safe feature ESD protection on RS-485 A, B, Y and Z pins 12 kV IEC61000-4-2 contact discharge 15 kV IEC61000-4-2 air discharge High speed 25 Mbps data rate (ADM2565E/ADM2567E) Low speed 500 kbps data rate for EMI control (ADM2561E/ADM2563E) Flexible power supplies Input VCC supply of 3 V to 5.5 V Logic VIO supply of 1.7 V to 5.5 V VSEL pin to select VISO supply of 5 V (VCC > 4.5 V) or 3.3 V PROFIBUS compliant for 5 V VISO Wide operating temperature range: -40C to +105C High common-mode transient immunity: 250 kV/s Short-circuit, open-circuit, and floating input receiver fail-safe Supports 192 bus nodes (72 k receiver input impedance) Full hot swap support (glitch free power-up/power-down) Safety and regulatory approvals (pending) CSA Component Acceptance Notice 5A, DIN V VDE V 088411, UL 1577, CQC11-471543-2012, IEC 61010-1 Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E) 28-lead, fine pitch SOIC_W package (10.15 mm x 10.05 mm) with >8.0 mm creepage and clearance The ADM2561E, ADM2563E, ADM2565E, and ADM2567E are 3 kV rms signal and power isolated RS-485 transceivers. These devices are designed for balanced transmission lines and comply with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E). The devices pass radiated emissions testing to the EN 55032 Class B standard with margin on a 2-layer printed circuit board (PCB) using two small external 0402 ferrites on isolated power and ground pins. The device features an integrated, low electromagnetic interference (EMI), isolated dc-to-dc converter, which eliminates the need for an external isolated power supply. The isolation barrier provides immunity to system level electromagnetic compatibility (EMC) standards. The family of isolator devices features 12 kV contact and 15 kV air IEC61000-4-2 ESD protection on the RS-485 A, B, Y, and Z pins. The devices also features cable invert pins, allowing the user to quickly correct reversed cable connection on the A, B, Y, and Z bus pins while maintaining full receiver fail-safe performance. Slew rate limited versions are available, which are optimized for low speed over long cable runs, and have a maximum data rate of 500 kbps. Half duplex and full duplex variants are available. The full duplex generics allow independent cable inversion of the driver and receiver for additional flexibility. Table 18 shows the summary description of each generic. APPLICATIONS Heating, ventilation, and air conditioning (HVAC) networks Industrial field buses Building automation Utility networks Energy meters Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Robust Low Power Digital Isolator.......................................... 20 Applications ...................................................................................... 1 High Driver Differential Output Voltage ............................... 20 General Description ......................................................................... 1 IEC61000-4-2 ESD Protection ................................................. 20 Revision History ............................................................................... 2 Truth Tables ................................................................................ 21 Functional Block Diagrams............................................................. 3 Receiver Fail-Safe ....................................................................... 22 Specifications .................................................................................... 4 Driver And Receiver Cable Inversion ..................................... 22 Timing Specifications .................................................................. 6 Hot Swap Inputs ......................................................................... 22 Package Characteristics ............................................................... 9 192 Transceivers on the Bus ..................................................... 23 Regulatory Information............................................................... 9 Driver Output Protection ......................................................... 23 Insulation and Safety Related Specifications ............................ 9 1.7 V To 5.5 V VIO Logic Supply .............................................. 23 DIN VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) .......................................................... 10 Applications Information ............................................................. 24 Absolute Maximum Ratings ......................................................... 11 Device Power-Up ....................................................................... 24 Thermal Resistance .................................................................... 11 Maximum Data Rate vs. Ambient Temperature ................... 24 Electrostatic Discharge (ESD) Ratings .................................... 11 Isolated PROFIBUS Solution ................................................... 25 ESD Caution................................................................................ 11 EMC, EFT, and Surge ................................................................ 25 Pin Configurations and Function Descriptions ......................... 12 Insulation Lifetime ..................................................................... 25 Typical Performance Characteristics ........................................... 14 Typical Applications .................................................................. 26 Test Circuits .................................................................................... 19 Outline Dimensions ....................................................................... 28 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 28 PCB Layout and Electromagnetic Interference (EMI) ......... 24 Low EMI Integrated DC-to-DC Converter ............................ 20 REVISION HISTORY 8/2020--Rev. A to Rev. B Changed ADM2565E Status and ADM2567E Status from Pending to Released ............................................................Throughout Changes to Features Section and General Description Section ....... 1 Changes to Table 5................................................................................... 9 Changes to 192 Transceivers on the Bus Section ....................... 23 Changes to Ordering Guide .......................................................... 28 Deleted Pending Products Section and Table 22 ....................... 29 6/2020--Rev. 0 to Rev. A Changes to General Description Section .......................................1 Changes to DIN VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) Section ................................................ 10 Changes to Table 8 ......................................................................... 11 Added Electrostatic Discharge (ESD) Ratings Section, ESD Ratings for ADM2561E/ADM2563E/ADM2565E/ADM2567E Section, and Table 11; Renumbered Sequentially...................... 11 Changes to Ordering Guide .......................................................... 28 Changes to Table 21 ....................................................................... 29 5/2020--Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E FUNCTIONAL BLOCK DIAGRAMS VCC VISOIN VISOOUT OSCILLATOR RECTIFIER REGULATOR LOW RADIATED EMISSIONS DC-TO-DC VIO DIGITAL ISOLATOR iCoupler RS-485 TRANSCEIVER RxD DECODE ENCODE INVR ENCODE DECODE ENCODE DECODE R IEC61000-4-2 ESD PROTECTION RE CABLE INVERT INVD TxD DE ENCODE D DECODE A B Z Y GND1 GNDISO 22764-001 ADM2563E/ADM2567E ISOLATION BARRIER GND2 Figure 1. ADM2563E/ADM2567E VCC VISOOUT OSCILLATOR VISOIN RECTIFIER REGULATOR LOW RADIATED EMISSIONS DC-TO-DC V IO DIGITAL ISOLATOR iCoupler RS-485 TRANSCEIVER RxD DECODE ENCODE DE ENCODE DECODE TxD ENCODE DECODE INV ENCODE DECODE R CABLE INVERT D IEC61000-4-2 ESD PROTECTION B A ADM2561E/ADM2565E GND1 ISOLATION BARRIER GNDISO Figure 2. ADM2561E/ADM2565E Rev. B | Page 3 of 28 GND2 22764-101 RE ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet SPECIFICATIONS All voltages are relative to their respective ground: 3.0 V VCC 5.5 V, 1.7 V VIO 5.5 V, TMIN (-40C) to TMAX (+105C). All minimum and maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VCC = VIO = 5 V, VISOOUT output voltage (VISO) = 3.3 V (VSEL = GNDISO), unless otherwise noted. All parameters are characterized with a BLM15HD182SN1 ferrite bead between the VISOOUT and VISOIN pins, and between the GNDISO and GND2 pins. Table 1. Parameter PRIMARY SUPPLY CURRENT VCC Supply Current--Unloaded VIO Logic Supply Current ISOLATED SUPPLY CURRENT ADM2561E/ADM2563E (Data Rate = 500 kbps) ADM2565E/ADM2567E (Data Rate = 25 Mbps ) ISOLATED DC-TO-DC CONVERTER VISOOUT Output Voltage Output Current Available from VISOOUT Supply Pin VCC Minimum Start-Up Voltage Start-Up Time DRIVER Differential Output Voltage Loaded Over Common-Mode Range |VOD2| for Complementary Output States Common-Mode Output Voltage |VOC| for Complementary Output States Short-Circuit Output Current Output Leakage Current (Y, Z) 2 Pin Capacitance (A, B, Y, Z) RECEIVER Differential Input Threshold Voltage, Noninverted Differential Input Threshold Voltage, Inverted Input Voltage Hysteresis Input Current (A, B) Symbol Min Typ Max Unit Test Conditions/Comments 21 28 20 26 0.65 5 46 48 53 51 0.9 8 mA mA mA mA mA mA VSEL = GNDISO (DE = 0 V) VCC 4.5 V, VSEL = VISO (DE =0 V) VSEL = GNDISO (DE = VIO) VCC 4.5 V, VSEL = VISO (DE = VIO) DE = 0 V DE = VIO 50 75 55 75 mA VISOIN = 3 V to 3.465 V, 54 between Y and Z 3 3.3 3.465 V 4.5 5.0 5.25 V mA VSEL = GNDISO, IISOOUT = 10 mA minimum to 55 mA maximum 1 VCC 4.5 V, VSEL = VISO, IISOOUT = 10 mA minimum to 90 mA maximum1 VCC 4.5 V, VSEL = VISO, VISO 4.5 V V ms DE = GND1, see the Device Power-Up section DE = GND1, see the Device Power-Up section ICC IIO IISOIN VISO IISOOUT 90 VSTART tSTART 3.135 |VOD2| 2.0 2.4 VISO V VCC 3.0 V, VSEL = GNDISO, RL = 100 , see Figure 40 |VOD3| 1.5 2.1 1.5 2 3.1 1.9 VISO VISO VISO V V V 2.1 3.1 VISO 0.2 V V VCC 3.0 V, VSEL = GNDISO, RL = 54 , see Figure 40 VCC 4.5 V, VSEL = VISO, RL = 54 , see Figure 40 VCC 3.0 V, VSEL = GNDISO, -7 V common-mode voltage (VCM) 12 V, see Figure 41 VCC 4.5 V, VSEL = VISO, -7 V VCM 12 V, see Figure 41 RL = 54 or 100 , see Figure 40 1.5 3.0 0.2 V V RL = 54 or 100 , see Figure 40 RL = 54 or 100 , see Figure 40 +250 50 mA A A pF -7 V output voltage (VO) +12 V DE = RE = 0 V, VCC = 0 V or 5.5 V, VIN = 12 V DE = RE = 0 V, VCC = 0 V or 5.5 V, VIN = -7 V Input voltage (VIN) = 0.4sin(10t x 106) 10 |VOD2| VOC |VOC| IOS IO -250 -50 1 10 28 -200 -125 -30 mV -7 V VCM +12 V, INV/INVR = 0 V 30 125 200 mV -7 V VCM +12 V, INV/INVR = VIO mV A A pF -7 V VCM +12 V DE = 0 V, VCC = powered/unpowered, VIN = 12 V DE = 0 V, VCC = powered/unpowered, VIN = -7 V Input voltage (VIN) = 0.4sin(10t x 106) CIN VTH VHYS II 25 167 -133 Pin Capacitance (A, B) VISOIN = 3 V to 3.465 V, 54 between Y and Z CIN 4 Rev. B | Page 4 of 28 Data Sheet Parameter DIGITAL LOGIC INPUTS Input Low Voltage Input High Voltage Input Leakage Current RxD DIGITAL OUTPUT Output Low Voltage Output High Voltage Short-Circuit Current Three-State Output Leakage Current COMMON-MODE TRANSIENT IMMUNITY 3 ADM2561E/ADM2563E/ADM2565E/ADM2567E Symbol VIL VIH II Min 0.7 x VIO -1 -1 Typ 0.1 10 VOL VOH 2.4 2.0 VIO - 0.2 IOZR -1 CMTI 250 +0.01 Max Unit Test Conditions/Comments 0.3 x VIO 2 30 V V A A DE, RE, TxD, INV, INVR, INVD DE, RE, TxD, INV, INVR, INVD DE, RE, TxD, VIN = 0 V or VIO INV, INVR, INVD, VIN = 0 V or VIO 0.4 V 0.4 0.2 V V V V V mA A VIO = 2.7 V, IOUT = 1.0 mA, VID -0.2 V VIO = 1.95 V, IOUT = 500 A, VID -0.2 V VIO = 3.0 V, IOUT = -2.0 mA, VID -0.03 V VIO = 2.3 V, IOUT = -1.0 mA, VID -0.03 V VIO = 1.7 V, IOUT = -500 A, VID -0.03 V VO = 0 V or VIO, RE = 0 V RE = VIO, RxD = 0 V or VIO kV/s VCM 1 kV, transient magnitude measured at between 20% and 80% of VCM, see Figure 46 and Figure 47 100 +1 VIO = 3.6 V, output current (IOUT) = 2.0 mA, differential input voltage (VID) -0.2 V These parameters include the voltage drop across the dc resistance of the BLM15HD182SN1 ferrite beads. The ADM2563E and ADM2567E only. 3 CMTI is the maximum common-mode voltage slew rate that can be sustained while maintaining specification compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. B | Page 5 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet TIMING SPECIFICATIONS ADM2565E/ADM2567E All minimum and maximum specifications apply over the entire recommended operation range, VCC = 3.0 V to 5.5 V, VIO = 1.7 V to 5.5 V, TA = TMIN (-40C) to TMAX (+105C). All typical specifications are at TA = 25C, VCC = VIO = 5 V, VISO = 3.3 V (VSEL = GNDISO). All parameters are characterized with a BLM15HD182SN1 ferrite bead between the VISOOUT and VISOIN pins, and between the GNDISO and GND2 pins. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay Output Skew Rise Time/Fall Time Enable Time Disable Time RECEIVER Propagation Delay Output Skew Enable Time Disable Time RECEIVER CABLE INVERT, INVR Propagation Delay High to Low Low to High DRIVER CABLE INVERT, INVD Propagation Delay High to Low Low to High Symbol Min Typ Max Unit Test Conditions/Comments tDPLH, tDPHL tSKEW tDR, tDF tZL, tZH tLZ, tHZ 18 1.5 4.5 25 20 25 5 10 40 40 Mbps ns ns ns ns ns RL = 54 , CL1 = C L2 = 100 pF, see Figure 3 and Figure 42 RL = 54 , CL1 = CL2 = 100 pF, see Figure 3 and Figure 42 RL = 54 , CL1 = CL2 = 100 pF, see Figure 3 and Figure 42 RL = 110 , CL = 50 pF, see Figure 5 and Figure 43 RL = 110 , CL = 50 pF, see Figure 5 and Figure 43 tRPLH, tRPHL tSKEW tZL, tZH tLZ, tHZ 32 2 4 8 50 6 25 25 ns ns ns ns CL = 15 pF, see Figure 4 and Figure 44 CL = 15 pF, see Figure 4 and Figure 44 RL = 1 k, CL = 15 pF, see Figure 6 and Figure 45 RL = 1 k, CL = 15 pF, see Figure 6 and Figure 45 tINVRPHL tINVRPLH 25 25 35 35 ns ns VID +200 mV or VID -200 mV, see Figure 7 VID +200 mV or VID -200 mV, see Figure 7 tINVDPHL tINVDPLH 18 18 25 25 ns ns TxD = 0 V or TxD = VIO, see Figure 8 TxD = 0 V or TxD = VIO, see Figure 8 25 ADM2561E/ADM2563E All minimum and maximum specifications apply over the entire recommended operation range, VCC = 3.0 V to 5.5 V, VIO = 1.7 V to 5.5 V, TA = TMIN (-40C) to TMAX (+105C). All typical specifications are at TA = 25C, VCC = VIO = 5 V, VISO = 3.3 V (VSEL = GNDISO). Table 3. Parameter DRIVER Maximum Data Rate Propagation Delay Output Skew Rise Time/Fall Time Enable Time Disable Time RECEIVER Propagation Delay Output Skew Enable Time Disable Time RECEIVER CABLE INVERT, INVR Propagation Delay High to Low Low to High DRIVER CABLE INVERT, INVD Propagation Delay High to Low Low to High Symbol Min Typ Max Unit Test Conditions/Comments 220 5 280 130 800 400 100 600 1000 2000 kbps ns ns ns ns ns RL = 54 , CL1 = C L2 = 100 pF, see Figure 3 and Figure 42 RL = 54 , CL1 = CL2 = 100 pF, see Figure 3 and Figure 42 RL = 54 , CL1 = CL2 = 100 pF, see Figure 3 and Figure 42 RL = 110 , CL = 50 pF, see Figure 5 and Figure 43 RL = 110 , CL = 50 pF, see Figure 5 and Figure 43 tRPLH, tRPHL tSKEW tZL, tZH tLZ, tHZ 35 2 10 10 200 50 100 100 ns ns ns ns CL = 15 pF, see Figure 4 and Figure 44 CL = 15 pF, see Figure 4 and Figure 44 RL = 1 k, CL = 15 pF, see Figure 6 and Figure 45 RL = 1 k, CL = 15 pF, see Figure 6 and Figure 45 tINVRPHL tINVRPLH 25 25 200 200 ns ns VID +200 mV or VID -200 mV, see Figure 7 VID +200 mV or VID -200 mV, see Figure 7 tINVDPHL tINVDPLH 220 220 400 400 ns ns TxD = 0 V or TxD = VIO, see Figure 8 TxD = 0 V or TxD = VIO, see Figure 8 500 tDPLH, tDPHL tSKEW tDR, tDF tZL, tZH tLZ, tHZ 200 Rev. B | Page 6 of 28 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E Timing Diagrams VIO VIO/2 VIO/2 0V tDPLH tDPHL Z tSKEW = tDPLH - tDPHL 1/2VO VO Y +VO 90% POINT 90% POINT VDIFF = V(Y) - V(Z) VDIFF 10% POINT -VO 10% POINT tDF 22764-029 tDR NOTES 1. Y = A, Z = B FOR ADM2561E/ADM2565E Figure 3. Driver Propagation Delay, Rise/Fall Timing (See Figure 42 for Test Circuit) A-B 0V 0V tRPLH tRPHL 0.5VIO 0.5VIO RxD tSKEW = |tRPLH - tRPHL | VOL 22764-030 VOH Figure 4. Receiver Propagation Delay (See Figure 44 for Test Circuit) VIO DE 0.5VIO 0.5VIO 0V tZL tLZ 0.5 (VISOIN + VOL) Y, Z VOL + 0.5V VOL tZH tHZ VOH VOH - 0.5V 0.5 VOH NOTES 1. Y = A, Z = B FOR ADM2561E/ADM2565E 22764-031 Y, Z Figure 5. Driver Enable or Disable Timing (See Figure 43 for Test Circuit) Rev. B | Page 7 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet VIO RE 0.5VIO 0.5VIO 0V tLZ tZL 0.5VIO VOL + 0.5V OUTPUT LOW tZH RxD VOL tHZ OUTPUT HIGH VOH VOH - 0.5V 0.5VIO 22764-032 RxD 0V Figure 6. Receiver Enable or Disable Timing (See Figure 45 for Test Circuit) VIO INVR 0.5VIO 0.5VIO 0V tINVRPHL tINVRPLH VOH 0.5VIO 0.5VIO RxD (VID +200 mV) VOL VOH RxD (VID -200 mV) 0.5VIO 0.5VIO 22764-033 VOL NOTES 1. INVR = INV FOR ADM2561E/ADM2565E Figure 7. Receiver Cable Invert Timing V IO INVD 0.5VIO 0.5VIO tINVDPLH tINVDPHL Z 1/2|VO| |VOD| TxD = 0 Y Y 1/2|VO| |VOD| TxD = 1 NOTES 1. INVD = INV, Y = A, Z = B FOR ADM2561E/ADM2565E Figure 8. Driver Cable Invert Timing Rev. B | Page 8 of 28 22764-034 Z Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 1 2 Symbol RI-O CI-O CI Min Typ 1013 2.2 3.0 Max Unit pF pF Test Conditions/Comments f = 1 MHz Input capacitance Device considered a 2-terminal device: short together Pin 1 to Pin 14 and short together Pin 15 to Pin 28. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION For additional information, see www.analog.com/icouplersafety. Table 5. ADM2561E/ADM2563E/ADM2565E/ADM2567E Approvals UL (Pending) Recognized Under UL 1577 Component Recognition Program 1 Single Protection, 3 kV rms CSA (Pending) Approved under CSA Component Acceptance Notice 5A VDE (Pending) To be certified under DIN V VDE 0884-11 2 CQC (Pending) Certified under CQC11-471543-2012 CSA 62368-1-14, EN 62368-1:2014/A11:2017 and IEC 62368-1:2014 second edition: Basic insulation at 800 V rms (1131 V peak) Basic insulation: GB4943.1-2011: Working voltage (VIOWM) = 400 V rms Basic insulation at 800 V rms (1131 V peak) Reinforced insulation at 400 V rms (565 V peak) Reinforced insulation at 400 V rms (565 V peak) IEC 60601-1 Edition 3.1: 1 means of patient protection (MOPP), 250 V rms (354 V peak) CSA 61010-1-12 and IEC 61010-1 third edition: Basic insulation at 300 V rms mains, 800 V rms (1131 V peak) from secondary circuit Reinforced insulation at 300 V rms mains, 400 V rms (565 V peak) from secondary circuit File (Pending) 1 2 File 205078 (basic, reinforced pending) Repetitive maximum voltage (VIORM) = 565 V peak Surge isolation voltage (VIOSM) = 10 kV peak Highest allowable overvoltage (VIOTM) = 8000 V peak) Reinforced insulation: Working voltage (VIOWM) = 330 V rms Repetitive maximum voltage (VIORM) = 466 V peak Surge isolation voltage (VIOSM) = 6.25 kV peak Highest allowable overvoltage (VIOTM) = 8000 V peak) File (pending) File (pending) In accordance with UL 1577, each ADM2561E/ADM2563E/ADM2565E/ADM2567E is proof tested by applying an insulation test voltage 3600 V rms for 1 sec. In accordance with DIN V VDE 0884-11, each ADM2561E/ADM2563E/ADM2565E/ADM2567E is proof tested by applying an insulation test voltage 1060 V peak for 1 sec (partial discharge detection limit = 5 pC). INSULATION AND SAFETY RELATED SPECIFICATIONS Table 6. Critical Safety Related Dimensions and Material Properties Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 3 8.3 Unit kV rms mm Minimum External Tracking (Creepage) L(I02) 8.3 mm Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 8.1 mm CTI 22 >600 I m min V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Rev. B | Page 9 of 28 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110: 1989-01, Table 1) ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet DIN VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS (PENDING) The ADM2561E/ADM2563E/ADM2565E/ADM2567E are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. The asterisk (*) marking on packages denotes DIN VDE V 0884-11 approval. Table 7. Description CLASSIFICATIONS Installation Classification per DIN VDE V 0110 for Rated Mains Voltage 150 V rms 300 V rms 400 V rms Climatic Classification Pollution Degree VOLTAGE Maximum Working Insulation Voltage Maximum Repetitive Peak Insulation Voltage Input to Output Test Voltage Method b1 Method a After Environmental Tests, Subgroup 1 After Input and/or Safety Test, Subgroup 2/Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage, Basic Surge Isolation Voltage, Reinforced SAFETY LIMITING VALUES Case Temperature Total Power Dissipation at TA = 25C Insulation Resistance at TS Test Conditions/Comments VIOWM VIORM VPR V rms V peak VIORM x 1.875 = VPR, 100% production tested, tm = 1 sec, partial discharge < 5 pC 1060 V peak VIORM x 1.5 = Vpd (m), tini = 60 sec, tm= 10 sec, partial discharge < 5 pC VIORM x 1.2 = Vpd (m), tini = 60 sec, tm= 10 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Peak voltage (VPEAK) = 10 kV, 1.2 s rise time, 50 s, 50% fall time VPEAK = 10 kV, 1.2 s rise time, 50 s, 50% fall time Maximum value allowed in the event of a failure 848 V peak 678 V peak VIOTM VIOSM 8000 10,000 V peak V peak VIOSM 6250 V peak TS PS RS 150 2.87 >109 C W 2.7 SAFE LIMITING POWER (W) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0 100 150 22764-002 0.3 50 Unit 400 565 VIO = 500 V AMBIENT TEMPERATURE (C) Characteristic I to IV I to II I 40/105/21 2 Per DIN VDE V 0110, Table 1 3.0 0 Symbol Figure 9. Thermal Derating Curve for 28-Lead Standard Small Outline, Wide Body, with Finer Pitch (SOIC_W_FP), Dependence of Safety Limiting Values with Ambient Temperature per DIN VDE V 0884-11 Rev. B | Page 10 of 28 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 8. Parameter VCC to GND1 VIO to GND1 Digital Input Voltage (DE, RE, TxD, INV, INVR, INVD) to GND1 Digital Output Voltage (RxD) to GND1 Driver Output/Receiver Input Voltage (A, B, Y, Z) to GND2 VSEL to GND2 Operating Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.5 V to +6.0 V -0.5 V to +7.0 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -9 V to +14 V -0.5 V to +7.0 V -40C to +105C -55C to +150C Table 10. Maximum Continuous Working Voltage1, 2 Parameter AC Voltage Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation 260C 215C 220C Reinforced Insulation Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 1 2 Max Unit Reference Standard 565 V peak 565 V peak 50-year minimum lifetime 50-year minimum lifetime 1131 V peak 1131 V peak 565 V dc 565 V dc 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Values quoted for Material Group I, Pollution Degree II. ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. THERMAL RESISTANCE Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. International Electrotechnical Commission (IEC) electromagnetic compatibility: Part 4-2 (IEC) per IEC 61000-4-2. ESD Ratings for ADM2561E/ADM2563E/ ADM2565E/ADM2567E JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. Table 11. ADM2561E/ADM2563E/ADM2565E/ADM2567E, 28-Lead SOIC_W_FP Table 9. Thermal Resistance Package Type RN-28-11 1 JA 43.45 Unit C/W Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with no bias. See JEDEC JESD-51. ESD Model HBM CDM IEC1 1 2 Withstand Threshold (kV) 4 1.25 12 (contact discharge) to GND2 15 (air discharge) to GND2 8 (across isolation barrier) to GND1 Pin A, Pin B, Pin Y, and Pin Z only. Limited by clearance across isolation barrier. ESD CAUTION Rev. B | Page 11 of 28 Class 3A C5 Level 4 Level 4 Level 42 ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet GND1 1 GND1 2 28 GNDISO 27 VSEL GND1 3 26 GNDISO VCC 4 GND1 5 GND1 6 25 VISOOUT VIO 7 RxD 8 ADM2561E/ ADM2565E TOP VIEW (Not to Scale) 24 GNDISO 23 VISOIN 22 GND2 21 GND2 20 NIC DE 10 TxD 11 19 NIC 18 B INV 12 17 A NIC 13 GND1 14 16 GND2 15 GND2 RE 9 NIC = NOT INTERNALLY CONNECTED 22764-104 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 10. ADM2561E/ADM2565E Pin Configuration Table 12. ADM2561E/ADM2565E Pin Function Descriptions Pin No. 1, 2, 3, 5, 6, 14 4 Mnemonic GND1 VCC 7 VIO 8 RxD 9 RE 10 DE 11 TxD 12 INV 13, 19, 20 15, 16, 21, 22 17 18 23 NIC GND2 A B VISOIN 24, 26 25 GNDISO VISOOUT 27 VSEL 28 GNDISO Description Ground 1, Logic Side. 3.0 V to 3.6 V, or 4.5 V to 5.5 V Logic Side Power Supply. It is recommended that a 10 F and a 0.1 F decoupling capacitor be connected between VCC and GND1 (Pin 1, Pin 2, and Pin 3). 1.7 V to 5.5 V Logic Side Flexible I/O Supply. It is recommended that a 0.1 F decoupling capacitor be connected between VIO and GND1 (Pin 5 and Pin 6). Receiver Output Data. When the INV pin is logic low, this output is high when (A - B) -30 mV and low when (A - B) -200 mV. When the INV pin is high, this output is high when (A - B) 30 mV and low when (A - B) 200 mV. This output is tristated when the receiver is disabled by driving the RE pin high. Receiver Enable Input. This pin is an active low input. Driving this input low enables the receiver, and driving it high disables the receiver. Driver Output Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places these outputs in a high impedance state. Transmit Data Input. Data to be transmitted by the driver is applied to this input. When the INV pin is logic high, the data applied to this input is inverted. Inversion Enable. This pin is active high input. Driving this pin high inverts the TxD signal applied and inverts the A and B receiver inputs. Not Internally Connected. This pin is not internally connected. Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side. Noninverting Driver Output/Receiver Input. Inverting Driver Output/Receiver Input. Isolated Power Supply Input. This pin must be connected externally to VISOOUT (Pin 25) through one BLM15HD182SN1 ferrite. It is recommended that a reservoir capacitor of 10 F and a 0.1 F decoupling capacitor be connected between VISOIN (Pin 23) and GND2 (Pin 21). Isolated Power Supply Ground. These pins must be connected externally to Pin 28. Isolated Power Supply Output. This pin must be connected externally to VISOIN (Pin 23) through one BLM15HD182SN1 ferrite. It is recommended that a decoupling capacitor of 0.1 F be connected between VISOOUT and GNDISO (Pin 28). Output Voltage Selection. When VSEL = VISO, the VISO set point is 5.0 V. When VSEL = GNDISO, the VISO set point is 3.3 V. Isolated Power Supply Ground. This pin must be connected externally to GND2 (Pin 22) through one BLM15HD182SN1 ferrite. Rev. B | Page 12 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E GND1 1 28 GNDISO GND1 2 27 VSEL GND1 3 26 GNDISO VCC 4 GND1 5 GND1 6 25 VISOOUT 24 GNDISO 23 VISOIN 22 GND2 VIO 7 RxD 8 ADM2563E/ ADM2567E TOP VIEW (Not to Scale) 21 GND2 RE 9 20 A DE 10 TxD 11 19 B 18 Z INVD 12 17 Y INVR 13 GND1 14 16 GND2 15 GND2 22764-003 Data Sheet Figure 11. ADM2563E/ADM2567E Pin Configuration Table 13. ADM2563E/ADM2567E Pin Function Descriptions Pin No. 1, 2, 3, 5, 6, 14 4 Mnemonic GND1 VCC 7 VIO 8 RxD 9 RE 10 DE 11 TxD 12 13 INVD INVR 15, 16, 21, 22 17 18 19 20 23 GND2 Y Z B A VISOIN 24, 26 25 GNDISO VISOOUT 27 VSEL 28 GNDISO Description Ground 1, Logic Side. 3.0 V to 3.6 V, or 4.5 V to 5.5 V Logic Side Power Supply. It is recommended that a 10 F and a 0.1 F decoupling capacitor be connected between VCC and GND1 (Pin 1, Pin 2, and Pin 3). 1.7 V to 5.5 V Logic Side Flexible Input/Output (I/O) Supply. It is recommended that a 0.1 F decoupling capacitor be connected between VIO and GND1 (Pin 5 and Pin 6). Receiver Output Data. When the INVR pin is logic low, this output is high when (A - B) -30 mV and low when (A - B) -200 mV. When the INVR pin is high, this output is high when (A - B) 30 mV and low when (A - B) 200 mV. This output is tristated when the receiver is disabled by driving the RE pin high. Receiver Enable Input. This pin is an active low input. Driving this input low enables the receiver, and driving it high disables the receiver. Driver Output Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places these outputs in a high impedance state. Transmit Data Input. Data to be transmitted by the driver is applied to this input. When the INVD pin is logic high, the data applied to this input is inverted. Driver Inversion Enable. This pin is active high input. Driving this pin high inverts the TxD signal applied. Receiver Inversion Enable. This pin is active high input. Driving this pin high inverts the A and B receiver inputs. Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side. Driver Noninverting Output. Driver Inverting Output. Receiver Inverting Input. Receiver Noninverting Input. Isolated Power Supply Input. This pin must be connected externally to VISOOUT (Pin 25) through one BLM15HD182SN1 ferrite. It is recommended that a reservoir capacitor of 10 F and a 0.1 F decoupling capacitor be connected between VISOIN (Pin 23) and GND2 (Pin 21). Isolated Power Supply Ground. These pins must be connected externally to Pin 28. Isolated Power Supply Output. This pin must be connected externally to VISOIN (Pin 23) through one BLM15HD182SN1 ferrite. It is recommended that a decoupling capacitor of 0.1 F be connected between VISOOUT and GNDISO (Pin 28). Output Voltage Selection. When VSEL = VISO, the VISO set point is 5.0 V. When VSEL = GNDISO, the VISO set point is 3.3 V. Isolated Power Supply Ground. This pin must be connected externally to GND2 (Pin 22) through one BLM15HD182SN1 ferrite. Rev. B | Page 13 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.16 VCC SUPPLY CURRENT (A) VCC SUPPLY CURRENT (A) 0.16 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.18 0.18 0.14 0.12 0.10 0.08 0.14 0.12 0.10 0.08 0.06 0.04 0.06 TEMPERATURE (C) 0 22764-212 10 20 30 40 50 60 70 80 90 100 0 200 300 400 500 FREQUENCY (kHz) Figure 12. VCC Supply Current vs. Temperature at 500 kbps, No Load, 500 kbps Models (ADM2561E and ADM2563E) Figure 15. VCC Supply Current vs. Frequency, TA = 25C, No Load, 500 kbps Models (ADM2561E and ADM2563E) 0.30 0.33 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.25 VCC SUPPLY CURRENT (A) 0.28 0.23 0.18 0.20 0.15 0.10 0.13 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 0.05 22764-213 0.08 -40 -30 -20 -10 0 0 100 200 300 400 500 FREQUENCY (kHz) Figure 13. VCC Supply Current vs. Temperature at 500 kbps, 120 Load, 500 kbps Models (ADM2561E and ADM2563E) 22764-216 VCC SUPPLY CURRENT (A) 100 22764-214 0.02 0.04 -40 -30 -20 -10 0 Figure 16. VCC Supply Current vs. Frequency, TA = 25C, 120 Load, 500 kbps Models (ADM2561E and ADM2563E) 0.35 0.35 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.30 VCC SUPPLY CURRENT (A) VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.25 0.20 0.20 0.15 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 22764-215 0.15 0.10 -40 -30 -20 -10 0 0.25 Figure 14. VCC Supply Current vs. Temperature at 500 kbps, 54 Load, 500 kbps Models (ADM2561E and ADM2563E) Rev. B | Page 14 of 28 0.10 0 100 200 300 400 500 FREQUENCY (kHz) Figure 17. VCC Supply Current vs. Frequency, TA = 25C, 54 Load, 500 kbps Models (ADM2561E and ADM2563E) 22764-217 VCC SUPPLY CURRENT (A) 0.30 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E 0.20 0.16 0.14 0.12 0.10 0.08 0.12 0.10 0.08 0.06 0.04 TEMPERATURE (C) 0 22764-004 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 FREQUENCY (Mbps) Figure 18. VCC Supply Current vs. Temperature at 25 Mbps, No Load, 25 Mbps Models (ADM2565E and ADM2567E) 22764-010 0.02 0.06 -40 -30 -20 -10 0 Figure 21. VCC Supply Current vs. Frequency, TA = 25C, No Load, 25 Mbps Models (ADM2565E and ADM2567E) 0.30 0.24 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.22 0.25 VCC SUPPLY CURRENT (A) VCC SUPPLY CURRENT (A) VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.14 VCC SUPPLY CURRENT (A) VCC SUPPLY CURRENT (A) 0.18 0.16 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V 0.20 0.15 0.20 0.18 0.16 0.14 0.12 0.10 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 0.06 22764-005 0.10 -40 -30 -20 -10 0 10 15 20 25 Figure 22. VCC Supply Current vs. Frequency, TA = 25C, 120 Load, 25 Mbps Models (ADM2565E and ADM2567E) 0.30 VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 3.3V VCC = 5V, VISO = 5V VCC SUPPLY CURRENT (A) VCC SUPPLY CURRENT (A) 0.35 5 FREQUENCY (Mbps) Figure 19. VCC Supply Current vs. Temperature at 25 Mbps, 120 Load, 25 Mbps Models (ADM2565E and ADM2567E) 0.40 0 22764-011 0.08 0.30 0.25 0.20 0.25 0.20 0.15 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) Figure 20. VCC Supply Current vs. Temperature at 25 Mbps, 54 Load, 25 Mbps Models (ADM2565E and ADM2567E) Rev. B | Page 15 of 28 0.10 0 5 10 15 20 25 FREQUENCY (Mbps) Figure 23. VCC Supply Current vs. Frequency, TA = 25C, 54 Load, 25 Mbps Models (ADM2565E and ADM2567E) 22764-012 0.10 -40 -30 -20 -10 0 22764-006 0.15 ADM2561E/ADM2563E/ADM2565E/ADM2567E VISO = 3.3V VISO = 5V DRIVER OUTPUT CURRENT (mA) 5.3 5.1 4.9 4.7 4.5 4.3 4.1 1k 1M 100k 10k 100M 10M DATA RATE (bps) -40 -60 -80 -100 -120 22764-007 3.9 100 -20 -8 -6 -4 -2 Figure 24. VIO Supply Current vs. Data Rate Figure 27. Driver Output Current vs. Driver Output High Voltage 120 140 VISO = 3.3V VISO = 5V 120 DRIVER OUTPUT CURRENT (mA) 100 80 60 40 20 80 60 40 1 2 3 4 5 6 0 2.8 1.8 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 22764-220 2.3 4 6 8 10 12 Figure 28. Driver Output Current vs. Driver Output Low Voltage DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) 3.3 RL = 100, VISO = 3.3V RL = 100, VISO = 5V RL = 54, VISO = 3.3V RL = 54, VISO = 5V 2 DRIVER OUTPUT LOW VOLTAGE (V) Figure 25. Driver Output Current vs. Driver Differential Output Voltage 3.8 0 22764-125 0 DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V) 100 20 22764-022 DRIVER OUTPUT CURRENT (mA) VISO = 3.3V VISO = 5V 0 0 DRIVER OUTPUT HIGH VOLTAGE (V) Figure 26. Driver Differential Output Voltage vs. Temperature 220 tDPLH (VISO = 3.3V) tDPLH (VISO = 5V) tDPHL (VISO = 3.3V) tDPHL (VISO = 5V) 200 180 160 140 120 -50 0 50 100 150 TEMPERATURE (C) Figure 29. Driver Differential Propagation Delay vs. Temperature, 500 kbps Models (ADM2561E and ADM2563E) Rev. B | Page 16 of 28 22764-009 VIO SUPPLY CURRENT (mA) 0 VIO = 1.8V VIO = 2.5V VIO = 3.3V VIO = 5V 22764-124 5.5 Data Sheet Data Sheet 16 14 12 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 30. Driver Differential Propagation Delay vs. Temperature, 25 Mbps Models (ADM2565E and ADM2567E) -0.005 -0.010 0 Figure 33. Receiver Output High Voltage vs. Receiver Output Current 22764-014 2 VIO = 5V VIO = 3.3V VIO = 2.5V VIO = 1.8V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 RECEIVER OUTPUT CURRENT (mA) Figure 31. Transmitter Switching at 500 kbps, 500 kbps Models (ADM2561E and ADM2563E) Figure 34. Receiver Output Low Voltage vs. Receiver Output Current 25.5 RECEIVER OUTPUT LOW VOLTAGE (mV) CHANNEL 1 (TxD) 1 CHANNEL 2 (VOD) 22764-013 2 50ns/DIV 1 RECEIVER OUTPUT CURRENT (A) RECEIVER OUTPUT LOW VOLTAGE (V) CHANNEL 2 (VOD) CH1 1.0V CH2 1.0V 2 1.0 1 2s/DIV 3 0 -0.015 CHANNEL 1 (TxD) CH1 1.0V CH2 1.0V 4 22764-016 -40 22764-008 10 -60 5 22764-015 18 VIO = 5V VIO = 3.3V VIO = 2.5V VIO = 1.8V VIO = 3.6V, 2mA LOAD VIO = 2.7V, 1mA LOAD VIO = 1.95V, 0.5mA LOAD 25.0 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 32. Transmitter Switching at 25 Mbps, 25 Mbps Models (ADM2565E and ADM2567E) Figure 35. Receiver Output Low Voltage vs. Temperature Rev. B | Page 17 of 28 120 22764-017 20 6 tDPLH (VISO = 3.3V) tDPLH (VISO = 5V) tDPHL (VISO = 3.3V) tDPHL (VISO = 5V) RECEIVER OUTPUT HIGH VOLTAGE (V) DRIVER DIFFERENTIAL PROPAGATION DELAY (ns) 22 ADM2561E/ADM2563E/ADM2565E/ADM2567E ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet CHANNEL 1 (VID) 2.8 VIO = 3.0V, -2mA LOAD VIO = 2.3V, -1mA LOAD VIO = 1.7V, -0.5mA LOAD 2.6 1 2.4 CHANNEL 2 (RxD) 2.2 2.0 1.8 1.6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) CH1 1.0V CH2 1.0V Figure 38. Receiver Switching at 25 Mbps Figure 36. Receiver Output High Voltage vs. Temperature CHANNEL 1 (VID) tRPLH (VISO = 3.3V) tRPLH (VISO = 5V) tRPHL (VISO = 3.3V) tRPLH (VISO = 5V) 36 1 34 32 CHANNEL 2 (RxD) 30 28 26 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 120 Figure 37. Receiver Propagation Delay vs. Temperature CH1 1.0V CH2 1.0V 2s/DIV Figure 39. Receiver Switching at 500 kbps Rev. B | Page 18 of 28 22764-233 2 22764-231 RECEIVER PROPAGATION DELAY (ns) 38 50ns/DIV 22764-232 2 22764-018 RECEIVER OUTPUT HIGH VOLTAGE (V) 3.0 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E TEST CIRCUITS +1.5V RL 2 VIO S1 VOD2 RL 2 B/Z VOC RL -1.5V 22764-023 TxD RE S2 CL 22764-028 A/Y RE IN Figure 45. Receiver Enable or Disable Time Measurement Figure 40. Driver Voltage Measurement 375 VIO VCC VISOOUT VISOIN Figure 41. Driver Voltage Measurement over Common-Mode Range VIO R 15pF GND1 TxD A/Y GND1 CL TxD Figure 42. Driver Propagation Delay Measurement VO S1 B/Z VIO VCC S2 CL 50pF DE VISOOUT ISOLATED DC-TO-DC CONVERTER 22764-026 TxD RxD Figure 43. Driver Enable or Disable Time Measurement VIO R 15pF GND1 TxD A VO CL GND1 22764-027 B D GND1 RE Y DE = VIO RE = GND1 Figure 46. CMTI Test Diagram, Full Duplex VISOIN RL 110 Z ISOLATION BARRIER 22764-025 CL B/Z 120 B GND2 GND1 RL A/Y D A Figure 44. Receiver Propagation Delay Time Measurement VISOIN GND2 ISOLATION BARRIER A 120 B DE = VIO RE = GND1 Figure 47. CMTI Test Diagram, Half Duplex Rev. B | Page 19 of 28 22764-137 375 RxD IEC 61000-4-2 ESD PROTECTION B/Z 22764-136 VCM 60 22764-024 VOD3 TxD ISOLATED DC-TO-DC CONVERTER IEC 61000-4-2 ESD PROTECTION A/Y ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet THEORY OF OPERATION LOW EMI INTEGRATED DC-TO-DC CONVERTER ROBUST LOW POWER DIGITAL ISOLATOR The ADM2561E/ADM2563E/ADM2565E/ADM2567E include a flexible integrated dc-to-dc converter optimized for low radiated emissions (EMI). The isolated dc-to-dc converter is constructed of a set of chip scale coplanar coils separated by an insulating material. By exciting the upper coil with an ac signal, power is magnetically coupled across the isolation barrier where it is rectified and regulated. Because no direct electrical connection exists between the top and bottom coil, the primary and secondary side of the device remain galvanically isolated. The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature a low power digital isolator to galvanically isolate the primary and secondary side of the device. The use of coplanar transformer coils with an on and off keying modulation scheme allows high data throughput across the isolation barrier while minimizing radiation emissions. This architecture provides a robust digital isolator with immunity to common-mode transients of greater than 250 kV/s across the full temperature and supply range of the device. This isolated dc-to-dc converter features a regulated output of either 3.3 V or 5 V, selectable via the VSEL logic pin, which allows the user to optimize the supply rail of the RS-485 transceiver. For lower power applications, a 3.3 V supply can be chosen. For applications requiring a large differential output voltage, such as PROFIBUS(R), the isolated dc-to-dc converter can be operated with a 5 V output. Table 14 shows the supported supply configurations for the isolated dc-to-dc converter. CHANNEL 1 (TxD) 1 CHANNEL 2 (VCM) 2 CHANNEL 3 (RxD) Table 14. Isolated DC-to-DC Converter Supply Configuration VSEL Pin Connected to GNDISO Connected to VISOOUT 3 Supported VCC Supply Range 3 V to 5.5 V 4.5 V to 5.5 V CH1 2.0V CH3 2.0V The integrated dc-to-dc converter is optimized to minimize radiated EMI, and allows designers to meet the CISPR32 and EN 55032 Class B requirements on a 2-layer PCB with the addition of two low cost, surface-mount device (SMD) ferrites. Follow layout recommendations during PCB design to minimize these emissions. See the PCB Layout and Electromagnetic Interference (EMI) section for more details. 70 60 50 CLASS A 40 CLASS B 20 10 0 100ns/DIV Figure 49. Switching Correctly in the Presence of >250 kV/s Common-Mode Transients HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature a proprietary transmitter architecture with a low driver output impedance, resulting in an increased driver differential output voltage. This architecture is particularly useful when operating the device over long cable runs, where the dc resistance of the transmission line dominates signal attenuation. In these applications, the increased differential voltage improves noise margin and allows transmission over longer cable lengths. In addition, when operated as a 5 V transceiver (VSEL = VISO), the ADM2561E/ADM2563E/ADM2565E/ADM2567E meet or exceed the PROFIBUS requirement of a minimum 2.1 V differential output voltage. IEC61000-4-2 ESD PROTECTION 30 30 100 22764-035 RADIATED FIELD STRENGTH (dBV/m) 80 CH2 1kV 22764-113 VISO Output Supply Voltage 3.3 V 5V 1000 FREQUENCY (MHz) Figure 48. Low Radiated Emissions DC-to-DC Converter Meets EN55022 Class B with Margin on a 2-Layer PCB ESD is the sudden transfer of electrostatic charge between bodies at different potentials caused by near contact or induced by an electric field. ESD has the characteristics of high current in a short time period. The primary purpose of the IEC 61000-4-2 test is to determine the immunity of systems to external ESD events outside the system during operation. IEC 61000-4-2 describes testing using two coupling methods: contact discharge and air discharge. Contact discharge implies a direct contact between the discharge gun and the equipment under test (EUT). During air discharge testing, the charged electrode of the discharge gun is moved toward the EUT until a discharge occurs as an arc across the air gap. The discharge gun does not Rev. B | Page 20 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E make direct contact with the EUT. A number of factors affect the results and repeatability of the air discharge test, including humidity, temperature, barometric pressure, distance, and rate of approach to the EUT. Air discharge testing is a more accurate representation of an actual ESD event than contact discharge but is not as repeatable. Therefore, contact discharge is the preferred test method. During testing, the data port is subjected to at least 10 positive and 10 negative single discharges. Selection of the test voltage is dependent on the system end environment. Figure 50 shows the 8 kV contact discharge current waveform as described in the IEC 61000-4-2 specification. Some of the key waveform parameters are rise times of less than 1 ns and pulse widths of approximately 60 ns. IPEAK 30A 90% IEC 61000-4-2 ESD 8kV I30ns 16A I60ns 8A 5.33A HBM ESD 8kV 10% 10ns 30ns TIME 60ns tR = 0.7ns TO 1ns 22764-038 Data Sheet Figure 51. IEC61000-4-2 ESD 8 kV Waveform Compared to HBM ESD 8 kV Waveform IPEAK 30A 90% TRUTH TABLES Table 16 and Table 17 use the abbreviations shown in Table 15. VIO supplies the DE, TxD, RE, RxD, INVR, and INVD pins only. I30ns 16A Table 15. Truth Table Abbreviations I60ns 8A 30ns 60ns tR = 0.7ns TO 1ns TIME 22764-036 10% Figure 50. IEC61000-4-2 ESD Waveform (8 kV) Figure 51 shows the 8 kV contact discharge current waveform from the IEC 61000-4-2 standard compared to the HBM ESD 8 kV waveform. Figure 51 shows that the two standards specify a different waveform shape and peak current (IPEAK). The peak current associated with an IEC 61000-4-2 8 kV pulse is 30 A, whereas the corresponding peak current for HBM ESD is more than five times less, at 5.33 A. The other difference is the rise time of the initial voltage spike, with the IEC 61000-4-2 ESD waveform having a much faster rise time of 1 ns, compared to the 10 ns associated with the HBM ESD waveform. The amount of power associated with an IEC ESD waveform is much greater than that of an HBM ESD waveform. The HBM ESD standard requires the EUT to be subjected to three positive and three negative discharges, whereas in comparison, the IEC ESD standard requires 10 positive and 10 negative discharge tests. The ADM2561E/ADM2563E/ADM2565E/ADM2567E are rated to 12 kV contact and 15 kV air ESD protection to the IEC61000-4-2 standard between the RS-485 bus pins (A, B, Y and Z) and GND2. The isolation barrier provides 8 kV contact protection between the bus pins and GND1. These devices with IEC 61000-4-2 ESD ratings are better suited for operation in harsh environments when compared to other RS-485 transceivers that state varying levels of HBM ESD protection. Letter H I L X Z Description High level Indeterminate Low level Any state High impedance (off) Table 16. Transmitting Truth Table Supply Status VCC VIO On On On On On On On On On On On Off Off X DE H H H H L X X Inputs TxD H H L L X X X Outputs Y Z H L L H L H H L Z Z Z Z Z Z INVD L H L H X X X Table 17. Receiving Truth Table Supply Status VCC On On On On On On On X X Off Rev. B | Page 21 of 28 VIO On On On On On On On On Off On Inputs A-B -0.03 V 0.03 V -0.2 V 0.2 V -0.2 V < A - B < -0.03 V 0.03 V < A - B < 0.2 V Inputs open/shorted X X X Output INVR RE L H L H L H X X X X L L L L L L L H X L RxD H H L L I I H Z I I ADM2561E/ADM2563E/ADM2565E/ADM2567E The ADM2561E/ADM2563E/ADM2565E/ADM2567E guarantee a logic high receiver output when the receiver inputs are shorted, open, or connected to a terminated transmission line with all drivers disabled. When the receiver inversion feature is disabled (INV/INVR = 0 V), a fail-safe logic high output is achieved by setting the receiver input threshold between -30 mV and -200 mV. If the differential receiver input voltage (A - B) is greater than or equal to -30 mV, the RxD pin is logic high. If the A - B input is less than or equal to -200 mV, RxD is logic low. Fail-safe is preserved when the receiver inversion feature is enabled (INVR = VIO) by setting the inverted receiver input threshold between 30 mV and 200 mV. In the case of a shorted or terminated bus with all transmitters disabled, the receiver differential input voltage is pulled to 0 V by the termination resistor, resulting in a logic high with a 30 mV minimum noise margin. This feature eliminates the need for external biasing components usually required to implement fail-safe. These features are fully compatible with external fail-safe biasing configurations, which can be used in applications with legacy devices that lack fail-safe support, or in applications where additional noise margin is desired. See the AN-960 Application Note, RS-485/RS-422 Circuit Implementation Guide, for details on external fail-safe biasing. DRIVER AND RECEIVER CABLE INVERSION The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature cable inversion functionality to correct errors during installation. This adjustment can be implemented in software on the controller driving the RS485 transceiver and helps avoid additional installation costs to fix wiring errors. The ADM2563E/ ADM2567E feature separate digital logic pins, INVD and INVR, to correct cases where the driver, receiver, or both are wired in reverse. Use the INVD pin to correct driver functionality when Y and Z are wired with the incorrect polarity. Use the INVR pin to correct receiver functionality when A and B are wired with the incorrect polarity. The ADM2561E/ADM2565E are half-duplex devices that have a single inversion pin, INV, to correct both transmitter and receiver polarity. When the receiver is inverted, the device maintains a Logic 1 receiver output with a 30 mV noise margin when inputs are shorted together or open circuit. Figure 52 shows the receiver output in both inverted and noninverted cases. PHASE INVERTED RS-485 INVR = H A-B RS-485 INVR = L 0 +200mV IN 1 +30mV FAIL SAFE FAIL SAFE -30mV 1 -200mV 0 Figure 52. RS-485 and Phase Inverted RS-485 Comparison HOT SWAP INPUTS When a circuit board is inserted in a powered (or hot) backplane, parasitic coupling from supply and ground rails to digital inputs may occur. The ADM2561E/ADM2563E/ ADM2565E/ADM2567E contain circuitry to ensure that the Y and Z outputs remain in a high impedance state during power-up, and then default to the correct states. For example, when VIO and VCC power up at the same time and the RE pin is pulled low, with the DE and TxD pins pulled high, the Y and Z outputs remain in high impedance until settling at an expected default high state for the Y pin and expected default low state for the Z pin. Table 18. Product Description Table Device ADM2561E ADM2563E ADM2565E ADM2567E 1 Isolation Withstand 3 kV 3 kV 3 kV 3 kV Duplex Half Full Half Full Maximum Data Rate 500 kbps1 500 kbps1 25 Mbps 25 Mbps 22764-039 RECEIVER FAIL-SAFE Data Sheet Cable Inversion Feature Inversion pin (INV) Separate driver (INVD) and receiver (INVR) inversion Inversion pin (INV) Separate driver (INVD) and receiver (INVR) inversion Driver outputs are slew rate limited to minimize common-mode emissions over long cable runs. Rev. B | Page 22 of 28 Package(s) Available 28-lead SOIC_W with finer pitch 28-lead SOIC_W with finer pitch 28-lead SOIC_W with finer pitch 28-lead SOIC_W with finer pitch Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E 192 TRANSCEIVERS ON THE BUS 1.7 V TO 5.5 V VIO LOGIC SUPPLY The standard RS-485 receiver input impedance is 12 k (1 unit load), and the standard driver can drive up to 32 unit loads. The ADM2561E/ADM2563E/ADM2565E/ADM2567E transceiver has a 1/6 unit load receiver input resistance (equivalent to 72 k), allowing up to 192 transceivers to be connected in parallel on one communication line. Any combination of these devices and other RS-485 transceivers with a total of 32 unit loads or fewer can be connected to the line. The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature a VIO logic supply pin to allow a flexible digital interface operational to voltages as low as 1.7 V. The VIO pin powers the primary side of the signal isolation, the logic inputs, and the RxD output. These input and output pins interface with logic devices such as universal asynchronous receiver/transmitters (UARTs), application specific integrated circuits (ASICs), and microcontrollers. For applications where these devices use I/Os operating at voltages other than the ADM2561E/ADM2563E/ ADM2565E/ADM2567E VCC supply voltage, the VIO supply can be powered from the same supply rail as the logic device. The VIO supply accepts a supply voltage between 1.7 V and 5.5 V, allowing communication with 1.8 V, 2.5 V, 3.3 V, and 5 V devices. DRIVER OUTPUT PROTECTION The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature two methods to prevent excessive output current and power dissipation caused by faults or by bus contention. Current-limit protection on the output stage provides immediate protection against short circuits over the entire common-mode voltage range. In addition, a thermal shutdown circuit forces the driver outputs to a high impedance state if the die temperature rises excessively. This circuitry is designed to disable the driver outputs when a die temperature greater than 150C is reached. As the device cools, the drivers are reenabled at a temperature of 140C. Rev. B | Page 23 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet APPLICATIONS INFORMATION PCB LAYOUT AND ELECTROMAGNETIC INTERFERENCE (EMI) The ADM2561E/ADM2563E/ADM2565E/ADM2567E meet EN 55032 Class B/CISPR32 radiated emissions requirements. Two external surface-mount technology (SMT) ferrite beads are used to pass the Class B limits with margin. No additional mitigation techniques, such as stitching capacitance, are needed, allowing system designers to create a compliant design on a 2-layer PCB, without the need for complex and area intensive layouts. The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature an internal split paddle lead frame on the bus side. For optimal noise suppression, filter the VISOOUT signal (Pin 25) and GNDISO signal (Pin 24, Pin 26, and Pin 28) for high frequency currents before routing power to the RS-485 transceiver and other circuitry. Two SMT ferrite beads, L1 and L2, are recommended to achieve this filtering. The size of the VISOOUT and GNDISO net must also be kept to a minimum. See Figure 53 for the recommended PCB layout. METAL KEEP OUT GND1 GND1 GND1 0.1F VCC GND1 0.1F 1 28 2 27 3 26 4 25 5 24 GND1 6 VIO RxD RE 7 8 23 ADM2567E TOP VIEW (Not to Scale) 22 21 9 20 10 19 11 18 12 17 INVR 13 GND1 16 DE TxD INVD 14 15 GNDISO VSEL L1 GNDISO 0.1F L2 VISOOUT 10F VISOIN GND2 0.1F GND2 A B Z Y GND2 GND2 DEVICE POWER-UP The integrated isoPower isolated dc-to-dc converter requires 10 ms to power up to the setpoint of 3.3 V or 5 V. During this start-up time, it is not recommended to assert the DE driver enable signal. In applications where the isolated dc-to-dc converter is operated with a 3.3 V output voltage (VSEL pin connected to GNDISO), the VCC supply rail must be greater than 3.135 V during the power-up sequence. After the 10 ms power-up duration, the VCC supply rail can operate across the full 3 V to 5.5 V range. MAXIMUM DATA RATE vs. AMBIENT TEMPERATURE GNDISO 22764-040 10F The ADM2561E/ADM2563E/ADM2565E/ADM2567E can dissipate over 500 mW of power when fully loaded. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation to the PCB through the GNDx pins. If the devices are used at high ambient temperatures, provide a thermal path from the GNDx pins to the PCB ground plane. The use of a solid GND1 and GND2 plane is recommended. Implementing a low thermal impedance between the top ground layers and internal ground layers reduce the temperature inside the chip significantly. Figure 53. Recommended PCB Layout The isoPower(R) integrated dc-to-dc converter contains switching frequencies between 180 MHz and 400 MHz. To effectively filter these frequencies, the impedance of the ferrite bead is chosen to be about 2 k between the 100 MHz and 1 GHz frequency range. Some recommended SMT ferrites are shown in Table 19. Although these ferrite beads are required to achieve compliance to EN 55032 Class B, they are not needed for system functionality. The ADM2561E/ADM2563E/ADM2565E/ ADM2567E have been fully characterized with the recommended BLM15HD182SN1 ferrite beads. Under a large current load or when operating at high frequency operation, self heating effects within the isoPower dc-to-dc converter can limit the maximum ambient temperature achievable while retaining a silicon junction temperature below 150C. This internal power dissipation is related to application conditions such as supply voltage configuration, switching frequency, effective load on the RS-485 bus, and the amount of time the transceiver is in transmit mode. Thermal performance also depends on the PCB design and thermal characteristics of a system. In applications with a fully loaded RS-485 bus (equivalent to 54 bus resistance) operating with VISO = 5 V, it is recommended to keep the VCC input supply greater than 4.75 V. If this is not possible for the ADM2565E/ADM2567E, limit either the maximum ambient temperature to 85C or the maximum operating data rate to 6 Mbps. If this is not possible for the ADM2561E/ADM2563E, limit the maximum ambient temperature to 85C. Table 19. Examples of Surface-Mount Ferrite Beads Manufacturer Murata Electronics Taiyo Yuden Device No. BLM15HD182SN1 BKH1005LM182-T Rev. B | Page 24 of 28 Data Sheet ADM2561E/ADM2563E/ADM2565E/ADM2567E ISOLATED PROFIBUS SOLUTION The ADM2565E features a driver that is well suited for meeting the requirements of an isolated PROFIBUS node. When operating the ADM2565E as a PROFIBUS transceiver, connect the VSEL pin to the VISOOUT pin to operate the transceiver with a 5 V isolated supply voltage. The ADM2565E features the following characteristics that make it ideally suited for use in PROFIBUS applications: * 5 V isolated transceiver power supply. The 5 V VISO output supply provides the required current for the RS-485 transceiver at up to 12 Mbps and the additional 5 mA required for the PROFIBUS termination network. The output driver meets or exceeds the PROFIBUS differential output requirements. To ensure the transmitter differential output does not exceed 7 V p-p over all conditions, place 10 resistors in series with the A and B transmitter outputs. High speed timing to operate at 12 Mbps with low propagation delay and less than 10% transmitter and receiver skew. Low bus pin capacitance of 28 pF. Class I (no loss of data) immunity to IEC 61000-4-4 EFT to 1 kV can be achieved using a PROFIBUS shielded cable. At data rates of 500 kbps, IEC 61000-4-4 Class I to 3 kV can be achieved with the addition of a 470 pF capacitor to GND1 on the RxD output pin. * * * * EMC, EFT, AND SURGE In applications where additional levels of protection against IEC61000-4-4 EFT or IEC61000-4-5 surge events are required, external protection circuits can be added to further enhance the EMC robustness of these devices. See Figure 54 for a recommended protection circuit, which uses a series of SM712 transient voltage suppressor (TVS) and 10 pulse proof resistors to achieve in excess of Level 4 IEC61000-4-2 ESD and IEC61000-4-4 EFT protection, and Level 2 IEC61000-4-5 surge protection. Table 20 and Table 21 describe the recommended components for protection and the protection levels. VIO TxD D GND2 GND1 ISOLATION BARRIER A 10 120 B 10 SM712 TVS Y 10 Recommended Components TVS 10 Pulse Proof Resistors Part Number CDSOT23-SM712 CRCW060310R0FKEAHP Table 21. Protection Levels with Recommended Circuit EMC Standard ESD--Contact (IEC61000-4-2) ESD--Air (IEC61000-4-2) EFT (IEC61000-4-4) Surge (IEC61000-4-5) Protection Level (kV) 30 (exceeds Level 4) 30 (exceeds Level 4) 4 (exceeds Level 4) 1 (Level 2) INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period of time. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation, as well as on the materials and material interfaces. The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and is the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components, allowing the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and can therefore provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. See Table 6 for the material group and creepage information for the ADM2561E/ADM2563E/ ADM2565E/ADM2567E isolated RS-485 transceiver. Insulation Wear Out Z 10 SM712 TVS 22764-041 R RxD IEC 61000-4-2 ESD PROTECTION VCC Table 20. Recommended Components for ESD, EFT, and Surge Protection Figure 54. Isolated RS-485 Solution with ESD, EFT, and Surge Protection The lifetime of insulation caused by wear out is determined by the thickness, material properties, and the voltage stress applied across the insulation. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. The working voltage applicable to tracking is specified in most standards. Rev. B | Page 25 of 28 ADM2561E/ADM2563E/ADM2565E/ADM2567E Testing and modeling show that the primary driver of long-term degradation is displacement current in the polyimide insulation, causing incremental damage. The stress on the insulation can be divided into broad categories, such as dc stress and ac component time varying voltage stress. DC stress causes little wear out because there is no displacement current, whereas ac component time varying voltage stress causes wear out. The ratings in certification documents are typically based on 60 Hz sinusoidal stress to reflect isolation from the line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier, as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials used in these products, the ac rms voltage determines the product lifetime. = VRMS VAC RMS 2 - VDC 2 VRMS 2 - VDC 2 (2) where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 V ac rms and a 400 V dc bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage, clearance, and lifetime of a device, see Figure 55 and the following equations. = VRMS This VRMS value is the working voltage used together with the material group and pollution degree when determining the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation 2. V= AC RMS VRMS 2 - VDC 2 VAC = RMS 4662 - 4002 VAC RMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for working voltage in Table 10 for the expected lifetime, which is less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. An example circuit using the ADM2567E as a full duplex RS-485 node is shown in Figure 56. Placement of the termination resistor, RT, is dependent on the location of the node and the network topology. Refer to the AN-960 Application Note, RS-485/RS-422 Circuit Implementation Guide, for guidance on termination. Up to 192 transceivers can be connected to the bus. To minimize reflections, terminate the line at the receiving end in its characteristic impedance and keep stub lengths off the main line as short as possible. For half-duplex operation, this means that both ends of the line must be terminated because either end can be the receiving end. VDC TIME 2402 - 4002 TYPICAL APPLICATIONS VAC RMS VRMS VAC RMS 2 - VDC 2 VRMS = 466 V 22764-042 ISOLATION VOLTAGE = VRMS The dc working voltage limit is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. Calculation and Use of Parameters Example VPEAK The working voltage across the barrier from Equation 1 is (1) or V= AC RMS Data Sheet Figure 55. Critical Voltage Example Rev. B | Page 26 of 28 Data Sheet LOW VOLTAGE 1.8V/2.5V SUPPLY ADM2561E/ADM2563E/ADM2565E/ADM2567E 3.3V/5V POWER SUPPLY 100nF 10uF VSEL VCC 100nF GNDISO VISOOUT 10F 100nF VISOIN LOW RADIATED EMISSIONS DC-TO-DC VIO RECTIFIER OSCILLATOR 100nF VCC REGULATOR RE DIGITAL ISOLATION iCoupler RS-485 TRANSCEIVER A INVR MICROCONTROLLER AND UART TxD DECODE ENCODE ENCODE DECODE ENCODE DECODE R CABLE INVERT D INVD DE RT IEC 61000-4-2 ESD PROTECTION RxD B Y Z DECODE ENCODE GND1 GNDISO GND1 ISOLATION BARRIER Figure 56. Example Circuit Diagram Using the ADM2567E Rev. B | Page 27 of 28 GND2 22764-043 ADM2567E ADM2561E/ADM2563E/ADM2565E/ADM2567E Data Sheet OUTLINE DIMENSIONS 10.45 10.15 28 15 7.60 7.40 10.55 10.05 14 1 PIN 1 INDICATOR TOP VIEW 2.40 2.25 0.65 BSC 0.75 x 45 0.25 SIDE VIEW 2.65 2.35 END VIEW 0.32 0.23 PKG-004678 8 0 0.25 0.10 COPLANARITY 0.10 SEATING PLANE 0.25 BSC (GAUGE PLANE) 1.27 0.40 1.40 REF 06-01-2015-A 0.40 0.25 Figure 57. 28-Lead Standard Small Outline, Wide Body, with Finer Pitch [SOIC_W_FP] (RN-28-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADM2561EBRNZ ADM2561EBRNZ-RL7 ADM2563EBRNZ ADM2563EBRNZ-RL7 ADM2565EBRNZ ADM2565EBRNZ-RL7 ADM2567EBRNZ ADM2567EBRNZ-RL7 EVAL-ADM2561EEBZ EVAL-ADM2563EEBZ EVAL-ADM2565EEBZ EVAL-ADM2567EEBZ 1 Isolation (kV) 3 3 3 3 3 3 3 3 Data Rate (Mbps) 0.5 0.5 0.5 0.5 25 25 25 25 Duplex Half Half Full Full Half Half Full Full Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Z = RoHS Compliant Part. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D22764-8/20(B) Rev. B | Page 28 of 28 Package Description 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP 28-Lead SOIC_W_FP Half Duplex Evaluation Board Full Duplex Evaluation Board Half Duplex Evaluation Board Full Duplex Evaluation Board Package Option RN-28-1 RN-28-1 RN-28-1 RN-28-1 RN-28-1 RN-28-1 RN-28-1 RN-28-1