DATASHEET 82C55A FN2969 Rev 11.00 Dec 8, 2015 CMOS Programmable Peripheral Interface The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Features Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power. * Direct Bit Set/Reset Capability * Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info) * Pin Compatible with NMOS 8255A * 24 Programmable I/O Pins * Fully TTL Compatible * High Speed, No "Wait State" Operation with 5MHz and 8MHz 80C86 and 80C88 * Enhanced Control Word Read Capability * L7 Process * 2.5mA Drive Capability on All I/O Ports * Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A Ordering Information PART NUMBERS 5MHz PART MARKING 8MHz CP82C55A-5 (No longer available, recommended replacement: CP82C55A-5Z) CP82C55A-5 CP82C55A CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) IP82C55A PART MARKING CP82C55A CP82C55AZ TEMP. RANGE (C) PACKAGE 0 to +70 40 Ld PDIP 0 to +70 40 Ld PDIP (Pb-free) IP82C55A -40 to +85 IP82C55AZ (Note) IP82C55AZ -40 to +85 CS82C55A* CS82C55A* 0 to +70 PKG. DWG. # E40.6 40 Ld PDIP 40 Ld PDIP (Pb-free) CS82C55A-5* (No longer available, recommended replacement: CS82C55A-5Z) CS82C55A-5 CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ IS82C55A-5* IS82C55A-5 IS82C55A* IS82C55A* -40 to +85 44 Ld PLCC IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ -40 to +85 44 Ld PLCC (Pb-free) CQ82C55AZ (Note) CQ82C55AZ 0 to +70 44 Ld MQFP (Pb-free) IQ82C55AZ* (Note) IQ82C55AZ -40 to +85 44 Ld MQFP (Pb-free) ID82C55A ID82C55A -40 to +85 40 Ld CERDIP F40.6 MD82C55A/B MD82C55A/B -55 to +125 8406602QA 8406602QA SMD# 8406602XA 8406602XA SMD# 44 Ld CLCC J44.A 0 to +70 44 Ld PLCC N44.65 44 Ld PLCC (Pb-free) Q44.10x10 *Add "96" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2969 Rev 11.00 Dec 8, 2015 Page 1 of 30 82C55A Pinouts WR PA7 PA6 PA5 PA4 PA3 PA1 RD CS PA2 2 1 44 43 42 41 40 39 NC 38 RESET 37 D0 36 D1 35 D2 34 D3 33 D4 32 D5 31 D6 30 D7 29 NC 7 8 9 10 11 12 13 14 15 16 17 NC VCC PB7 PB6 PB5 PB4 PB3 WR PA7 PA6 PA5 PA4 NC PA3 PA1 RD PA0 82C55A (MQFP) TOP VIEW RD PA0 PA1 PA2 PA3 NC PA4 PA5 PA6 PA7 WR 82C55A (PLCC) TOP VIEW PB2 18 19 20 21 22 23 24 25 26 27 28 PA2 13 14 15 16 17 18 19 20 6 5 4 3 GND NC A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PB1 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 PB0 40 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 9 10 11 12 PC3 PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 82C55A (CLCC) TOP VIEW PA0 82C55A (PDIP, CERDIP) TOP VIEW 6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34 33 2 32 RESET A1 3 31 D1 A0 4 30 D2 PC7 5 29 D3 CS GND 1 FN2969 Rev 11.00 Dec 8, 2015 D0 D6 PC0 9 25 D7 PC1 10 24 VCC PC2 11 23 12 13 14 15 16 17 18 19 20 21 22 PB7 NC 26 PB6 8 PB5 D5 PC4 PB4 D4 27 PB3 28 7 NC 6 PB2 PC6 PC5 NC PB2 NC PB3 PB4 PB5 PB6 PB7 PC2 PC3 PB0 PB1 18 1920 21 22 23 24 25 26 27 28 RESET D0 D1 D2 D3 NC D4 D5 D6 D7 VCC PB1 39 38 37 36 35 34 33 32 31 30 29 PB0 7 8 9 10 11 12 13 14 15 16 17 PC3 CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1 Page 2 of 30 82C55A Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling. GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the "Bus Hold" circuitry turned on. CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. A0-A1 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PB0-PB7 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PC0-PC7 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port. Functional Diagram POWER SUPPLIES +5V GND GROUP A PORT A (8) GROUP A CONTROL GROUP A PORT C UPPER (4) BIDIRECTIONAL DATA BUS D7-D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS RD WR A1 A0 READ WRITE CONTROL LOGIC GROUP B CONTROL GROUP B PORT C LOWER (4) GROUP B PORT B (8) I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 RESET CS FN2969 Rev 11.00 Dec 8, 2015 Page 3 of 30 82C55A Functional Description Data Bus Buffer This three-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A "low" on this input pin enables the communication between the 82C55A and the CPU. (RD) Read. A "low" on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 82C55A. (WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). 82C55A BASIC OPERATION INPUT OPERATION (READ) A1 A0 RD WR CS 0 0 0 1 0 Port A Data Bus 0 1 0 1 0 Port B Data Bus 1 0 0 1 0 Port C Data Bus 1 1 0 1 0 Control Word Data Bus POWER SUPPLIES +5V GND BIDIRECTIONAL DATA BUS DATA BUS D7-D0 BUFFER RD WR A1 A0 RESET READ WRITE CONTROL LOGIC GROUP A CONTROL GROUP A PORT A (8) GROUP A PORT C UPPER (4) 8-BIT INTERNAL DATA BUS GROUP B CONTROL GROUP B PORT C LOWER (4) GROUP B PORT B (8) I/O PA7PA0 I/O PC7PC4 I/O PC3PC0 I/O PB7PB0 CS FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 82C55A. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) 0 0 1 0 0 Data Bus Port A The control word register can be both written and read as shown in the "Basic Operation" table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic "1", as this implies control word mode information. 0 1 1 0 0 Data Bus Port B Ports A, B, and C 1 0 1 0 0 Data Bus Port C 1 1 1 0 0 Data Bus Control OUTPUT OPERATION (WRITE) DISABLE FUNCTION X X X X 1 Data Bus Three-State X X 1 1 0 Data Bus Three-State (RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. "Bus hold" devices internal to the 82C55A will hold the I/O port inputs to a logic "1" state with a maximum hold current of 400A. FN2969 Rev 11.00 Dec 8, 2015 The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 82C55A. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A. See Figure 2A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 2B. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into Page 4 of 30 82C55A two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. See Figure 2B. ADDRESS BUS CONTROL BUS DATA BUS INPUT MODE MASTER RESET OR MODE CHANGE RD, WR INTERNAL DATA IN EXTERNAL PORT A PIN MODE 0 INTERNAL DATA OUT (LATCHED) OUTPUT MODE I/O PB7-PB0 MODE 1 VCC RESET OR MODE CHANGE EXTERNAL PORT B, C PIN INTERNAL DATA OUT (LATCHED) OUTPUT MODE 4 I/O PC7-PC4 I/O 8 CONTROL CONTROL OR I/O OR I/O C I/O PA7-PA0 A 8 I/O PA7-PA0 A BIDIRECTIONAL I/O PB7-PB0 FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION I/O PC3-PC0 B 8 A C PB7-PB0 MODE 2 4 B 8 P INTERNAL DATA IN A0-A1 CS C B 8 FIGURE 2A. PORT A BUS-HOLD CONFIGURATION D7-D0 82C55A CONTROL PA7-PA0 FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE FIGURE 2. BUS-HOLD CONFIGURATION Operational Description Mode Selection There are three basic modes of operation than can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the reset input goes "high", all ports will be set to the input mode with all 24 port lines held at a logic "one" level by internal bus hold devices. After the reset is removed, the 82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pull-up or pull-down resistors in all-CMOS designs. The control word register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written. CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 GROUP A PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE FIGURE 4. MODE DEFINITION FORMAT FN2969 Rev 11.00 Dec 8, 2015 Page 5 of 30 82C55A The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. The mode definitions and possible mode combinations may seem confusing at first, but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. INTE Flip-Flop Definition (BIT-SET)-INTE is SET - Interrupt Enable (BIT-RESET)-INTE is Reset - Interrupt Disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No handshaking is required, data is simply written to or read from a specific port. Mode 0 Basic Functional Definitions: * Two 8-bit ports and two 4-bit ports * Any Port can be input or output * Outputs are latched * Inputs are not latched * 16 different Input/Output configurations possible Single Bit Set/Reset Feature (Figure 5) Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports. CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 X X X DON'T CARE BIT SET/RESET 1 = SET 0 = RESET BIT SELECT 0 1 2 3 4 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 5 1 0 1 6 0 1 1 7 1 B0 1 B1 1 B2 BIT SET/RESET FLAG 0 = ACTIVE FIGURE 5. BIT SET/RESET FORMAT Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. MODE 0 PORT DEFINITION A B GROUP A PORT C PORT A (Upper) GROUP B # PORT C PORT B (Lower) D4 D3 D1 D0 0 0 0 0 Output Output 0 Output Output 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. FN2969 Rev 11.00 Dec 8, 2015 Page 6 of 30 82C55A Mode 0 (Basic Input) tRR RD tIR tHR INPUT tAR tRA CS, A1, A0 D7-D0 tRD tDF Mode 0 (Basic Output) tWW WR tWD tDW D7-D0 tAW tWA CS, A1, A0 OUTPUT tWB Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 A 82C55A 1 8 4 C D7 - D0 D7 D6 D5 D4 D3 D2 D1 D0 4 B 8 0 0 0 0 0 0 1 0 A C D7 - D0 4 PC3 - PC0 PB7 - PB0 8 4 PC7 - PC4 B 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 1 82C55A 1 8 4 C 4 B FN2969 Rev 11.00 Dec 8, 2015 0 CONTROL WORD #3 A D7 - D0 0 82C55A D7 D6 D5 D4 D3 D2 D1 D0 0 0 PA7 - PA0 CONTROL WORD #1 1 0 8 0 0 0 0 0 1 1 PA7 - PA0 A 82C55A 4 PC7 - PC4 D7 - D0 C 4 PC3 - PC0 PB7 - PB0 8 B 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 Page 7 of 30 82C55A Mode 0 Configurations (Continued) CONTROL WORD #4 CONTROL WORD #8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 A 82C55A 1 8 4 C D7 - D0 D7 D6 D5 D4 D3 D2 D1 D0 0 4 B 8 0 0 1 0 0 D7 - D0 PB7 - PB0 8 1 0 1 8 D7 - D0 0 1 0 0 0 PC3 - PC0 PB7 - PB0 1 A C D7 - D0 4 PC3 - PC0 PB7 - PB0 8 4 PC7 - PC4 B 1 8 4 B 8 0 0 1 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 0 PA7 - PA0 A 82C55A C D7 - D0 4 PC3 - PC0 PB7 - PB0 8 4 PC7 - PC4 CONTROL WORD #7 B 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 CONTROL WORD #11 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 A 82C55A 1 8 4 C 4 B FN2969 Rev 11.00 Dec 8, 2015 PC7 - PC4 D7 D6 D5 D4 D3 D2 D1 D0 4 C D7 - D0 0 82C55A 0 82C55A 0 8 PA7 - PA0 CONTROL WORD #10 A 0 4 B PA7 - PA0 D7 D6 D5 D4 D3 D2 D1 D0 0 C D7 - D0 8 4 PC3 - PC0 CONTROL WORD #6 1 0 A 1 4 B 0 0 D7 D6 D5 D4 D3 D2 D1 D0 4 C 0 0 PC7 - PC4 1 82C55A 0 0 CONTROL WORD #9 A 1 1 82C55A D7 D6 D5 D4 D3 D2 D1 D0 0 0 PA7 - PA0 CONTROL WORD #5 1 0 8 0 0 1 0 0 1 1 PA7 - PA0 A 82C55A 4 PC7 - PC4 D7 - D0 C 4 PC3 - PC0 PB7 - PB0 8 B 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 Page 8 of 30 82C55A Mode 0 Configurations (Continued) CONTROL WORD #12 CONTROL WORD #14 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 A 82C55A 1 8 4 C D7 - D0 D7 D6 D5 D4 D3 D2 D1 D0 0 4 B 8 0 1 1 1 0 1 0 8 A 82C55A 4 PC7 - PC4 C D7 - D0 4 PC3 - PC0 PB7 - PB0 8 B PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 CONTROL WORD #15 D7 D6 D5 D4 D3 D2 D1 D0 0 0 PA7 - PA0 CONTROL WORD #13 1 0 1 0 0 A 82C55A D7 - D0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 4 C 4 B 8 0 0 1 1 0 1 1 PA7 - PA0 8 A 82C55A 4 PC7 - PC4 C D7 - D0 4 PC3 - PC0 PB7 - PB0 Operating Modes Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or "hand shaking" signals. In mode 1, port A and port B use the lines on port C to generate or accept these "hand shaking" signals. 8 B CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 INTE A PC6, PC7 1 = INPUT 0 = OUTPUT PB7 - PB0 8 PC4 STBA PC5 IBFA INTRA PC3 RD * Each group contains one 8-bit port and one 4-bit control/data port * The 8-bit data port can be either input or output. Both inputs and outputs are latched. (Figures 6 and 7) PC3 - PC0 PA7-PA0 * Two Groups (Group A and Group B) Input Control Signal Definition PC7 - PC4 MODE 1 (PORT A) Mode 1 Basic Function Definitions: * The 4-bit port is used for control and status of the 8-bit port. PA7 - PA0 PC6, PC7 2 I/O MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 PB7-PB0 INTE B PC2 8 STBB PC1 IBFB PC0 INTRB STB (Strobe Input) A "low" on this input loads data into the input latch. IBF (Input Buffer Full F/F) A "high" on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. FN2969 Rev 11.00 Dec 8, 2015 RD FIGURE 6. MODE 1 INPUT Page 9 of 30 82C55A tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH INPUT FROM PERIPHERAL tPS FIGURE 7. MODE 1 (STROBED INPUT) INTR (Interrupt Request) INTE A A "high" on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the condition: STB is a "one", IBF is a "one" and INTE is a "one". It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. Controlled by Bit Set/Reset of PC6. INTE A Controlled by bit set/reset of PC4. INTE B INTE B Controlled by Bit Set/Reset of PC2. NOTE: 1. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generates an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF. Controlled by bit set/reset of PC2. Output Control Signal Definition (Figure 8 and 9) OBF - (Output Buffer Full F/F). The OBF output will go "low" to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF, (See Note 1). The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. ACK - (Acknowledge Input). A "low" on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data, (See Note 1). INTR - (Interrupt Request). A "high" on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a "one", OBF is a "one" and INTE is a "one". It is reset by the falling edge of WR. MODE 1 (PORT A) PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 PC4, PC5 1 = INPUT 0 = OUTPUT INTE A 8 PC7 OBFA PC6 ACKA INTRA PC3 WR PC4, PC5 2 MODE 1 (PORT B) PB7-PB0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 INTE B 8 PC1 OBFB PC2 ACKB PC0 INTRB WR FIGURE 8. MODE 1 OUTPUT FN2969 Rev 11.00 Dec 8, 2015 Page 10 of 30 82C55A tWOB WR tAOB OBF INTR tWIT ACK tAK tAIT OUTPUT tWB FIGURE 9. MODE 1 (STROBED OUTPUT) 8 PA7-PA0 RD CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 PC4 STBA PC5 IIBFA INTRA PC3 0 PC6, PC7 1 = INPUT 0 = OUTPUT PC6, PC7 2 PB7, PB0 WR PA7-PA0 WR CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 I/O OBFB PC2 PC0 PC7 OBFA PC6 ACKA INTRA PC3 1 PC4, PC5 1 = INPUT 0 = OUTPUT 8 PC1 1 8 PC4, PC5 PB7, PB0 2 I/O 8 PC2 STBB ACKB PC1 IBFB INTRB PC0 INTRB RD PORT A - (STROBED INPUT) PORT B - (STROBED OUTPUT) PORT A - (STROBED OUTPUT) PORT B - (STROBED INPUT) Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. FIGURE 10. COMBINATIONS OF MODE 1 Operating Modes Output Operations Mode 2 (Strobed Bidirectional Bus I/O) OBF - (Output Buffer Full). The OBF output will go "low" to indicate that the CPU has written data out to port A. This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). "Hand shaking" signals are provided to maintain proper bus flow discipline similar to Mode 1. Interrupt generation and enable/disable functions are also available. Mode 2 Basic Functional Definitions: * Used in Group A only * One 8-bit, bidirectional bus Port (Port A) and a 5-bit control Port (Port C) * Both inputs and outputs are latched * The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A) Bidirectional Bus I/O Control Signal Definition ACK - (Acknowledge). A "low" on this input enables the threestate output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 - (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4. Input Operations STB - (Strobe Input). A "low" on this input loads data into the input latch. IBF - (Input Buffer Full F/F). A "high" on this output indicates that data has been loaded into the input latch. INTE 2 - (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4. (Figures 11, 12, 13, 14) INTR - (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. FN2969 Rev 11.00 Dec 8, 2015 Page 11 of 30 82C55A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 INTRA PC3 1/0 1/0 1/0 PA7-PA0 PC2-PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT 8 PC7 OBFA INTE 1 PC6 ACKA INTE 2 PC4 STBA PC5 IBFA WR GROUP B MODE 0 = MODE 0 1 = MODE 1 PC2-PC0 RD FIGURE 11. MODE CONTROL WORD 3 I/O FIGURE 12. MODE 2 DATA FROM CPU TO 82C55A WR tAOB OBF tWOB INTR tAK ACK tST STB tSIB IBF tAD tPS tKD PERIPHERAL BUS tRIB tPH RD DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK ACK WR) FIGURE 13. MODE 2 (BIDIRECTIONAL) FN2969 Rev 11.00 Dec 8, 2015 Page 12 of 30 82C55A MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC3 PA7-PA0 1 0 1 1 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT PA7-PA0 8 OBFA PC7 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 PC6 ACKA PC4 STBA PC5 IBFA PC2-PC0 PC3 INTRA 3 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 I/O PB7-PB0 PC6 ACKA PC4 STBA PC5 IBFA PC2-PC0 3 I/O 8 MODE 2 AND MODE 1 (INPUT) PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 0 PC3 INTRA PA7-PA0 8 PC7 OBFA PC6 ACKA PC4 STBA PC5 IBFA PB7-PB0 WR OBFA WR PC3 RD PC7 PB7, PB0 8 MODE 2 AND MODE 1 (OUTPUT) 1 1/0 8 RD WR 1 0 PC2-PC0 1 = INPUT 0 = OUTPUT RD 1 0 INTRA CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 PC1 OBFB PC2 ACKB PC0 INTRB RD WR 8 PC7 OBFA PC6 ACKA PC4 STBA PC5 IBFA PB7-PB0 8 INTRA 8 PC2 STBB PC1 IBFB PC0 INTRB FIGURE 14. MODE 2 COMBINATIONS FN2969 Rev 11.00 Dec 8, 2015 Page 13 of 30 82C55A MODE DEFINITION SUMMARY MODE 0 MODE 1 MODE 2 IN OUT IN OUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In Out Out Out Out Out Out Out Out INTRB IBFB STBB INTRA STBA IBFA I/O I/O INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a "Set Mode" command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 17. Through a "Write Port C" command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a "Write Port C" command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in Mode 1 group or to change an interrupt enable flag, the "Set/Reset Port C Bit" command must be used. With a "Set/Reset Port C Bit" command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C are not affected by a "Set/Reset Port C Bit" command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the "Set Reset Port C Bit" command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 17. GROUP A ONLY Mode 0 or Mode 1 Only I/O I/O I/O INTRA STBA IBFA ACKA OBFA INPUT CONFIGURATION D7 D6 D5 I/O I/O IBFA D4 D3 D2 INTEA INTRA INTEB GROUP A D1 D0 IBFB INTRB GROUP B OUTPUT CONFIGURATION D7 D6 OBFA INTEA D5 D4 I/O I/O D3 D2 D1 D0 INTRA INTEB OBFB INTRB GROUP A GROUP B FIGURE 15. MODE 1 STATUS WORD FORMAT D7 D6 OBFA INTE1 D5 IBFA D4 D3 INTE2 INTRA D2 D1 D0 X X X GROUP A GROUP B (Defined by Mode 0 or Mode 1 Selection) FIGURE 16. MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C Status (Figures 15 and 16) In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes FN2969 Rev 11.00 Dec 8, 2015 Page 14 of 30 82C55A 1 or 2, Port C generates or accepts "hand shaking" signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly. There is not a special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. INTERRUPT ENABLE FLAG POSITION ALTERNATE PORT C PIN SIGNAL (MODE) INTE B PC2 ACKB (Output Mode 1) or STBB (Input Mode 1) INTE A2 PC4 STBA (Input Mode 1 or Mode 2) INTE A1 PC6 ACKA (Output Mode 1 or Mode 2) FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 Applications of the 82C55A The 82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system. It represents the optimum use of available pins and is flexible enough to interface almost any I/O device without the need for additional external logic. Each peripheral device in a microcomputer system usually has a "service routine" associated with it. The routine manages the software interface between the device and the CPU. The functional definition of the 82C55A is programmed by the I/O service routine and becomes an extension of the system software. By examining the I/O devices interface characteristics for both data transfer and timing, and matching this information to the examples and tables in the detailed operational description, a control word can easily be developed to initialize the 82C55A to exactly "fit" the application. Figures 18 through 24 present a few examples of typical applications of the 82C55A. INTERRUPT REQUEST PC3 MODE 1 (OUTPUT) 82C55A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC7 PC6 PC5 PC4 HIGH SPEED PRINTER HAMMER RELAYS DATA READY ACK PAPER FEED FORWARD/REV. PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 PC1 PC2 PAPER FEED FORWARD/REV. RIBBON CARRIAGE SEN. DATA READY ACK PC0 INTERRUPT REQUEST CONTROL LOGIC AND DRIVERS FIGURE 18. PRINTER INTERFACE FN2969 Rev 11.00 Dec 8, 2015 Page 15 of 30 82C55A INTERRUPT REQUEST PC3 MODE 1 (INPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL PC4 PC5 STROBE ACK INTERRUPT REQUEST PC3 MODE 1 (INPUT) 82C55A PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 B0 B1 B2 BURROUGHS SELF-SCAN B3 DISPLAY B4 B5 BACKSPACE CLEAR MODE 0 (INPUT) DATA READY ACK BLANKING CANCEL WORD PC1 PC2 PC6 PC7 82C55A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL PC4 PC5 PC6 PC7 STROBE ACK BUST LT TEST LT TERMINAL ADDRESS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 INTERRUPT REQUEST FIGURE 19. KEYBOARD AND DISPLAY INTERFACE FIGURE 20. KEYBOARD AND TERMINAL ADDRESS INTERFACE INTERRUPT REQUEST PA0 PA1 PA2 PA3 PA4 MODE 0 PA5 (OUTPUT) PA6 PA7 PC4 PC5 PC6 PC7 82C55A PC0 PC1 BIT SET/RESET PC2 PC3 PB0 PB1 PB2 MODE 0 (INPUT) PB3 PB4 PB5 PB6 PB7 LSB PC3 12-BIT D/A CONVERTER (DAC) ANALOG OUTPUT MSB 82C55A STB DATA SAMPLE EN STB LSB 8-BIT A/D CONVERTER (ADC) ANALOG INPUT MSB FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL FN2969 Rev 11.00 Dec 8, 2015 PA0 PA1 PA2 PA3 PA4 PA5 MODE 1 PA6 (OUTPUT) PA7 R0 R1 R2 CRT CONTROLLER R3 CHARACTER GEN. REFRESH BUFFER R4 CURSOR CONTROL R5 SHIFT CONTROL PC7 PC6 PC5 PC4 DATA READY ACK BLANKED BLACK/WHITE PC2 PC1 PC0 ROW STB COLUMN STB CURSOR H/V STB PB0 MODE 0 PB1 (OUTPUT) PB2 PB3 PB4 PB5 PB6 PB7 CURSOR/ROW/COLUMN ADDRESS H&V FIGURE 22. BASIC CRT CONTROLLER INTERFACE Page 16 of 30 82C55A INTERRUPT REQUEST INTERRUPT REQUEST PC3 MODE 2 82C55A PC3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D0 D1 D2 D3 D4 D5 D6 D7 PC4 PC5 PC7 PC6 DATA STB ACK (IN) DATA READY ACK (OUT) PC2 PC1 PC0 TRACK "0" SENSOR SYNC READY INDEX PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 FLOPPY DISK CONTROLLER AND DRIVE ENGAGE HEAD FORWARD/REV. READ ENABLE WRITE ENABLE DISC SELECT ENABLE CRC TEST BUSY LT FIGURE 23. BASIC FLOPPY DISC INTERFACE FN2969 Rev 11.00 Dec 8, 2015 MODE 1 (INPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 R3 R4 R5 R6 R7 PC4 PC5 PC6 STB ACK STOP/GO MACHINE TOOL 82C55A MODE 0 (INPUT) B LEVEL PAPER TAPE READER PC0 PC1 PC2 PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 START/STOP LIMIT SENSOR (H/V) OUT OF FLUID CHANGE TOOL LEFT/RIGHT UP/DOWN HOR. STEP STROBE VERT. STEP STROBE SLEW/STEP FLUID ENABLE EMERGENCY STOP FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE Page 17 of 30 82C55A Absolute Maximum Ratings TA = +25C Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . . GND-0.5V to VCC+0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Operating Temperature Range CX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C IX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C MX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to 125C Die Characteristics JA (C/W) JC(C/W) CERDIP Package. . . . . . . . . . . . . . . . . 50 10 CLCC Package . . . . . . . . . . . . . . . . . . 65 14 PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A PLCC Package. . . . . . . . . . . . . . . . . . . 55 N/A MQFP Package . . . . . . . . . . . . . . . . . . 62 N/A Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Junction Temperature CDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C (PLCC and MQFP Lead Tips Only) Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications SYMBOL VCC = 5.0V 10%; TA = Operating Temperature Range PARAMETER TEST CONDITIONS MIN MAX UNITS VIH Logical One Input Voltage 2.0 2.2 - V VIL Logical Zero Input Voltage - 0.8 V 3.0 VCC -0.4 - V - 0.4 V VOH Logical One Output Voltage IOH = -2.5mA, IOH = -100A VOL Logical Zero Output Voltage IOL +2.5mA II Input Leakage Current VIN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 +1.0 A IO I/O Pin Leakage Current VO = VCC or GND, D0 - D7 -10 +10 A Bus Hold High Current VO = 3.0V. Ports A, B, C TA = -55C -50 -450 A TA = +128C -50 -400 A TA = -55C 50 450 A TA = +128C 50 400 A -2.5 Note 2, 4 mA IBHH IBHL IDAR Bus Hold Low Current VO = 1.0V. Port A ONLY Darlington Drive Current Ports A, B, C. Test Condition 3 ICCSB Standby Power Supply Current VCC = 5.5V, VIN = VCC or GND. Output Open - 10 A ICCOP Operating Power Supply Current TA = +25C, VCC = 5.0V, Typical (See Note 3) - 1 mA/MHz NOTES: 2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA). 4. Tested as VOH at -2.5mA. Capacitance TA = +25C SYMBOL PARAMETER TYPICAL UNITS CIN Input Capacitance 10 pF CI/O I/O Capacitance 20 pF FN2969 Rev 11.00 Dec 8, 2015 TEST CONDITIONS FREQ = 1MHz, All Measurements are referenced to device GND Page 18 of 30 82C55A AC Electrical Specifications VCC = +5V 10%, GND = 0V; TA = Operating Temperature Range 82C55A-5 SYMBOL PARAMETER 82C55A MIN MAX MIN MAX UNITS TEST CONDITIONS READ TIMING (1) tAR Address Stable Before RD 0 - 0 - ns (2) tRA Address Stable After RD 0 - 0 - ns (3) tRR RD Pulse Width 250 - 150 - ns (4) tRD Data Valid From RD - 200 - 120 ns 1 (5) tDF Data Float After RD 10 75 10 75 ns 2 (6) tRV Time Between RDs and/or WRs 300 - 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0 - 0 - ns (8) tWA Address Stable After WR 20 - 20 - ns (9) tWW WR Pulse Width 100 - 100 - ns (10) tDW Data Valid to WR High 100 - 100 - ns (11) tWD Data Valid After WR High 30 - 30 - ns OTHER TIMING (12) tWB WR = 1 to Output - 350 - 350 ns (13) tIR Peripheral Data Before RD 0 - 0 - ns (14) tHR Peripheral Data After RD 0 - 0 - ns (15) tAK ACK Pulse Width 200 - 200 - ns (16) tST STB Pulse Width 100 - 100 - ns (17) tPS Peripheral Data Before STB High 20 - 20 - ns (18) tPH Peripheral Data After STB High 50 - 50 - ns (19) tAD ACK = 0 to Output - 175 - 175 ns 1 (20) tKD ACK = 1 to Output Float 20 250 20 250 ns 2 (21) tWOB WR = 1 to OBF = 0 - 150 - 150 ns 1 (22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1 (23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1 (24) tRIB RD = 1 to IBF = 0 - 150 - 150 ns 1 (25) tRIT RD = 0 to INTR = 0 - 200 - 200 ns 1 (26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1 (27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1 (28) tWIT WR = 0 to INTR = 0 - 200 - 200 ns 1 (29) tRES Reset Pulse Width 500 - 500 - ns 1, (Note) 1 NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum. FN2969 Rev 11.00 Dec 8, 2015 Page 19 of 30 82C55A Timing Waveforms tRR (3) RD tIR (13) tHR (14) INPUT tAR (1) tRA (2) CS, A1, A0 D7-D0 tRD (4) tDF (5) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) WR tDW (10) tWD (11) D7-D0 tAW (7) tWA (8) CS, A1, A0 OUTPUT tWS (12) FIGURE 26. MODE 0 (BASIC OUTPUT) tST (16) STB IBF tSIB (23) tSIT (26) tRIB (24) tRIT (25) INTR RD tPH (18) INPUT FROM PERIPHERAL tPS (17) FIGURE 27. MODE 1 (STROBED INPUT) FN2969 Rev 11.00 Dec 8, 2015 Page 20 of 30 82C55A Timing Waveforms (Continued) tWOB (21) WR tAOB (22) OBF tWIT (28) INTR ACK tAK (15) tAIT (27) OUTPUT tWB (12) FIGURE 28. MODE 1 (STROBED OUTPUT) DATA FROM CPU TO 82C55A WR (NOTE) tAOB (22) OBF tWOB (21) INTR tAK (15) ACK tST (16) STB (NOTE) IBF tSIB (23) tAD (19) tPS (17) tKD (20) PERIPHERAL BUS tRIB (24) tPH (18) RD DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU FIGURE 29. MODE 2 (BIDIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF MASK ACK WR) FN2969 Rev 11.00 Dec 8, 2015 Page 21 of 30 82C55A Timing Waveforms (Continued) A0-A1, CS tWA (8) tAW (7) DATA BUS tDW (10) tWD (11) A0-A1, CS tRA (2) tAR (1) tRR (3) RD (4) tRD WR tDF (5) DATA BUS VALID HIGH IMPEDANCE tWW (9) FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING AC Test Circuit AC Testing Input, Output Waveforms V1 INPUT OUTPUT VIH + 0.4V VOH 1.5V R1 OUTPUT FROM DEVICE UNDER TEST TEST POINT R2 C1 (SEE NOTE) 1.5V VIL - 0.4V VOL AC Testing: All AC Parameters tested as per test circuits. Input RISE and FALL times are driven at 1ns/V. TEST CONDITION DEFINITION TABLE NOTE: Includes STRAY and JIG Capacitance FN2969 Rev 11.00 Dec 8, 2015 TEST CONDITION V1 R1 R2 C1 1 1.7V 523 Open 150pF 2 VCC 2k 1.7k 50pF 3 1.5V 750 Open 50pF Page 22 of 30 82C55A Burn-In Circuits CERDIP F14 F4 5 36 F2 F3 6 35 F5 GND F0 7 8 34 33 GND 6 5 4 3 2 F2 37 F14 4 F13 F13 F9 F11 38 F12 3 F6 F12 F8 F7 F11 39 F8 40 2 F9 1 F7 F4 F6 F3 CLCC 1 44 43 42 41 40 7 39 8 38 F5 F11 F0 9 37 F15 F12 10 36 11 35 F11 F12 F15 F10 10 31 F13 F1 F10 F6 11 30 F14 F6 12 34 F13 F15 F7 13 33 F14 F8 14 32 F15 F9 15 31 F11 F10 16 30 F12 F6 17 29 15 26 F6 16 25 F13 F7 17 24 F14 F8 18 23 F15 19 22 F11 20 21 F12 F9 F10 NOTES: VCC C1 18 19 20 21 22 23 24 25 26 27 28 C1 NOTES: 1. VCC = 5.5V 0.5V 1. C1 = 0.01F minimum 2. VIH = 4.5V 10% 2. All resistors are 47k 5% 3. VIL = -0.2V to 0.4V 3. f0 = 100kHz 10% 4. GND = 0V 4. f1 = f0 2; f2 = f1 2; . . . ; f15 = f14 2 FN2969 Rev 11.00 Dec 8, 2015 F13 F10 F12 VCC 27 F14 14 F15 F9 F11 F11 13 F12 28 F8 F10 29 F9 12 32 F8 F7 9 F7 F1 Page 23 of 30 82C55A GLASSIVATION: Die Characteristics Type: SiO2 Thickness: 8kA 1kA METALLIZATION: Type: Silicon - Aluminum Thickness: 11kA 1kA Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR RESET CS D0 GND D1 A1 D2 A0 D3 PC7 D4 PC6 D5 PC5 D6 PC4 D7 PC0 VCC PC1 PC2 FN2969 Rev 11.00 Dec 8, 2015 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Page 24 of 30 82C55A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 8, 2015 FN2969.11 CHANGE - Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support (c) Copyright Intersil Americas LLC 1998-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2969 Rev 11.00 Dec 8, 2015 Page 25 of 30 82C55A Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN2969 Rev 11.00 Dec 8, 2015 Page 26 of 30 82C55A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A) 40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL (c) E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 b2 ccc M C A-B S D S eA/2 NOTES - 0.225 - 5.72 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 5 E 0.510 0.620 15.75 5 eA e b MAX b A A MIN A A L MILLIMETERS MAX M (b) D BASE PLANE MIN b1 SECTION A-A D S INCHES SYMBOL c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. e 12.95 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. N 40 40 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. FN2969 Rev 11.00 Dec 8, 2015 Page 27 of 30 82C55A Ceramic Leadless Chip Carrier Packages (CLCC) J44.A MIL-STD-1835 CQCC1-N44 (C-5) 44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B E h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 -E- B1 e L -H- L3 MILLIMETERS MAX MAX NOTES A 0.064 0.120 1.63 3.05 6, 7 0.054 0.088 1.37 2.24 - B 0.033 0.039 0.84 0.99 4 B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.640 0.662 16.26 16.81 - D1 0.500 BSC 12.70 BSC - D2 0.250 BSC 6.35 BSC - D3 - 0.662 E 0.640 0.662 16.26 16.81 2 16.81 - E1 0.500 BSC 12.70 BSC - E2 0.250 BSC 6.35 BSC - E3 e - 0.662 0.050 BSC 0.015 - - 16.81 1.27 BSC 0.38 2 - - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.38 - ND 11 11 3 NE 11 11 3 N 44 44 -F- 3 Rev. 0 5/18/94 B3 E1 E2 MIN A1 e1 0.007 M E F S H S MIN 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 L1 D2 e1 D1 NOTES: 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. FN2969 Rev 11.00 Dec 8, 2015 Page 28 of 30 82C55A Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L N44.65 (JEDEC MS-018AC ISSUE A) 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL D2/E2 E1 E C L D2/E2 VIEW "A" 0.020 (0.51) MIN A1 A D1 D SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) MAX MILLIMETERS MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N 44 44 6 Rev. 2 11/97 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN MIN VIEW "A" TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions. FN2969 Rev 11.00 Dec 8, 2015 Page 29 of 30 82C55A Metric Plastic Quad Flatpack Packages (MQFP) D Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES SYMBOL -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M 0.008 C A-B S 0o MIN D S b A2 A1 0o-7o L 12o-16o b1 MILLIMETERS MIN MAX NOTES A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 - N 44 44 7 e 0.032 BSC 0.80 BSC Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. BASE METAL FN2969 Rev 11.00 Dec 8, 2015 MAX 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 WITH PLATING MIN 7. "N" is the number of terminal positions. 0.13/0.23 0.005/0.009 Page 30 of 30