Semiconductor Group 1 1.96
•2 097 152 words by 8-bit organization
•0 to 70 °C operating temperature
•Performance:
•Single + 3.3 V (± 0.3 V) supply
•Low power dissipation
max. 432 mW active (-50 version)
max. 396 mW active (-60 version)
max. 360 mW active (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
•Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
•Hyper page mode (EDO) capability
•All inputs, outputs and clocks fully TTL-compatible
•2048 refresh cycles / 32 ms (2k-Refresh)
•Plastic Package: P-SOJ-28-3 400 mil
-50 -60 -70
tRAC RAS access time 50 60 70 ns
tCAC CAS access time 13 15 20 ns
tAA Access time from address 25 30 35 ns
tRC Read/Write cycle time 84 104 124 ns
tHPC Hyper page mode (EDO)
cycle time 20 25 30 ns
2M x 8 - Bit Dynamic RAM
2k Refresh
(Hyper Page Mode- EDO)
Advanced Information
HYB3117805BSJ -50/-60/-70
Semiconductor Group 2
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
The HYB 3117805BSJ is a 16 MBit dynamic RAM organized as 2 097 152 words by 8-bits. The HYB
3117805BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 3117805BSJ to be packaged in a st andard SOJ 28
plastic package with 400 mil width. These packages provide high system bit densities and are
compatible with commonly used automatic testing and insertion equipment. System-oriented
features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic
device families such as Schottky TTL.
Ordering Information
Pin Names
Type Ordering Code Package Descriptions
HYB 3117805BJ-50 Q67100-Q1151 P-SOJ-28-3 400 mil DRAM (access time 50 ns)
HYB 3117805BJ-60 Q67100-Q1152 P-SOJ-28-3 400 mil DRAM (access time 60 ns)
HYB 3117805BJ-70 P-SOJ-28-3 400 mil DRAM (access time 70 ns)
A0-A10 Row Address Inputs
A0-A9 Column Address Inputs
RAS Row Address Strobe
OE Output Enable
I/O1-I/O8 Data Input/Output
CAS Column Address Strobe
WE Read/Write Input
VCC Power Supply (+ 3.3 V)
VSS Ground (0 V)
N.C. not connected
Semiconductor Group 3
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Pin Configuration
P-SOJ-28-3 400 mil
1
2
3
4
5
6
9
10
11
12
13
14
23
24
25
26
27
28 VSS
I/O8
I/O7
I/O6
I/O5
CAS
A8
A7
A6
A5
A4
VSS
VCC
I/O1
I/O2
I/O3
N.C.
A10
A0
A1
A2
A3
VCC 15
16
17
18
19
20
O
OE
A9
WE
I/O4
722
218
RAS
Semiconductor Group 4
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Block Diagram
No. 2 Clock
Generator
Column
Address
Buffer(10)
Refresh
Controller
Refresh
Counter (11)
Address
Buffers(11)
Row
No. 1 Clock
Generator
&Data in
Buffer Data out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
Memory Array
2048x1024x8
Row
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
CAS
2048
1024
x8
.
RAS
10
11
8
I/O1 I/O2
OE
11 11
A10
8
8
10
I/O8
Semiconductor Group 5
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation.....................................................................................................................0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those liste d under “Absolute Maximum Ratings” may cause permanent dama ge of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Test
Condition
min. max.
Input high voltage VIH 2.0 Vcc+0.5 V 1)
Input low voltage VIL – 0.5 0.8 V 1)
TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1)
TTL Output low voltage (IOUT = 2 mA) VOL –0.4V
1)
CMOS Output high voltage (IOUT = –100 uA) VOH VCC-0.2 – V
CMOS Output low voltage (IOUT = 100 uA) VOL –0.2V
Input leakage current
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA1)
Average VCC supply current:-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling, tRC = tRC min.)
ICC1 –
–
–
120
110
100
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby VCC supply current (RAS =CAS=VIH)ICC2 –2mA–
Average VCC supply current, during RAS-only
refresh cycles: -50 ns version
-60 ns version
-70 ns version
(RAS cycling: CAS = VIH, tRC = tRC min.)
ICC3 –
–
–
120
110
100
mA
mA
mA
2) 4)
2) 4)
2) 4)
Semiconductor Group 6
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Average VCC supply current, during hyper page
mode EDO): -50 ns version
-60 ns version
-70 ns version
(RAS = VIL, CAS, address c ycling, tPC = tPC min.)
ICC4 –
–
–
70
55
45
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V) ICC5 –1mA
1)
Average VCC supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
-70 ns version
(RAS, CAS cycling, tRC = tRC min.)
ICC6 –
–
–
120
110
100
mA
mA
mA
2) 4)
2) 4)
2) 4)
Average Self Refresh Current
(CBR cylce with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7 _1mA
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , f = 1 MHz
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A10) CI1 –5pF
Input capacitance (RAS, CAS, WE, OE)CI2 –7pF
I/O capacitance (I/O1-I/O8) CIO –7pF
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Test
Condition
min. max.
Semiconductor Group 7
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
AC Characteristics 5 )6 ) 16E
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60 -70
min. max. min. max. min. max.
common parameters
Random read or write cycle time tRC 84 – 104 – 124 – ns
RAS precharge time tRP 30 – 40 – 50 – ns
RAS pulse width tRAS 50 10k 60 10k 70 10k ns
CAS pulse width tCAS 8 10k 10 10k 12 10k ns
Row address setup time tASR 0–0–0–ns
Row address hold time tRAH 8–10–10–ns
Column address setup time tASC 0–0–0–ns
Column address hold time tCAH 8–10–12–ns
RAS to CAS delay time tRCD 12 37 14 45 14 53 ns
RAS to column address delay tRAD 10 25 12 30 12 35 ns
RAS hold time tRSH 13 15 – 17 – ns
CAS hold time tCSH 40 50 – 60 – ns
CAS to RAS precharge time tCRP 5–5–5–ns
Transition time (rise and fall) tT150150150ns7
Refresh period tREF –32–32–32ms
Read Cycle
Access time from RAS tRAC –50–60–70ns8, 9
Access time from CAS tCAC –13–15–17ns8, 9
Access time from col umn address tAA –25–30–35ns8,10
OE access time tOEA –13–15–17ns
Column address to RAS lead t ime tRAL 25 – 30 – 35 – ns
Read command setup time tRCS 0–0–0–ns
Read command hold time tRCH 0–0–0–ns11
Read command hold time
referenced to RAS tRRH 0–0–0–ns11
CAS to output in low-Z tCLZ 0–0–0–ns8
Output buffer turn-off delay tOFF 013015017ns12
Output turn-off delay from OE tOEZ 013015017ns12
Semiconductor Group 8
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Data to CAS low delay tDZC 0–0–0–ns13
Data to OE low delay tDZO 0–0–0–ns13
CAS high to data delay tCDD 10 – 13 – 15 – ns 14
OE high to data delay tODD 10 – 13 – 15 – ns 14
Write Cycle
Write command hold time tWCH 8–10–10–ns
Write command pulse width tWP 8–10–10–ns
Write command setup time tWCS 0–0–0–ns15
Write command to RAS lead time tRWL 13 – 15 – 17 – ns
Write command to CAS lead time tCWL 13 – 15 – 17 – ns
Data setup time tDS 0–0–0–ns16
Data hold time tDH 8–10–12–ns16
Read-modify-Write Cycle
Read-write cycle time tRWC 113 – 138 – 162 – ns
RAS to WE delay time tRWD 64 – 77 – 89 – ns 15
CAS to WE delay time tCWD 27 – 32 – 36 – ns 15
Column address to WE delay t ime tAWD 39 – 47 – 54 – ns 15
OE command hold time tOEH 10 – 13 – 15 – ns
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle
time tHPC 20 – 25 – 30 – ns
CAS precharge time tCP 8–10–10–ns
Access time from CAS precharge tCPA –27–32–37ns7
Output data hold time tCOH 5–5–5–ns
RAS pulse width in EDO mode tRAS 50 200k 60 200k 70 200k ns
CAS precharge to RAS Delay tRHPC 27 – 32 – 37 – ns
AC Cha racte ris tics (cont’d) 5)6) 16E
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60 -70
min. max. min. max. min. max.
Semiconductor Group 9
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-
write cycle time tPRWC 58 – 68 – 77 – ns
CAS precharge to WE tCPWD 41 – 49 – 56 – ns
CAS-before-RAS Refresh Cycle
CAS setup time tCSR 10 – 10 – 10 – ns
CAS hold time tCHR 10 – 10 – 10 – ns
RAS to CAS precharge time tRPC 5–5–5–ns
Write to RAS precharge time tWRP 10 – 10 – 10 – ns
Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 – 40 – 40 – ns
Self Refresh Cycle
RAS pulse width tRASS 100k _ 100k _ 100k _ ns 17
RAS precharge tRPS 95 _ 110 _ 130 _ ns 17
CAS hold time tCHS -50 _ -50 _ -50 _ ns 17
Test Mode
Write command setup time tWTS 10 – 10 – 10 – ns
Write command hold time tWTH 10 – 10 – 10 – ns
CAS hold time tCHRT 30 – 30 – 30 – ns
AC Cha racte ris tics (cont’d) 5)6) 16E
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60 -70
min. max. min. max. min. max.
Semiconductor Group 10
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Notes:
1) All voltages are referen c ed t o VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cyc le rate.
3) ICC1 and ICC4 depend on output loa ding. Specified valu es are obtained wi th the out put open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimu m of 8 CAS -before-RAS initial iza tio n c ycles instead of 8 RAS cyc les are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, t AA,tCPA, t OEA . tCAC is measured from tristate.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than th e sp ec ifi ed tRCD (max.) limit, then acce ss ti me is cont rolled by tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than th e sp ec if ied tRAD (max.) limit, then acc es s tim e is co nt rolled by tAA.
11) Either tRCH or tRRH mus t be sa ti sfied for a read cycle .
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not
referen ce d t o out put voltage lev els . tOFF is referenced from the risi ng edge of RAS or CAS, whichever occurs
last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satis f ied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electric al characte ristics only. I f tWCS > tWCS (min.), the cycle is an early writ e cycle and data out pin w ill remain
open-c irc uit (high impedance) through the entire cyc le; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.),
the cycle is a read-write cycle and I/O will contain da ta rea d from the selected c ells. If neither of the a bove
sets of con dit ions is satisfied , the c ondition of I/O (at acc es s time) is indetermina te .
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)Whe n usin g Self Refres h mo de, the follow ing ref resh operat ions mus t be p erforme d to en sure p rop er DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addre sses are being refreshed in any ot her manner (ROR - Distribut ed/Burst; or CBR-Burs t) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit fro m S elf Re fre sh
Semiconductor Group 11
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Read Cycle
Row
Column
Row
Valid Data Out
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
V
OL
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
RAH
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASC
t
ASR
t
RCH
t
RRH
t
RCS
t
AA
t
OEA
t
CLZ
t
CAC
t
OEZ
t
ODD
t
CDD
t
OFF
t
DZC
t
DZO
t
RAC
Hi ZHi Z
“H” or “L” WL1
Semiconductor Group 12
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Write Cycle (Early Write)
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
V
OL
.
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASR
t
CWL
t
RWL
t
WP
t
ASC
t
WCH
Valid Data In
t
DS
t
DH
Hi Z
Column RowRow
t
RAH
t
WCS
“H” or “L” WL2
Semiconductor Group 13
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Write Cycle (OE Controlled Write)
Valid Data
t
RWL
t
WP
t
OEH
t
ODD
t
CWL
t
DZO
t
OEA
t
CLZ
t
DS
t
OEZ
t
DH
t
RC
VIH
VIL Row
t
DZC
“H” or “L”
Hi-Z
Hi-Z
Column
Row
t
ASC
t
RAD
t
RAL
t
CAH
t
RAH
RAS
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
V
OL
.
t
RAS
t
CSH
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
ASR
t
ASR
WL3
Semiconductor Group 14
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Read-Write (Read-Modify-Write) Cycle
RowRow
t
CSH
t
CAS
t
CRP
t
RWC
t
AWD
t
ASR
t
RP
t
RAS
t
RAH
t
CAH
I/O
(Outputs)
VOH
V
OL
VIH
VIL
VIH
VIL
I/O
(Inputs)
OE
WE
VIH
VIL
t
ASR
Column
t
RCD
t
DH
t
RSH
t
RAD
t
CWD
t
OEH
t
RWD
t
RWL
t
CWL
t
CLZ
t
WP
t
RCS
t
AA
t
OEA
t
DS
t
DZC
t
DZO
t
ODD
t
CAC
t
OEZ
Valid
Data in
Data
Out
t
RAC
“H” or “L”
t
ASC
VIH
VIL
VIH
VIL
RAS
CAS
Address
VIH
VIL
WL4
Semiconductor Group 15
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hyper Page Mode (EDO) Read Cycle
t
RP
t
RSH
t
CAS
t
CAS
t
CP
t
CRP
t
RAL
t
CAH
t
CAH
t
ASC
t
CSH
t
CAS
t
RCD
t
RAH
t
ASR
Column 2
Row
Data Out
RAS
I/O
WE
Address
CAS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
“H” or “L”
VOH
VOL
OE
t
RAS
t
CRP
t
ASC
t
HPC
t
CAH
t
RAD
t
RHCP
t
ASC
t
RCS
t
RRH
t
RCH
(Output)
t
RAC
t
AA
t
CAC
t
CLZ
t
OEA
t
OES
t
COH
t
CAC
t
AA
t
CPA
Data Out
Column N
Column 1
Data Out
t
OEZ
t
OFF
t
CAC
t
AA
t
CPA
12
t
COH
N
WL5
Semiconductor Group 16
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hyper Page Mode (EDO) Early Write Cycle
t
RP
t
RSH
t
CAS
t
CAS
t
CP
t
CRP
t
RAL
t
CAH
t
CAH
t
ASC
t
CWL
t
WCS
t
WP
t
WCH
t
CSH
t
CAS
t
RCD
t
RAH
t
ASR
t
DH
t
DS
t
DH
t
DS
Column 1 Column 2
Row
Addr
Data In N
Data In 2
Data In 1
Column N
RAS
I/O (Input)
WE
Address
CAS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
“H” or “L”
VOH
VOL
OE
t
RAS
t
CRP
t
ASC
t
CWL
t
WCS
t
WP
t
WCH
t
CWL
t
WCS
t
WP
t
WCH
t
RWL
t
DH
t
DS
t
HPC
t
CAH
t
RAD
t
RHCP
t
ASC
WL8
Semiconductor Group 17
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
t
CAH
t
CP
t
DZC
t
DZO
t
RAC
t
CAC
t
CLZ
t
RCS
t
AA
t
OEA
t
RCD
t
RAD
t
RAH
t
ASR
t
ASC
t
CAS
t
CAS
t
PRWC
t
CWD
t
CAH
t
ASC
t
CAS
t
RSH
t
RP
t
CRP
t
ASR
t
CAH
t
ASC
t
RAL
t
CWD
t
RWD
t
CWL
t
CWL
t
CWD
t
AWD
t
AWD
t
WP
t
WP
t
CWL
t
RWL
t
AWD
t
WP
t
ODD
t
OEH
t
DH
t
DS
t
CPA
t
OEZ
t
CLZ
t
DZC
t
AA
t
CAC
t
OEA
t
DS
t
OEZ
t
DH
t
OEH
t
AA
t
ODD
t
DZC
t
CPA
t
OEA
t
CLZ
t
DS
t
DH
t
OEH
t
ODD
RAS VIH
VIL
CAS VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
V
OL
WE
OE
Address
I/O
(Inputs)
I/O
(Outputs)
Data In Data In Data In
Data
Out Out
Data
Data
Out
Row
ColumnColumnRow
t
RASP
t
CSH
Column
t
CPWD
t
CPWD
WL17
Semiconductor Group 18
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
RAS-Only Refresh Cycle
t
CRP
t
RAH
t
RP
t
RAS
t
RC
t
ASR
t
ASR
t
RPC
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Row
Row
HI-Z
Address
RAS
CAS
I/O
(Outputs)
“H” or “L” WL9
Semiconductor Group 19
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
CAS-Before-RAS Refresh Cycle
t
RP
t
RAS
t
RP
t
RC
t
CRP
t
CP
t
RPC
t
CHR
t
WRH
t
WRP
t
CSR
t
RPC
t
OFF
t
OEZ
t
CDD
t
ODD
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
HI-Z
“H” or “L”
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
VOH
VOL
WL10
Semiconductor Group 20
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hidden Refresh Cycle (Read) Cycle
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
CAS
t
RC
t
RC
t
RAS
t
RAS
t
RP
t
RP
t
CRP
t
CHR
t
RAD
t
CAH
t
ASC
t
RAH
t
ASR
t
ASR
t
RCS
t
RRH
t
AA
t
DZC
t
DZO
t
CAC
t
RAC
t
CLZ
t
OEZ
t
OFF
t
ODD
t
CDD
t
RCD
t
RSH
t
OEA
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
t
WRP
t
WRH
“H” or “L”
Valid Data Out
Row
Column
Row
HI-Z
VOH
VOL
WL11
Semiconductor Group 21
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Hidden Refresh Early Write Cycle
RAS
I/O
(Output)
I/O
(Input)
WE
Address VIH
VIL
VIH
VIL
VIH
VIL
CAS
VIH
VIL
VIH
VIL
“H” or “L”
t
RC
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
WCS
t
WCH
t
WP
t
ASR
t
RAH
t
DS
t
DH
t
ASR
t
CRP
t
CHR
t
RP
t
RAS
t
RC
t
RP
t
ASC
Row Row
Valid Data
HI-Z
Column
VOH
VOL
t
WRP
t
WRH
WL12
Semiconductor Group 22
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Self Refresh
t
RPS
t
RASS
t
RP
t
CRP
t
CP
t
RPC
t
WRH
t
WRP
t
CSR
t
OFF
t
OEZ
t
CDD
t
ODD
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
HI-Z
“H” or “L”
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
CAS
VOH
VOL
t
CHS
WL13
Semiconductor Group 23
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
CAS-Before-RAS Refresh Counter Test Cycle
t
CSR
t
ASR
t
ASC
t
CHR
t
CP
t
WRP
t
RAL
t
CAH
t
RSH
t
RP
t
RAS
t
CAS
t
RCS
t
CDD
t
CAC
t
AA
t
WRH
t
OEA
t
ODD
t
CLZ
t
DZC
t
DZO
t
OEZ
t
OFF
t
RWL
t
CWL
t
WCH
t
WCS
t
WRH
t
WRP
t
DS
t
DH
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
RAS
I/O
(Inputs)
OE
WE
Address
CAS
I/O
(Outputs)
I/O
(Outputs)
I/O
(Inputs)
WE
OE
Column Row
Data Out
Data In
HI-Z
Read Cycle:
Write Cycl e:
tRRH tRCH
Semiconductor Group 24
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Test Mode Entry
t
RC
t
RAS
t
RP
t
RPC
t
CRP
t
CHR
t
WTH
t
RPC
t
RP
t
CP
t
CSR
t
WTS
t
CDD
t
OFF
t
OEZ
t
ODD
I/O
(Outputs)
VOH
V
OL
VIH
VIL
VIH
VIL
I/O
(Inputs)
OE
WE
VIH
VIL
CAS
RAS
VIH
VIL
VIH
VIL
“H” or “L”
HI-Z
Address
t
RAH
t
ASR
VIH
VIL Row
WL15
HI-Z
Semiconductor Group 25
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Package Outline
(Small Outline J-lead, SMD)
Plastic Package P-SOJ-28-3 (400mil)
1) Does not include plastic or metal protrusion of 0.15 max. per side
28x
0.18
1.27 0.81max
-0.13
0.51 0.18
1)
1)
-0.25
18.54
Index Marking
0.1
114
1528
10.16
+0.13
9.4
11.18
+0.13
0.25
-
+
30
O
MM
-
-
GPJ05699
