Product Folder Sample & Buy Support & Community Tools & Software Technical Documents PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 PCA9534 Remote 8-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output and Configuration Registers 1 Features * * * * 1 * * * * * * * * * * * * * 2 Description This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. Low Standby Current Consumption of 1 A Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant I/O Ports 400-kHz Fast I2C Bus Three Hardware Address Pins Allow up to Eight Devices on the I2C/SMBus Allows Up to 16 Devices on the I2C/SMBus When Used in Conjunction with the PCA9534A See Device Comparison Table for I2C Expander offerings Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset Power-Up With All Channels Configured as Inputs No Glitch on Power Up Noise Filter on SCL/SDA Inputs Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) The PCA9534 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low) register. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the PCA9534 in the event of a timeout or other improper operation by utilizing the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine. The PCA9534 open-drain interrupt (INT) output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. Device Information(1) PART NUMBER PCA9534 PACKAGE BODY SIZE (NOM) SSOP (16) 6.20 mm x 5.30 mm VQFN (16) 4.00 mm x 4.00 mm QFN (16) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 14 4 13 5 12 6 11 7 10 8 9 A1 A0 VCC S DA SDA VCC RGT PACKAGE (TOP VIEW) A2 1 16 15 14 13 12 P0 2 11 INT P1 3 10 P7 P2 4 9 P6 5 6 7 8 SCL A2 P0 P1 P2 16 15 14 13 12 SCL 11 INT 2 3 10 P7 1 9 P6 4 5 6 7 8 P3 GND P4 P5 3 VCC SDA SCL INT P7 P6 P5 P4 P5 15 P4 16 2 GND 1 P3 A0 A1 A2 P0 P1 P2 P3 GND A0 RGV PACKAGE (TOP VIEW) A1 DB, DGV, DW, OR PW PACKAGE (TOP VIEW) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 2 3 4 5 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 6 6 6 7 8 8 9 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Electrical Characteristics........................................... I2C Interface Timing Requirements........................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 12 9 Detailed Description ............................................ 15 9.1 Functional Block Diagram ....................................... 15 9.2 Device Functional Modes........................................ 16 9.3 Programming........................................................... 17 10 Application And Implementation ....................... 23 10.1 Typical Application ............................................... 23 11 Power Supply Recommendations ..................... 25 11.1 Power-On Reset Requirements ........................... 25 11.2 Power-On Reset Errata......................................... 26 12 Device and Documentation Support ................. 27 12.1 Trademarks ........................................................... 27 12.2 Electrostatic Discharge Caution ............................ 27 12.3 Glossary ................................................................ 27 13 Mechanical, Packaging, and Orderable Information ........................................................... 27 3 Revision History Changes from Revision F (June 2010) to Revision G Page * Added Interrupt Errata section.............................................................................................................................................. 17 * Added Power-On Reset Errata section. ............................................................................................................................... 26 2 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 4 Description (Continued) INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9534 can remain a simple slave device. The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current consumption. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight devices to share the same I2C bus or SMBus. The PCA9534 is pin-to-pin and I2C address compatible with the PCF8574. However, software changes are required due to the enhancements in the PCA9534 over the PCF8574. The PCA9534 is a low-power version of the PCA9554. The only difference between the PCA9534 and PCA9554 is that the PCA9534 eliminates an internal I/O pullup resistor, which dramatically reduces power consumption in the standby mode when the I/Os are held low. The PCA9534A and PCA9534 are identical, except for their fixed I2C address. This allows for up to 16 of these devices (8 of each) on the same I2C bus. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 3 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com 5 Device Comparison Table MAX FREQUE NCY DEVICE I2C ADDRES S NO. OF GPIOs INTERRU PT OUTPUT RESET INPUT CONFIGURATIO N REGISTERS 5-V TOLERAN T PUSHPULL I/O TYPE OPENDRAIN I/O TYPE COMMENT VCC = 1.65 to 5.5 V TCA6408 400 0100 00x 8 Yes Yes Yes Yes Yes No Power on reset, tf (fall time) > 100 ms and tr (ramp time) < 10 ms TCA6408 400 0100 00x 8 Yes Yes Yes Yes Yes No Unrestricted power on reset ramp/fall time. Both tf (fall time) and TRT (ramp time) can be between 0.1 ms and 2000 ms TCA6416 400 0100 00x 16 Yes Yes Yes Yes Yes No Power on reset, tf (fall time) > 100 ms and TRT (ramp time) < 10 ms TCA6416 A 400 0100 00x 16 Yes Yes Yes Yes Yes No Unrestricted power on reset ramp/fall time. Both tf (fall time) and TRT (ramp time) can be between 0.1 ms and 2000ms TCA6424 400 0100 00x 24 Yes Yes Yes Yes Yes No Power on reset, tf (fall time) > 100 ms and TRT (ramp time) < 10 ms TCA9535 400 0100 xxx 16 Yes No Yes Yes Yes No TCA9539 400 1110 1xx 16 Yes Yes Yes Yes Yes No TCA9555 400 0100 xxx 16 Yes No Yes Yes Yes No VCC = 2.3 to 5.5 V PCA6107 400 0011 xxx 8 Yes Yes Yes Yes Yes P1P7 bits Yes P0 bit One open drain output; eight push pull outputs PCA9534 400 0100 xxx 8 Yes No Yes Yes Yes No PCA9534 has a different slave address as the PCA9534A, allowing up to 16 devices '9534 type devices on the same I2C bus PCA9534 A 400 0111 xxx 8 Yes No Yes Yes Yes No PCA9534A has a different slave address as the PCA9534, allowing up to 16 devices '9534 type devices on the same I2C bus PCA9535 400 0100 xxx 16 Yes No Yes Yes Yes No PCA9536 400 1000 001 4 No No Yes Yes Yes No PCA9538 400 1110 0xx 8 Yes Yes Yes Yes Yes No PCA9539 400 1110 1xx 16 Yes Yes Yes Yes Yes No PCA9554 400 0100 xxx 8 Yes No Yes Yes Yes No PCA9554 A 400 0111 xxx 8 Yes No Yes Yes Yes No PCA9555 400 0100 xxx 16 Yes No Yes Yes Yes No PCA9557 400 0011 xxx 8 No Yes Yes Yes Yes Yes VCC = 2.5 to 6.0 V PCF8574 400 0100 xxx 8 Yes No No Yes Yes No PCA8574 has a different slave address as the PCA8574A, allowing up to 16 devices '9534 type devices on the same I2C bus PCF8574 A 400 0111 xxx 8 Yes No No Yes Yes No PCA8574A has a different slave address as the PCA8574, allowing up to 16 devices '9534 type devices on the same I2C bus VCC = 2.5 to 5.5 V 4 PCF8575 400 0100 xxx 16 Yes No No Yes Yes No PCF8575 C 400 0100 xxx 16 Yes No No Yes No Yes Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 6 Pin Configuration and Functions 14 4 13 5 12 6 11 7 10 8 9 A2 1 A1 A0 VCC S DA VCC 16 15 14 13 12 SCL P0 2 11 INT P1 3 10 P7 P2 4 9 P6 5 6 7 8 A2 P0 P1 P2 16 15 14 13 12 SCL 11 INT 2 3 10 P7 1 9 P6 4 5 6 7 8 P3 GND P4 P5 3 VCC SDA SCL INT P7 P6 P5 P4 P5 15 P4 16 2 GND 1 P3 A0 A1 A2 P0 P1 P2 P3 GND RGT PACKAGE (TOP VIEW) SDA A1 RGV PACKAGE (TOP VIEW) A0 DB, DGV, DW, OR PW PACKAGE (TOP VIEW) Pin Functions PIN NAME SOIC (DW), SSOP (DB), TSSOP (PW), AND TVSOP (DGV) QFN (RGT AND RGV) A0 1 15 Address input. Connect directly to VCC or ground. A1 2 16 Address input. Connect directly to VCC or ground. A2 3 1 Address input. Connect directly to VCC or ground. P0 4 2 P-port input/output. Push-pull design structure. P1 5 3 P-port input/output. Push-pull design structure. P2 6 4 P-port input/output. Push-pull design structure. P3 7 5 P-port input/output. Push-pull design structure. GND 8 6 Ground P4 9 7 P-port input/output. Push-pull design structure. P5 10 8 P-port input/output. Push-pull design structure. P6 11 9 P-port input/output. Push-pull design structure. P7 12 10 P-port input/output. Push-pull design structure. DESCRIPTION INT 13 11 Interrupt output. Connect to VCC through a pullup resistor. SCL 14 12 Serial clock bus. Connect to VCC through a pullup resistor. SDA 15 13 Serial data bus. Connect to VCC through a pullup resistor. VCC 16 14 Supply voltage Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 5 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range -0.5 6 UNIT V (2) -0.5 6 V -0.5 6 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 -20 mA IOK Output clamp current VO < 0 -20 mA IIOK Input/output clamp current VO < 0 or VO > VCC 20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC -50 mA ICC (2) (3) -250 Continuous current through VCC 160 Package thermal impedance (3) JA (1) Continuous current through GND DB package 82 DGV package 86 DW package 46 PW package 88 RGT package TBD RGV package 51 V mA C/W Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. 7.2 Handling Ratings MIN Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MAX UNIT -65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 C V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN MAX 2.3 5.5 0.7 x VCC 5.5 2 5.5 SCL, SDA -0.5 0.3 x VCC A0, A1, A2, P7-P0 -0.5 0.8 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current P7-P0 -10 mA IOL Low-level output current P7-P0 25 mA TA Operating free-air temperature 85 C 6 SCL, SDA A0, A1, A2, P7-P0 -40 Submit Documentation Feedback V V V Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 7.4 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = -18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 IOH = -8 mA P-port high-level output voltage (2) VOH IOH = -10 mA SDA VOL = 0.4 V VOL = 0.5 V P port (3) IOL VOL = 0.7 V INT SCL, SDA II A0, A1, A2 VCC MIN 2.3 V to 5.5 V -1.2 VPOR 2.3 V 1.8 3V 2.6 4.5 V 4.1 4.75 V 4.1 2.3 V 1.7 3V 2.5 TYP (1) MAX 1.5 1.65 UNIT V V V 4.5 V 4 4.75 V 4 2.3 V to 5.5 V 3 8 2.3 V 8 10 3V 8 14 4.5 V 8 17 4.75 V 8 35 2.3 V 10 13 3V 10 19 4.5 V 10 24 4.75 V 10 45 VOL = 0.4 V 2.3 V to 5.5 V 3 10 VI = VCC or GND 2.3 V to 5.5 V mA 1 1 A IIH P port VI = VCC 2.3 V to 5.5 V 1 A IIL P port VI = GND 2.3 V to 5.5 V -1 A VI = VCC or GND, IO = 0, I/O = inputs, fscl = 400 kHz Operating mode VI = VCC or GND, IO = 0, I/O = inputs, fscl = 100 kHz ICC Standby mode ICC Ci Cio (1) (2) (3) Additional current in standby mode SCL SDA P port VI = GND, IO = 0, I/O = inputs, fscl = 0 kHz One input at VCC - 0.6 V, Other inputs at VCC or GND All LED I/Os at VI = 4.3 V, fscl = 0 kHz VI = VCC or GND VIO = VCC or GND 5.5 V 104 175 3.6 V 50 90 2.7 V 20 65 5.5 V 60 150 3.6 V 15 40 2.7 V 8 20 5.5 V 0.25 1 3.6 V 0.2 0.9 2.7 V 0.1 0.8 2.3 V to 5.5 V A 1.5 mA 5.5 V 1 2.3 V to 5.5 V 2.3 V to 5.5 V 4 5 5.5 6.5 8 9.5 pF pF All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. The total current sourced by all I/Os must be limited to 85 mA. Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7-P0) must be limited to a maximum current of 200 mA. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 7 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com 7.5 I2C Interface Timing Requirements over operating free-air temperature range (unless otherwise noted) (see Figure 14) STANDARD MODE I2C BUS MIN MAX 100 fscl I2C clock frequency 0 tsch I2C clock high time 4 2 tscl I C clock low time tsp I2C spike time tsds I2C serial-data setup time FAST MODE I2C BUS UNIT MIN MAX 0 400 4.7 s 1.3 50 50 250 2 100 0 kHz s 0.6 ns ns tsdh I C serial-data hold time ticr I2C input rise time 1000 20 + 0.1Cb (1) 0 300 ns ticf I2C input fall time 300 20 + 0.1Cb (1) 300 ns tocf I2C output fall time 300 20 + 0.1Cb (1) 300 ns 10-pF to 400-pF bus 2 ns tbuf I C bus free time between stop and start 4.7 1.3 s tsts I2C Start or repeated Start condition setup 4.7 0.6 s tsth I2C Start or repeated Start condition hold 4 0.6 s 2 4 0.6 s tvd(data) Valid data time SCL low to SDA output valid 300 50 ns tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.3 Cb I2C bus capacitive load tsps (1) I C Stop condition setup 3.45 0.1 400 0.9 s 400 ns Cb = total capacitive of one bus in pF 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 15 and Figure 16) PARAMETER FROM (INPUT) TO (OUTPUT) P port INT STANDARD MODE I2C BUS MIN MAX FAST MODE I2C BUS MIN UNIT MAX 4 s 4 4 s 200 200 ns tiv Interrupt valid time tir Interrupt reset delay time SCL INT tpv Output data valid SCL P7-P0 tps Input data setup time P port SCL 100 100 ns tph Input data hold time P port SCL 1 1 s 8 Submit Documentation Feedback 4 Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 7.7 Typical Characteristics 35 55 50 VCC = 5 V 30 40 f SCL = 400 kHz I/Os unloaded 35 30 25 VCC = 3.3 V 20 15 VCC = 2.5 V 10 VCC = 5 V ICC - Supply Current - nA ICC - Supply Current - A 45 25 VCC = 3.3 V 20 15 VCC = 2.5 V 10 5 5 SCL = VCC 0 -40 -15 10 35 60 0 -40 85 -15 TA - Free-Air Temperature - C Figure 1. Supply Current vs Temperature 35 60 85 Figure 2. Quiescent Supply Current vs Temperature 600 70 f SCL = 400 kHz I/Os unloaded 60 VCC = 5 V 550 500 450 ICC - Supply Current - A ICC - Supply Current - A 10 TA - Free-Air Temperature - C 50 40 30 20 400 TA = -40C 350 300 TA = 25C 250 200 TA = 85C 150 100 10 50 0 0 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 1 2 3 4 5 6 7 8 5.5 Number of I/Os Held Low VCC - Supply Voltage - V Figure 3. Supply Current vs Supply Voltage Figure 4. Supply Current vs Number Of I/Os Held Low 30 300 250 VCC = 2.5 V VCC = 2.5 V, ISINK = 10 mA 25 ISINK - I/O Sink Current - mA VOL - Output Low Voltage - mV 275 225 200 175 150 VCC = 5 V, ISINK = 10 mA 125 100 75 VCC = 2.5 V, ISINK = 1 mA 50 TA = -40C 20 TA = 25C 15 TA = 85C 10 VCC = 5 V, ISINK = 1 mA 5 25 0 -40 0 -15 10 35 60 0.0 85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TA - Free-Air Temperature - C VOL - Output Low Voltage - V Figure 5. I/O Output Low Voltage vs Temperature Figure 6. I/O Sink Current vs Output Low Voltage Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 9 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Typical Characteristics (continued) 60 40 VCC = 3.3 V VCC = 5 V 55 35 50 ISINK - I/O Sink Current - mA ISINK - I/O Sink Current - mA TA = -40C 30 25 TA = 25C 20 15 TA = 85C 10 45 TA = -40C 40 35 TA = 25C 30 25 TA = 85C 20 15 10 5 5 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VOL - Output Low Voltage - V VOL - Output Low Voltage - V Figure 7. I/O Sink Current vs Output Low Voltage Figure 8. I/O Sink Current vs Output Low Voltage 35 275 VCC = 2.5 V VCC = 2.5 V, IOL = 10 mA ISOURCE - I/O Source Current - mA (V CC - V OH ) - Output High Voltage - mV 250 225 200 175 150 125 VCC = 5 V, IOL = 10 mA 100 75 VCC = 2.5 V, IOL = 1 mA 50 VCC = 5 V, IOL = 1 mA 30 TA = -40C 25 TA = 25C 20 15 10 25 TA = 85C 5 0 0 -40 0.0 -15 10 35 60 85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (VCC - VOH) - Output High Voltage - V TA - Free-Air Temperature - C Figure 10. I/O Source Current vs Output High Voltage Figure 9. I/O Output High Voltage vs Temperature 75 70 50 ISOURCE - I/O Source Current - mA 40 ISOURCE - I/O Source Current - mA VCC = 3.3 V 45 TA = -40C 35 TA = 25C 30 25 20 TA = 85C 15 10 5 TA = -40C 45 40 35 30 TA = 25C TA = 85C 25 20 15 10 5 0 0 0.0 10 VCC = 5 V 65 60 55 50 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (VCC - VOH) - Output High Voltage - V (VCC - VOH) - Output High Voltage - V Figure 11. I/O Source Current vs Output High Voltage Figure 12. I/O Source Current vs Output High Voltage Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 Typical Characteristics (continued) 6 TA = 25C VOH - Output High Voltage - V 5 4 IOH = -8 mA 3 IOH = -10 mA 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VCC - Supply Voltage - V Figure 13. Output High Voltage vs Supply Voltage Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 11 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com 8 Parameter Measurement Information VCC R L = 1 kW SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Address Start Address Condition Condition Bit 7 Bit 6 (P) (S) (MSB) R/W Bit 0 (LSB) Address Bit 1 tscl ACK (A) Data Bit 07 (MSB) Data Bit 10 (LSB) Stop Condition (P) tsch 0.7 VCC SCL 0.3 VCC ticr tPHL ticf tbuf tsts tPLH tsp 0.7 VCC SDA 0.3 VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I C address 2, 3 P-port data 2 A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 14. I2C Interface Load Circuit And Voltage Waveforms 12 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 Parameter Measurement Information (continued) VCC RL = 4.7 k INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 0 1 0 0 A2 A1 A0 1 A 1 2 3 4 A 5 6 7 8 Data 1 ACK From Slave Data From Port A Data 2 1 P A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 x VCC INT 0.3 x VCC SCL Data 2 0.7 x VCC R/W tiv A 0.3 x VCC tir 0.7 x VCC Pn 0.7 x VCC INT 0.3 x VCC 0.3 x VCC View A-A View B-B A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 15. Interrupt Load Circuit And Voltage Waveforms Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 13 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Parameter Measurement Information (continued) 500 W Pn 2 x VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 x VCC SCL P0 A P3 0.3 x VCC Slave ACK III III III III III SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 x VCC SCL P0 A tps P3 0.3 x VCC tph 0.7 x VCC Pn 0.3 x VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 16. P-Port Load Circuit And Voltage Waveforms 14 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 9 Detailed Description 9.1 Functional Block Diagram INT A0 A1 A2 SCL SDA 13 Interrupt Logic LP Filter 1 2 P7-P0 3 14 15 I2C Bus Control Input Filter Shift Register 8 Bits I/O Port Write Pulse VCC GND 16 8 Power-On Reset Read Pulse A. Pin numbers shown are for DB, DGV, DW, or PW package. B. All I/Os are set to inputs at reset. Figure 17. Logic Diagram (Positive Logic) Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 15 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Functional Block Diagram (continued) Data From Shift Register Data From Shift Register Output Port Register Data Configuration Register VCC Q1 Q D FF Write Configuration Pulse Q D CK Q FF Write Pulse P0 to P7 CK Q Q2 Output Port Register Input Port Register GND Input Port Register Data Q D FF Read Pulse CK Q Data From Shift Register D Write Polarity Pulse CK Q ESD Protection Diode To INT Polarity Register Data Q FF Polarity Inversion Register A. At power-on reset, all registers return to default values. Figure 18. Simplified Schematic of P0 to P7 9.2 Device Functional Modes 9.2.1 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9534 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the PCA9534 registers and I2C/SMBus state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. Refer to the Power-On Reset Errata section. 9.2.2 I/O Port When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. 16 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 Device Functional Modes (continued) 9.2.3 Interrupt Output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa. The INT output has an open-drain structure and requires pullup resistor to VCC. 9.2.3.1 Interrupt Errata Description The INT will be improperly de-asserted if the following two conditions occur: 1. The last I2C command byte (register pointer) written to the device was 00h. NOTE This generally means the last operation with the device was a Read of the input register. However, the command byte may have been written with 00h without ever going on to read the input register. After reading from the device, if no other command byte written, it will remain 00h. 2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high System Impact Can cause improper interrupt handling as the Master will see the interrupt as being cleared. System Workaround Minor software change: User must change command byte to something besides 00h after a Read operation to the PCA9534 device or before reading from another slave device. NOTE Software change will be compatible with other versions (competition and TI redesigns) of this device. 9.3 Programming 9.3.1 I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 19). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0-A2) of the slave device must not be changed between the Start and Stop conditions. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 17 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Programming (continued) On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 20). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 19). Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Start Condition Stop Condition Figure 19. Definition Of Start And Stop Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 20. Bit Transfer 18 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 Programming (continued) Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 21. Acknowledgment On I2C Bus 9.3.2 Register Map Table 1. Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L A2 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0 I2C slave address Px I/O data bus 9.3.2.1 Device Address Figure 22 shows the address byte of the PCA9534. Slave Address 0 1 0 Fixed 0 A2 A1 A0 R/W Hardware Selectable Figure 22. Pca9534 Address Table 2. Address Reference INPUTS A0 I2C BUS SLAVE ADDRESS A2 A1 L L L 32 (decimal), 20 (hexadecimal) L L H 33 (decimal), 21 (hexadecimal) L H L 34 (decimal), 22 (hexadecimal) L H H 35 (decimal), 23 (hexadecimal) H L L 36 (decimal), 24 (hexadecimal) H L H 37 (decimal), 25 (hexadecimal) H H L 38 (decimal), 26 (hexadecimal) H H H 39 (decimal), 27 (hexadecimal) Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 19 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation. 9.3.2.2 Control Register And Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the PCA9534. Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. 0 0 0 0 0 0 B1 B0 Figure 23. Control Register Bits Table 3. Command Byte CONTROL REGISTER BITS COMMAND BYTE (HEX) REGISTER POWER-UP DEFAULT PROTOCOL B1 B0 0 0 0x00 Input Port Read byte xxxx xxxx 0 1 0x01 Output Port Read/write byte 1111 1111 1 0 0x02 Polarity Inversion Read/write byte 0000 0000 1 1 0x03 Configuration Read/write byte 1111 1111 9.3.2.3 Register Descriptions The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the Input Port register will be accessed next. Table 4. Register 0 (Input Port Register) BIT I7 I6 I5 I4 I3 I2 I1 I0 DEFAULT X X X X X X X X The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 5. Register 1 (Output Port Register) BIT O7 O6 O5 O4 O3 O2 O1 O0 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. Table 6. Register 2 (Polarity Inversion Register) 20 BIT N7 N6 N5 N4 N3 N2 N1 N0 DEFAULT 0 0 0 0 0 0 0 0 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7. Register 3 (Configuration Register) BIT C7 C6 C5 C4 C3 C2 C1 C0 DEFAULT 1 1 1 1 1 1 1 1 9.3.2.4 Bus Transactions Data is exchanged between the master and PCA9534 through write and read commands. 9.3.2.4.1 Writes Data is transmitted to the PCA9534 by sending the device address and setting the least significant bit (LSB) to a logic 0 (see Figure 22 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte (see Figure 24 and Figure 25). There is no limitation on the number of data bytes sent in one write transmission. SCL 1 2 3 4 5 6 7 8 9 Slave Address S SDA 0 1 0 Command Byte 0 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A Data 1 A P ACK From Slave ACK From Slave R/W ACK From Slave Start Condition Data to Port Write to Port Data Out From Port Data 1 Valid tpv Figure 24. Write To Output Port Register <br/> SCL 1 2 3 4 5 6 7 8 9 Slave Address SDA S 0 1 0 Start Condition Command Byte 0 A2 A1 A0 0 R/W A 0 0 0 0 ACK From Slave 0 0 Data to Register 1 1/0 A Data ACK From Slave A P ACK From Slave Data to Register Figure 25. Write To Configuration Or Polarity Inversion Registers Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 21 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com 9.3.2.4.2 Reads The bus master first must send the PCA9534 address with the LSB set to a logic 0 (see Figure 22 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9534 (see Figure 26 and Figure 27). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. S 0 1 0 ACK From Slave ACK From Slave Slave Address 0 A2 A1 A0 0 Command Byte A A S 0 ACK From ACK From Master Slave Data From Register Slave Address 1 0 Data 0 A2 A1 A0 1 A A R/W R/W Data From Register NACK From Master Data NA P Last Byte Figure 26. Read From Register <br/> 1 SCL 2 3 4 5 6 7 8 9 Data From Port Slave Address S 0 SDA 1 0 0 A2 A1 A0 1 Start Condition R/W Data 1 A Data From Port Data 4 A ACK From Master ACK From Slave NA P NACK From Master Stop Condition Read From Port Data Into Port Data 2 tph Data 3 Data 4 Data 5 tps INT tiv tir A. This figure assumes that the command byte has previously been programmed with 00h. B. Transfer of data can be stopped at any moment by a Stop condition. C. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address call and the actual data transfer from the P Port. See Figure 26 for these details. Figure 27. Read Input Port Register 22 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 10 Application And Implementation 10.1 Typical Application Figure 28 shows an application in which the PCA9534 can be used. VCC (5 V) 10 kW VCC Master Controller 10 kW 10 kW 2 kW 10 kW SDA VCC SDA SCL SCL INT INT P0 P1 100 kW (y3) Subsystem 1 (e.g., Temperature Sensor) INT P2 RESET GND P3 Subsystem 2 (e.g., Counter) PCA9534 P4 A P5 A2 Controlled Device (e.g., CBT Device) P6 ENABLE A1 P7 B A0 GND ALARM Subsystem 3 (e.g., Alarm System) VCC A. Device address is configured as 0100100 for this example. B. P0, P2, and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. P6 and P7 are not used and must be configured as outputs. Figure 28. Typical Application Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 23 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Typical Application (continued) 10.1.1 Design Requirements 10.1.1.1 Minimizing ICC When The I/O Controls Leds When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor, as shown in Figure 28. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ICC in Electrical Characteristics. For battery-powered applications, it is essential that the voltage of the I/O pins is greater than or equal to VCC when the LED is off to minimize current consumption. Figure 29 shows a high-value resistor in parallel with the LED. Figure 30 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevents additional supply-current consumption when the LED is off. VCC LED 100 kW VCC LEDx Figure 29. High-Value Resistor In Parallel With The Led 3.3 V VCC 5V LED LEDx Figure 30. Device Supplied By A Lower Voltage 24 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 11 Power Supply Recommendations 11.1 Power-On Reset Requirements In the event of a glitch or data corruption, PCA9534 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 31 and Figure 32. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 31. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 32. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC Table 8 specifies the performance of the power-on reset feature for PCA9534 for both types of power-on reset. Table 8. Recommended Supply Sequencing And Ramp Rates (1) MAX UNIT VCC_FT Fall rate PARAMETER See Figure 31 1 100 ms VCC_RT Rise rate See Figure 31 0.01 100 ms VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 31 0.001 ms VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN - 50 mV) See Figure 32 0.001 ms VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 s See Figure 33 VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 x VCCx See Figure 33 VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V (1) MIN TYP 1.2 V s TA = -40C to 85C (unless otherwise noted) Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 25 PCA9534 SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 www.ti.com Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 33 and Table 8 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 33. Glitch Width And Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 34 and Table 8 provide more details on this specification. VCC VPOR VPORF Time POR Time Figure 34. VPOR 11.2 Power-On Reset Errata A power-on reset condition can be missed if the VCC ramps are outside specification listed above. System Impact If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock up. 26 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 PCA9534 www.ti.com SCPS124G - SEPTEMBER 2006 - REVISED JUNE 2014 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: PCA9534 27 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) PCA9534DB ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD534 PCA9534DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD534 PCA9534DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD534 PCA9534DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9534 PCA9534DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9534 PCA9534DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9534 PCA9534PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD534 PCA9534PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD534 PCA9534RGVR ACTIVE VQFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD534 PCA9534RGVRG4 ACTIVE VQFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD534 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Aug-2018 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 PCA9534DBR SSOP DB 16 2000 330.0 16.4 PCA9534DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 PCA9534DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PCA9534PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 8.2 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9534DBR SSOP DB 16 2000 367.0 367.0 38.0 PCA9534DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 PCA9534DWR SOIC DW 16 2000 367.0 367.0 38.0 PCA9534PWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height SMALL OUTLINE INTEGRATED CIRCUIT Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4040000-2/H PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 1.27 16 1 2X 8.89 10.5 10.1 NOTE 3 8 9 0.51 0.31 0.25 C A B 16X B 7.6 7.4 NOTE 4 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0.1 0 -8 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE DETAILS SYMM 16 1 16X (0.6) SYMM 14X (1.27) 9 8 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK OPENING SOLDER MASK OPENING 0.07 MAX ALL AROUND METAL 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 9 8 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. 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