SCLS177D – MARCH 1984 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperating Voltage Range of 4.5 V to 5.5 V
DHigh-Current 3-State Noninverting Outputs
Drive Bus Lines Directly or Up To 15 LSTTL
Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 22 ns
D±6-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DInputs Are TTL-Voltage Compatible
DBus-Structured Pinout
description/ordering information
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
bus driving. The ’HCT574 devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74HCT574N SN74HCT574N
SOIC DW
Tube SN74HCT574DW
HCT574
SOIC – DW Tape and reel SN74HCT574DWR HCT574
–40°C to 85°CSOP – NS Tape and reel SN74HCT574NSR HCT574
40 C
to
85 C
SSOP – DB Tape and reel SN74HCT574DBR HT574
TSSOP PW
Tube SN74HCT574PW
HT574
TSSOP – PW Tape and reel SN74HCT574PWR HT574
CDIP – J Tube SNJ54HCT574J SNJ54HCT574J
–55°C to 125°CCFP – W Tube SNJ54HCT574W SNJ54HCT574W
55 C
to
125 C
LCCC – FK Tube SNJ54HCT574FK SNJ54HCT574FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q V
1Q
8D
GND
CLK
SN54HCT574 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HCT574 ...J OR W PACKAGE
SN74HCT574 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SCLS177D – MARCH 1984 – REVISED DECEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D
OUTPUT
Q
L↑H H
L↑LL
LH or L X Q0
H X X Z
logic diagram (positive logic)
OE
CLK
1D 1Q
1
11
219
To Seven Other Channels
1D
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS177D – MARCH 1984 – REVISED DECEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT574 SN74HCT574
UNIT
MIN NOM MAX MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
∆t/∆vInput transition rise/fall time 500 500 ns
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54HCT574 SN74HCT574
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
V
VVorV
IOH = –20 µA
45V
4.4 4.499 4.4 4.4
V
VOH VI = VIH or VIL IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84 V
V
VVorV
IOL = 20 µA
45V
0.001 0.1 0.1 0.1
V
VOL VI = VIH or VIL IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 V
IIVI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆ICC†One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA
Ci4.5 V
to 5.5 V 3 10 10 10 pF
†This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
TA = 25°C SN54HCT574 SN74HCT574
UNIT
VCC MIN MAX MIN MAX MIN MAX UNIT
f
Clock freq enc
4.5 V 30 20 24
MH
fclock Clock frequency 5.5 V 33 22 27 MHz
t
P lse d ration CLK high or lo
4.5 V 16 24 20
ns
twPulse duration, CLK high or low 5.5 V 14 22 18 ns
t
St ti dt bf CLK↑
4.5 V 20 30 25
ns
tsu Setup time, data before CLK↑5.5 V 17 27 23 ns
th
Hold time data after CLK↑
4.5 V 555
ns
thHold time, data after CLK↑5.5 V 555ns
SCLS177D – MARCH 1984 – REVISED DECEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
V
TA = 25°C SN54HCT574 SN74HCT574
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT
f
4.5 V 30 36 20 24
MH
fmax 5.5 V 33 40 22 27 MHz
t
CLK
Any Q
4.5 V 30 36 54 45
ns
tpd CLK Any Q 5.5 V 25 32 48 41 ns
t
OE
An Q
4.5 V 26 30 45 38
ns
ten OE Any Q 5.5 V 23 27 41 34 ns
t
OE
An Q
4.5 V 23 30 45 38
ns
tdis OE Any Q 5.5 V 22 27 41 34 ns
tt
Any Q
4.5 V 10 12 18 15
ns
ttAny Q 5.5 V 911 16 14 ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
V
TA = 25°C SN54HCT574 SN74HCT574
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT
f
4.5 V 30 36 20 24
MH
fmax 5.5 V 33 40 22 27 MHz
t
CLK
An Q
4.5 V 40 53 80 66
ns
tpd CLK Any Q 5.5 V 35 47 71 60 ns
t
OE
An Q
4.5 V 34 47 71 59
ns
ten OE Any Q 5.5 V 29 39 94 78 ns
tt
Any Q
4.5 V 18 42 63 53
ns
ttAny Q 5.5 V 16 38 57 48 ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 93 pF
SCLS177D – MARCH 1984 – REVISED DECEMBER 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
1.3 V
1.3 V1.3 V 0.3 V0.3 V 2.7 V 2.7 V
3 V
3 V
0 V
0 V
trtf
Reference
Input
Data
Input
1.3 V
High-Level
Pulse 1.3 V 3 V
0 V
1.3 V 1.3 V
3 V
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V 10%10% 90% 90%
3 V
VOH
VOL
0 V
trtf
Input
In-Phase
Output
1.3 V
tPLH tPHL
1.3 V 1.3 V
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
1.3 V
1.3 V
tPZH tPHZ
Output
Waveform 2
(See Note B)
Test
Point
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open––
CL
(see Note A)
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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