SCLS177D - MARCH 1984 - REVISED DECEMBER 2002 D Operating Voltage Range of 4.5 V to 5.5 V D High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 22 ns 6-mA Output Drive at 5 V Low Input Current of 1 A Max Inputs Are TTL-Voltage Compatible Bus-Structured Pinout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. The 'HCT574 devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 2D 1D SN54HCT574 . . . FK PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE VCC 1Q D D D D D D SN54HCT574 . . . J OR W PACKAGE SN74HCT574 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION PDIP - N SN74HCT574N Tube SN74HCT574DW Tape and reel SN74HCT574DWR SOP - NS Tape and reel SN74HCT574NSR HCT574 SSOP - DB Tape and reel SN74HCT574DBR HT574 Tube SN74HCT574PW Tape and reel SN74HCT574PWR CDIP - J Tube SNJ54HCT574J SNJ54HCT574J CFP - W Tube SNJ54HCT574W SNJ54HCT574W TSSOP - PW -55C 55 C to 125 125C C TOP-SIDE MARKING Tube SOIC - DW -40C 40 C to 85C 85 C ORDERABLE PART NUMBER PACKAGE TA SN74HCT574N HCT574 HT574 LCCC - FK Tube SNJ54HCT574FK SNJ54HCT574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated !"#$ $%$ $&'"%$ !''#$ % & (!)* %$ %#+ '! $&'" (# & %$ (#' # #'" & #,% $'!"#$ %$%' -%''%$.+ '! $ (' #$/ # $ $# #%'*. $ *!# #$/ & %** (%'%"##'+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS177D - MARCH 1984 - REVISED DECEMBER 2002 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L H H L L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS177D - MARCH 1984 - REVISED DECEMBER 2002 recommended operating conditions (see Note 3) SN54HCT574 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO t/v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT574 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.8 V VCC VCC V 500 ns V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = -20 A IOH = -6 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 A IOL = 6 mA 45V 4.5 II IOZ VI = VCC or 0 VO = VCC or 0 ICC VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V ICC MIN SN54HCT574 MIN MAX SN74HCT574 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 5.5 V 0.1 100 1000 1000 nA 5.5 V 0.01 0.5 10 5 A 8 160 80 A 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 4.5 V to 5.5 V Ci TA = 25C TYP MAX V This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) fclock Clock frequency freq enc tw P lse duration, Pulse d ration CLK high or lo low tsu S t titime, d Setup data t b before f CLK th Hold time, time data after CLK TA = 25C MIN MAX SN54HCT574 VCC 4.5 V 30 20 24 5.5 V 33 22 27 MIN MAX SN74HCT574 MIN 4.5 V 16 24 20 5.5 V 14 22 18 4.5 V 20 30 25 5.5 V 17 27 23 4.5 V 5 5 5 5.5 V 5 5 5 MAX UNIT MH MHz ns ns ns 0 $&'"%$ $ #'$ ('! $ # &'"%1# ' #/$ (%# & #1#*("#$+ %'% #' %% %$ #' (# & %$ %'# #/$ /%*+ #,% $'!"#$ '##'1# # '/ %$/# ' $$!# ## ('! -! $ #+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS177D - MARCH 1984 - REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK Any Q ten OE An Q Any tdis OE An Q Any tt Any Q TA = 25C TYP MAX SN54HCT574 SN74HCT574 VCC MIN 4.5 V 30 36 20 24 5.5 V 33 40 22 27 MIN MAX MIN MAX UNIT MH MHz 4.5 V 30 36 54 45 5.5 V 25 32 48 41 4.5 V 26 30 45 38 5.5 V 23 27 41 34 4.5 V 23 30 45 38 5.5 V 22 27 41 34 4.5 V 10 12 18 15 5.5 V 9 11 16 14 ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK An Q Any ten OE An Q Any tt Any Q TA = 25C TYP MAX SN54HCT574 SN74HCT574 VCC MIN 4.5 V 30 36 20 24 5.5 V 33 40 22 27 MIN MAX MIN MAX UNIT MH MHz 4.5 V 40 53 80 66 5.5 V 35 47 71 60 4.5 V 34 47 71 59 5.5 V 29 39 94 78 4.5 V 18 42 63 53 5.5 V 16 38 57 48 ns ns ns operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per flip-flop No load 0 $&'"%$ $ #'$ ('! $ # &'"%1# ' #/$ (%# & #1#*("#$+ %'% #' %% %$ #' (# & %$ %'# #/$ /%*+ #,% $'!"#$ '##'1# # '/ %$/# ' $$!# ## ('! -! $ #+ 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TYP 93 UNIT pF SCLS177D - MARCH 1984 - REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC ten RL tdis CL (see Note A) RL tPZH S1 Test Point From Output Under Test PARAMETER S2 1 k tPZL tPHZ tPLZ tpd or tt 1 k CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF 50 pF or 150 pF -- LOAD CIRCUIT 3V High-Level Pulse 1.3 V 3V Reference Input 1.3 V 0V 1.3 V tsu 0V tw Data Input 1.3 V 0.3 V 3V Low-Level Pulse 1.3 V 1.3 V Output Control (Low-Level Enabling) 3V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH 1.3 V 10% V OL tf 1.3 V 10% tf 3V 1.3 V 0.3 V 0 V tf 3V 1.3 V 1.3 V 0V tPZL Output Waveform 1 (See Note B) tPLZ VCC 1.3 V 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES Output Waveform 2 (See Note B) VOL tPHZ tPZH tPLH 1.3 V 10% 2.7 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 2.7 V tr 0V Input th 1.3 V 90% VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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